From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: Jakub Jelinek <jakub@redhat.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
richard.sandiford@arm.com
Subject: Re: [PATCH] aarch64: enable mixed-types for aarch64 simdclones
Date: Mon, 16 Oct 2023 16:03:26 +0100 [thread overview]
Message-ID: <6d99ea34-78df-4807-8e83-00695d729517@arm.com> (raw)
In-Reply-To: <48784e1a-b3b3-4b89-8d59-9c25cb943856@arm.com>
[-- Attachment #1: Type: text/plain, Size: 2204 bytes --]
Hey,
Just a minor update to the patch, I had missed the libgomp testsuite, so
had to make some adjustments there too.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (lane_size): New function.
(aarch64_simd_clone_compute_vecsize_and_simdlen): Determine
simdlen according to NDS rule
and reject combination of simdlen and types that lead to
vectors larger than 128bits.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add aarch64 targets to vect_simd_clones.
* c-c++-common/gomp/declare-variant-14.c: Adapt test for aarch64.
* c-c++-common/gomp/pr60823-1.c: Likewise.
* c-c++-common/gomp/pr60823-2.c: Likewise.
* c-c++-common/gomp/pr60823-3.c: Likewise.
* g++.dg/gomp/attrs-10.C: Likewise.
* g++.dg/gomp/declare-simd-1.C: Likewise.
* g++.dg/gomp/declare-simd-3.C: Likewise.
* g++.dg/gomp/declare-simd-4.C: Likewise.
* g++.dg/gomp/declare-simd-7.C: Likewise.
* g++.dg/gomp/declare-simd-8.C: Likewise.
* g++.dg/gomp/pr88182.C: Likewise.
* gcc.dg/declare-simd.c: Likewise.
* gcc.dg/gomp/declare-simd-1.c: Likewise.
* gcc.dg/gomp/declare-simd-3.c: Likewise.
* gcc.dg/gomp/pr87887-1.c: Likewise.
* gcc.dg/gomp/pr87895-1.c: Likewise.
* gcc.dg/gomp/pr89246-1.c: Likewise.
* gcc.dg/gomp/pr99542.c: Likewise.
* gcc.dg/gomp/simd-clones-2.c: Likewise.
* gcc.dg/gcc.dg/vect/vect-simd-clone-1.c: Likewise.
* gcc.dg/gcc.dg/vect/vect-simd-clone-2.c: Likewise.
* gcc.dg/gcc.dg/vect/vect-simd-clone-4.c: Likewise.
* gcc.dg/gcc.dg/vect/vect-simd-clone-5.c: Likewise.
* gcc.dg/gcc.dg/vect/vect-simd-clone-8.c: Likewise.
* gfortran.dg/gomp/declare-simd-2.f90: Likewise.
* gfortran.dg/gomp/declare-simd-coarray-lib.f90: Likewise.
* gfortran.dg/gomp/declare-variant-14.f90: Likewise.
* gfortran.dg/gomp/pr79154-1.f90: Likewise.
* gfortran.dg/gomp/pr83977.f90: Likewise.
libgomp/testsuite/ChangeLog:
* libgomp.c/declare-variant-1.c: Adapt test for aarch64.
* libgomp.fortran/declare-simd-1.f90: Likewise.
[-- Attachment #2: aarch64_simd_clone_mixed4.patch --]
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diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 9fbfc548a891f5d11940c6fd3c49a14bfbdec886..37507f091c2a6154fa944c3a9fad6a655ab5d5a1 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -27414,33 +27414,62 @@ supported_simd_type (tree t)
return false;
}
-/* Return true for types that currently are supported as SIMD return
- or argument types. */
+/* Determine the lane size for the clone argument/return type. This follows
+ the LS(P) rule in the VFABIA64. */
-static bool
-currently_supported_simd_type (tree t, tree b)
+static unsigned
+lane_size (cgraph_simd_clone_arg_type clone_arg_type, tree type)
{
- if (COMPLEX_FLOAT_TYPE_P (t))
- return false;
+ gcc_assert (clone_arg_type != SIMD_CLONE_ARG_TYPE_MASK);
- if (TYPE_SIZE (t) != TYPE_SIZE (b))
- return false;
+ /* For non map-to-vector types that are pointers we use the element type it
+ points to. */
+ if (POINTER_TYPE_P (type))
+ switch (clone_arg_type)
+ {
+ default:
+ break;
+ case SIMD_CLONE_ARG_TYPE_UNIFORM:
+ case SIMD_CLONE_ARG_TYPE_LINEAR_CONSTANT_STEP:
+ case SIMD_CLONE_ARG_TYPE_LINEAR_VARIABLE_STEP:
+ type = TREE_TYPE (type);
+ break;
+ }
- return supported_simd_type (t);
+ /* For types (or types pointers of non map-to-vector types point to) that are
+ integers or floating point, we use their size if they are 1, 2, 4 or 8.
+ */
+ if (INTEGRAL_TYPE_P (type)
+ || SCALAR_FLOAT_TYPE_P (type))
+ switch (TYPE_PRECISION (type) / BITS_PER_UNIT)
+ {
+ default:
+ break;
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ return TYPE_PRECISION (type);
+ }
+ /* For any other we use the size of uintptr_t. For map-to-vector types that
+ are pointers, using the size of uintptr_t is the same as using the size of
+ their type, seeing all pointers are the same size as uintptr_t. */
+ return POINTER_SIZE;
}
+
/* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */
static int
aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
struct cgraph_simd_clone *clonei,
- tree base_type, int num,
- bool explicit_p)
+ tree base_type ATTRIBUTE_UNUSED,
+ int num, bool explicit_p)
{
tree t, ret_type;
- unsigned int elt_bits, count;
+ unsigned int nds_elt_bits;
+ int count;
unsigned HOST_WIDE_INT const_simdlen;
- poly_uint64 vec_bits;
if (!TARGET_SIMD)
return 0;
@@ -27460,80 +27489,135 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
}
ret_type = TREE_TYPE (TREE_TYPE (node->decl));
+ /* According to AArch64's Vector ABI the type that determines the simdlen is
+ the narrowest of types, so we ignore base_type for AArch64. */
if (TREE_CODE (ret_type) != VOID_TYPE
- && !currently_supported_simd_type (ret_type, base_type))
+ && !supported_simd_type (ret_type))
{
if (!explicit_p)
;
- else if (TYPE_SIZE (ret_type) != TYPE_SIZE (base_type))
- warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
- "GCC does not currently support mixed size types "
- "for %<simd%> functions");
- else if (supported_simd_type (ret_type))
+ else if (COMPLEX_FLOAT_TYPE_P (ret_type))
warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
"GCC does not currently support return type %qT "
- "for %<simd%> functions", ret_type);
+ "for simd", ret_type);
else
warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
- "unsupported return type %qT for %<simd%> functions",
+ "unsupported return type %qT for simd",
ret_type);
return 0;
}
+ auto_vec<std::pair <tree, unsigned int>> vec_elts (clonei->nargs + 1);
+
+ /* We are looking for the NDS type here according to the VFABIA64. */
+ if (TREE_CODE (ret_type) != VOID_TYPE)
+ {
+ nds_elt_bits = lane_size (SIMD_CLONE_ARG_TYPE_VECTOR, ret_type);
+ vec_elts.safe_push (std::make_pair (ret_type, nds_elt_bits));
+ }
+ else
+ nds_elt_bits = POINTER_SIZE;
+
int i;
tree type_arg_types = TYPE_ARG_TYPES (TREE_TYPE (node->decl));
bool decl_arg_p = (node->definition || type_arg_types == NULL_TREE);
-
for (t = (decl_arg_p ? DECL_ARGUMENTS (node->decl) : type_arg_types), i = 0;
t && t != void_list_node; t = TREE_CHAIN (t), i++)
{
tree arg_type = decl_arg_p ? TREE_TYPE (t) : TREE_VALUE (t);
-
if (clonei->args[i].arg_type != SIMD_CLONE_ARG_TYPE_UNIFORM
- && !currently_supported_simd_type (arg_type, base_type))
+ && !supported_simd_type (arg_type))
{
if (!explicit_p)
;
- else if (TYPE_SIZE (arg_type) != TYPE_SIZE (base_type))
+ else if (COMPLEX_FLOAT_TYPE_P (ret_type))
warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
- "GCC does not currently support mixed size types "
- "for %<simd%> functions");
+ "GCC does not currently support argument type %qT "
+ "for simd", arg_type);
else
warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
- "GCC does not currently support argument type %qT "
- "for %<simd%> functions", arg_type);
+ "unsupported argument type %qT for simd",
+ arg_type);
return 0;
}
+ unsigned lane_bits = lane_size (clonei->args[i].arg_type, arg_type);
+ if (clonei->args[i].arg_type == SIMD_CLONE_ARG_TYPE_VECTOR)
+ vec_elts.safe_push (std::make_pair (arg_type, lane_bits));
+ if (nds_elt_bits > lane_bits)
+ nds_elt_bits = lane_bits;
}
clonei->vecsize_mangle = 'n';
clonei->mask_mode = VOIDmode;
- elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type));
+ poly_uint64 simdlen;
+ auto_vec<poly_uint64> simdlens (2);
+ /* Keep track of the possible simdlens the clones of this function can have,
+ and check them later to see if we support them. */
if (known_eq (clonei->simdlen, 0U))
{
- count = 2;
- vec_bits = (num == 0 ? 64 : 128);
- clonei->simdlen = exact_div (vec_bits, elt_bits);
+ simdlen = exact_div (poly_uint64 (64), nds_elt_bits);
+ simdlens.safe_push (simdlen);
+ simdlens.safe_push (simdlen * 2);
}
else
+ simdlens.safe_push (clonei->simdlen);
+
+ clonei->vecsize_int = 0;
+ clonei->vecsize_float = 0;
+
+ /* We currently do not support generating simdclones where vector arguments
+ do not fit into a single vector register, i.e. vector types that are more
+ than 128-bits large. This is because of how we currently represent such
+ types in ACLE, where we use a struct to allow us to pass them as arguments
+ and return.
+ Hence why we have to check whether the simdlens available for this
+ simdclone would cause a vector type to be larger than 128-bits, and reject
+ such a clone. */
+ count = simdlens.length ();
+ int j = 0;
+ while (j < count && !simdlens.is_empty ())
+ {
+ bool remove_simdlen = false;
+ for (auto elt : vec_elts)
+ if (known_gt (simdlens[j] * elt.second, 128U))
+ {
+ /* Don't issue a warning for every simdclone when there is no
+ specific simdlen clause. */
+ if (explicit_p && known_ne (clonei->simdlen, 0U))
+ warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
+ "GCC does not currently support simdlen %wd for "
+ "type %qT",
+ constant_lower_bound (simdlens[j]), elt.first);
+ remove_simdlen = true;
+ break;
+ }
+ if (remove_simdlen)
+ {
+ count--;
+ simdlens.ordered_remove (j);
+ }
+ else
+ j++;
+ }
+
+ count = simdlens.length ();
+ if (count == 0)
{
- count = 1;
- vec_bits = clonei->simdlen * elt_bits;
- /* For now, SVE simdclones won't produce illegal simdlen, So only check
- const simdlens here. */
- if (clonei->simdlen.is_constant (&const_simdlen)
- && maybe_ne (vec_bits, 64U) && maybe_ne (vec_bits, 128U))
+ if (explicit_p && known_eq (clonei->simdlen, 0U))
{
- if (explicit_p)
- warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
- "GCC does not currently support simdlen %wd for "
- "type %qT",
- const_simdlen, base_type);
- return 0;
+ /* Warn the user if we can't generate any simdclone. */
+ simdlen = exact_div (poly_uint64 (64), nds_elt_bits);
+ warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
+ "GCC does not currently support a simdclone with simdlens"
+ " %wd and %wd for these types.",
+ constant_lower_bound (simdlen),
+ constant_lower_bound (simdlen*2));
}
+ return 0;
}
- clonei->vecsize_int = vec_bits;
- clonei->vecsize_float = vec_bits;
+
+ gcc_assert (num < count);
+ clonei->simdlen = simdlens[num];
return count;
}
diff --git a/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c b/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c
index cdb0bb34f505bc9bd82a14b57d35138800bc4523..e3668893afe33a58c029cddd433d9bf43cce2bfa 100644
--- a/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c
+++ b/gcc/testsuite/c-c++-common/gomp/declare-variant-14.c
@@ -15,13 +15,15 @@ int
test1 (int x)
{
/* At gimplification time, we can't decide yet which function to call. */
- /* { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" } } */
+ /* { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" { target { !aarch64*-*-* } } } } */
/* After simd clones are created, the original non-clone test1 shall
call f03 (score 6), the sse2/avx/avx2 clones too, but avx512f clones
shall call f01 with score 8. */
/* { dg-final { scan-tree-dump-not "f04 \\\(x" "optimized" } } */
- /* { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" } } */
- /* { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" } } */
+ /* { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" { target { !aarch64*-*-* } } } } */
+ /* { dg-final { scan-tree-dump-times "f03 \\\(x" 10 "optimized" { target { aarch64*-*-* } } } } */
+ /* { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" { target { !aarch64*-*-* } } } } */
+ /* { dg-final { scan-tree-dump-times "f01 \\\(x" 0 "optimized" { target { aarch64*-*-* } } } } */
int a = f04 (x);
int b = f04 (x);
return a + b;
diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-1.c b/gcc/testsuite/c-c++-common/gomp/pr60823-1.c
index 2cc44e82c3cffa259003fa5fdbe8edd6b688d23e..9408c0f5bba68551ac3dc14ebf8c84c1d691fbc8 100644
--- a/gcc/testsuite/c-c++-common/gomp/pr60823-1.c
+++ b/gcc/testsuite/c-c++-common/gomp/pr60823-1.c
@@ -2,7 +2,11 @@
/* { dg-do compile } */
/* { dg-options "-O2 -fopenmp-simd" } */
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch
+#else
#pragma omp declare simd simdlen(4) notinbranch
+#endif
int
foo (const double c1, const double c2)
{
@@ -17,4 +21,3 @@ foo (const double c1, const double c2)
}
return res;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-13 } */
diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-2.c b/gcc/testsuite/c-c++-common/gomp/pr60823-2.c
index 4c87620076a0c5961c06d6a5beeb20d9afd2865d..e402b5ab06b35ba8dae19f496a0620f7ccb55858 100644
--- a/gcc/testsuite/c-c++-common/gomp/pr60823-2.c
+++ b/gcc/testsuite/c-c++-common/gomp/pr60823-2.c
@@ -3,7 +3,11 @@
/* { dg-require-effective-target vect_simd_clones } */
/* { dg-options "-O2 -fopenmp-simd" } */
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch
+#else
#pragma omp declare simd simdlen(4) notinbranch
+#endif
__attribute__((noinline)) int
foo (double c1, double c2)
{
diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-3.c b/gcc/testsuite/c-c++-common/gomp/pr60823-3.c
index 56ad50c41f6edeced26deaa57aea592f12c5edb1..44e02b6a2c061e07d59fcbc8e3172600af213eb0 100644
--- a/gcc/testsuite/c-c++-common/gomp/pr60823-3.c
+++ b/gcc/testsuite/c-c++-common/gomp/pr60823-3.c
@@ -9,8 +9,11 @@ void bar (char *, double *);
struct S { char c[sizeof (double)]; };
void baz (struct S, struct S);
union U { struct S s; double d; };
-
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch
+#else
#pragma omp declare simd simdlen(4) notinbranch
+#endif
__attribute__((noinline)) int
foo (double c1, double c2)
{
@@ -28,6 +31,5 @@ foo (double c1, double c2)
baz (*(struct S *)&c1, *(struct S *)&c2);
return c1 + c2 + ((struct S *)&c1)->c[1];
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-16 } */
#endif
diff --git a/gcc/testsuite/g++.dg/gomp/attrs-10.C b/gcc/testsuite/g++.dg/gomp/attrs-10.C
index ed0214a8de235b3c2a6b52336106ac5de754be46..7a968ba8cc242c90ca465a342b068e4c041daa6b 100644
--- a/gcc/testsuite/g++.dg/gomp/attrs-10.C
+++ b/gcc/testsuite/g++.dg/gomp/attrs-10.C
@@ -5,7 +5,11 @@ extern "C" void abort ();
[[omp::directive (declare simd, linear (l))]] extern int f1 (int l);
extern int f2 (int), f3 [[omp::directive (declare simd, uniform (m))]] (int m), f4 (int), z;
+#ifdef __aarch64__
+[[omp::directive (declare simd, linear (l), simdlen(4))]] extern int f5 [[omp::directive (declare simd uniform (l) simdlen (2) notinbranch)]] (int l);
+#else
[[omp::directive (declare simd, linear (l), simdlen(4))]] extern int f5 [[omp::directive (declare simd uniform (l) simdlen (8) notinbranch)]] (int l);
+#endif
int
f1 (int l)
@@ -13,6 +17,11 @@ f1 (int l)
return l;
}
+// { dg-final { scan-assembler-times "_ZGVnN2l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l__Z2f1i:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4l__Z2f1i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4l__Z2f1i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4l__Z2f1i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -28,7 +37,7 @@ f2 (int l)
return l + 1;
}
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f2i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f2i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
int
f3 (int l)
@@ -36,6 +45,11 @@ f3 (int l)
return l + 2;
}
+// { dg-final { scan-assembler-times "_ZGVnN2u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4u__Z2f3i:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4u__Z2f3i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4u__Z2f3i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4u__Z2f3i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -51,14 +65,18 @@ f4 (int l)
return l + 3;
}
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f4i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f4i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
int
f5 (int l)
-{ // { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64*-*-* } .-1 }
+{
return l + 4;
}
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z2f5i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l__Z2f5i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN2u__Z2f5i:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4l__Z2f5i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4l__Z2f5i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4l__Z2f5i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -76,12 +94,21 @@ f5 (int l)
[[omp::directive (declare simd, linear (l), simdlen(4), notinbranch),
omp::directive (declare simd, uniform (l), simdlen(4), inbranch)]]
int
+#ifdef __aarch64__
+f6 [[omp::sequence (directive (declare simd uniform (l) simdlen (2), notinbranch),
+ omp::directive (declare simd linear (l) simdlen (2) inbranch))]] (int l)
+#else
f6 [[omp::sequence (directive (declare simd uniform (l) simdlen (8), notinbranch),
omp::directive (declare simd linear (l) simdlen (8) inbranch))]] (int l)
-{ // { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64*-*-* } .-2 }
+#endif
+{
return l + 5;
}
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z2f6i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4u__Z2f6i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN2u__Z2f6i:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4u__Z2f6i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4l__Z2f6i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbM8l__Z2f6i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -109,7 +136,7 @@ f7 (int l)
return l + 6;
}
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f7i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f7i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
int
f8 (int l)
@@ -117,17 +144,26 @@ f8 (int l)
return l + 7;
}
-// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f8i:" { target { i?86-*-* x86_64-*-* } } } }
+// { dg-final { scan-assembler-not "_ZGV\[a-zA-Z0-9]__Z2f8i:" { target { i?86-*-* x86_64-*-* aarch64*-*-* } } } }
[[omp::sequence (omp::directive (declare variant (f7), match (construct={parallel})),
directive (declare simd uniform (l), simdlen(4)))]]
int
+#ifdef __aarch64__
+f9 [[omp::directive (declare simd uniform (l) simdlen (2)),
+#else
f9 [[omp::directive (declare simd uniform (l) simdlen (8)),
+#endif
omp::directive (declare variant (f8) match (construct={parallel,for}))]] (int l)
-{ // { dg-warning "GCC does not currently support simdlen 8 for type 'int'" "" { target aarch64*-*-* } .-2 }
+{
return l + 8;
}
+// { dg-final { scan-assembler-times "_ZGVnN2u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4u__Z2f9i:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4u__Z2f9i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4u__Z2f9i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4u__Z2f9i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -174,6 +210,9 @@ f10 (int x)
template [[omp::directive (declare simd, notinbranch)]] int f10<0> (int);
+// { dg-final { scan-assembler-times "_ZGVnN2v__Z3f10ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4v__Z3f10ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbN4v__Z3f10ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcN4v__Z3f10ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdN8v__Z3f10ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -181,6 +220,9 @@ template [[omp::directive (declare simd, notinbranch)]] int f10<0> (int);
template int f10<1> [[omp::directive (declare simd inbranch linear(x))]] (int x);
+// { dg-final { scan-assembler-times "_ZGVnM2l__Z3f10ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l__Z3f10ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4l__Z3f10ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4l__Z3f10ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdM8l__Z3f10ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -195,6 +237,9 @@ f11<0> (int x)
return x;
}
+// { dg-final { scan-assembler-times "_ZGVnM2v__Z3f11ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4v__Z3f11ILi0EEii:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4v__Z3f11ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4v__Z3f11ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdM8v__Z3f11ILi0EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -206,6 +251,9 @@ f11<1> [[omp::directive (declare simd, notinbranch, linear (y))]] (int y)
return y;
}
+// { dg-final { scan-assembler-times "_ZGVnN2l__Z3f11ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4l__Z3f11ILi1EEii:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbN4l__Z3f11ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcN4l__Z3f11ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdN8l__Z3f11ILi1EEii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -223,6 +271,9 @@ S::f12 (int x)
return x;
}
+// { dg-final { scan-assembler-times "_ZGVnM2uv__ZN1S3f12Ei:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2uv__ZN1S3f12Ei:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4uv__ZN1S3f12Ei:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4uv__ZN1S3f12Ei:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdM8uv__ZN1S3f12Ei:" 1 { target { i?86-*-* x86_64-*-* } } } }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C
index 00996b60e52760bf9fe82de7b0c42b9c846c1272..83255d9764a9c3b3f92d7a0bde45731501d937ba 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-1.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-1.C
@@ -2,19 +2,30 @@
// { dg-do compile }
// { dg-options "-fopenmp -ffat-lto-objects" }
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) \
+ linear (c : 4) simdlen (2) notinbranch
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) \
linear (c : 4) simdlen (8) notinbranch
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a \
: 4) simdlen (4) inbranch
+#endif
int f1 (int a, int *b, int c);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
+#endif
int f2 (int a, int *b, int c)
{
return a + *b + c;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN2uva8l4__Z2f2iPii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2uva8l4__Z2f2iPii:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -24,14 +35,22 @@ int f2 (int a, int *b, int c)
// { dg-final { scan-assembler-times "_ZGVeM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVeN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
+#ifdef __aarch64__
+#pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
template <typename T>
T f3 (int a, int *b, T c);
template <>
int f3 (int, int *, int);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) notinbranch simdlen (2)
+#else
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) notinbranch simdlen (4)
+#endif
template <typename T>
int f4 (int a, int *b, T c)
{
@@ -44,22 +63,38 @@ int f4 (int, int *, int);
template <typename T>
int f5 (int a, int *b, T c);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
template <>
int f5 (int a, int *b, int c);
template <int N>
int f6 (int a, int *b, int c);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) inbranch simdlen (2)
+#else
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) inbranch simdlen (4)
+#endif
template <>
int f6<3> (int a, int *b, int c);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (long long)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (long long)) linear (c : 4) simdlen (8)
+#endif
__extension__
long long f7 (long long a, long long *b, long long c);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) notinbranch simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) notinbranch simdlen (8)
+#endif
extern "C"
int f8 (int a, int *b, int c);
@@ -82,6 +117,9 @@ namespace N1
}
}
+// { dg-final { scan-assembler-times "_ZGVnN2va16__ZN2N12N23f10EPx:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2va16__ZN2N12N23f10EPx:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -95,28 +133,48 @@ namespace N1
struct A
{
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
int f11 (int a, int *b, int c);
#pragma omp declare simd
template <int N>
int f12 (int a, int *b, int c);
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) notinbranch simdlen (2)
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2) inbranch
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) notinbranch simdlen (8)
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4) inbranch
+#endif
static int f13 (int a, int *b, int c);
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
int f14 (int a, int *b, int c) { return a + *b + c; }
#pragma omp declare simd
template <int N>
int f15 (int a, int *b, int c) { return a + *b + c; }
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
static int f16 (int a, int *b, int c) { return a + *b + c; }
};
@@ -129,28 +187,48 @@ int A::f15<2> (int, int *, int);
template <typename T>
struct B
{
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2) notinbranch
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2) inbranch
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8) notinbranch
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4) inbranch
+#endif
int f17 (int a, int *b, int c);
#pragma omp declare simd
template <int N>
int f18 (int a, int *b, int c);
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
static int f19 (int a, int *b, int c);
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
int f20 (int a, int *b, int c) { return a + *b + c; }
#pragma omp declare simd
template <int N>
int f21 (int a, int *b, int c) { return a + *b + c; }
+#ifdef __aarch64__
+ #pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+ #pragma omp declare simd uniform (c) aligned (b : 2 * sizeof (int)) linear (a : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
+#endif
static int f22 (int a, int *b, int c) { return a + *b + c; }
template <int N>
@@ -176,25 +254,38 @@ template <>
template <>
int B<int>::f21<9> (int, int *, int);
+#ifdef __aarch64__
+#pragma omp declare simd simdlen (2) aligned (b : 2 * sizeof (int)) uniform (a, c)
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int)) uniform (a, c)
+#endif
template <>
template <>
int B<int>::f23<7> (int a, int *b, int c);
+#ifdef __aarch64__
+#pragma omp declare simd simdlen (2) aligned (b : 4 * sizeof (int)) linear (a, c : 2)
+#else
#pragma omp declare simd simdlen (4) aligned (b : 8 * sizeof (int)) linear (a, c : 2)
+#endif
template <>
template <>
int B<int>::f24<-1> (int a, int *b, int c);
+#ifdef __aarch64__
+#pragma omp declare simd simdlen (2) aligned (b : 2 * sizeof (int)) uniform (a, c)
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int)) uniform (a, c)
+#endif
template <>
template <>
int B<int>::f25<7> (int a, int *b, int c)
{
return a + *b + c;
}
+// { dg-final { scan-assembler-times "_ZGVnN2vuva8u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vuva8u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { aarch64*-*-* } } } }
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
// { dg-final { scan-assembler-times "_ZGVbM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -204,7 +295,11 @@ int B<int>::f25<7> (int a, int *b, int c)
// { dg-final { scan-assembler-times "_ZGVeM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVeN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
+#ifdef __aarch64__
+#pragma omp declare simd simdlen (2) aligned (b : 4 * sizeof (int)) linear (a, c : 2)
+#else
#pragma omp declare simd simdlen (4) aligned (b : 8 * sizeof (int)) linear (a, c : 2)
+#endif
template <>
template <>
int B<int>::f26<-1> (int a, int *b, int c)
@@ -212,7 +307,9 @@ int B<int>::f26<-1> (int a, int *b, int c)
return a + *b + c;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN2vl2va16__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vl2va16__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -225,26 +322,45 @@ int B<int>::f26<-1> (int a, int *b, int c)
int
f27 (int x)
{
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) aligned (b : 2 * sizeof (int))
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int))
+#endif
extern int f28 (int a, int *b, int c);
{
x++;
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) linear (c)
+#else
#pragma omp declare simd simdlen (4) linear (c)
+#endif
extern int f29 (int a, int *b, int c);
}
return x;
}
+#ifdef __aarch64__
+#pragma omp declare simd simdlen (4)
+#else
#pragma omp declare simd simdlen (16)
+#endif
int
f30 (int x)
{
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) aligned (b : 2 * sizeof (int))
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int))
+#endif
+
extern int f31 (int a, int *b, int c);
return x;
}
-// { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-7 }
+// { dg-final { scan-assembler-times "_ZGVnN4v__Z3f30i:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4v__Z3f30i:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -267,10 +383,18 @@ int
f33 (int x)
{
if (x)
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) aligned (b : 2 * sizeof (int))
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int))
+#endif
extern int f34 (int a, int *b, int c);
while (x < 10)
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) aligned (b : 2 * sizeof (int))
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int))
+#endif
extern int f35 (int a, int *b, int c);
return x;
}
@@ -287,10 +411,13 @@ struct D
int f37 (int a);
int e;
};
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-3 }
void
f38 (D &d)
{
+#ifdef __aarch64__
+ d.f37 <2> (6);
+#else
d.f37 <16> (6);
+#endif
}
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C
index ee4ab6febd0dfc727e57fce9438b2e9001075155..d89d9a7cf6b5aca4d69d819abbd975a7773ab824 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-3.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-3.C
@@ -13,7 +13,11 @@ int f1 (int a, int b, int c, int &d, int &e, int &f)
return a + b + c + d + e + f;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-11 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -42,7 +46,11 @@ int f2 (int a, int b, int c, int &d, int &e, int &f)
return a + b + c + d + e + f;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-17 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -58,7 +66,11 @@ int f3 (const int a, const int b, const int c, const int &d, const int &e, const
return a + b + c + d + e + f;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -80,7 +92,11 @@ int f4 (const int a, const int b, const int c, const int &d, const int &e, const
return a + b + c + d + e + f;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-11 }
+// { dg-final { scan-assembler-times "_ZGVnN2vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM2vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C
index d76defbc93319e94e23086250defc65758af18fc..0b76d922f3e15f996763de76940d368e516c16f7 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-4.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-4.C
@@ -5,7 +5,9 @@ f1 (int *p, int *q, short *s)
return *p + *q + *s;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64*-*-* } } } }
+// { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
@@ -13,29 +15,40 @@ f1 (int *p, int *q, short *s)
// { dg-final { scan-assembler-times "_ZGVdM8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
+#ifdef __aarch64__
+#pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(4) uniform(t)
+#else
#pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t)
+#endif
int
f2 (int *p, short *q, int s, int r, int &t)
{
return *p + *q + r;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN4ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVeN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
+#ifdef __aarch64__
+#pragma omp declare simd linear(ref(p):s) linear(val(q):t) uniform (s) linear(uval(r):s) notinbranch simdlen(4) uniform(t)
+#else
#pragma omp declare simd linear(ref(p):s) linear(val(q):t) uniform (s) linear(uval(r):s) notinbranch simdlen(8) uniform(t)
+#endif
int
f3 (int &p, short &q, int s, int &r, int &t)
{
return p + q + r;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 }
+// { dg-final { scan-assembler-times "_ZGVnN4Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { aarch64*-*-* } } } }
+
// { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
// { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C
index 373be28ebd325b254b1f467c2ad761479e26685b..52e9f182da35c920d78e64da8ee56cfdabaea541 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-7.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-7.C
@@ -18,7 +18,6 @@ foo1 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
{
return bar1 (a, b, c, d, e, f, g, h, i, j, k);
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
#pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \
linear (f : 2) linear (ref (g) : 1) \
@@ -29,7 +28,6 @@ foo2 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
{
return bar2 (a, b, c, d, e, f, g, h, i, j, k);
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
#pragma omp declare simd notinbranch uniform (b, c, d, e) aligned (e : 16) \
linear (f : 2) linear (ref (g) : 1) \
@@ -40,7 +38,6 @@ foo3 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
{
return bar3 (a, b, c, d, e, f, g, h, i, j, k);
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
#pragma omp declare simd inbranch uniform (b, c, d, e) aligned (e : 16) \
linear (f : 2) linear (ref (g) : 1) \
@@ -51,4 +48,3 @@ foo4 (int a, int b, float c, S d, int *e, int f, int &g, int &h, int &i, int j,
{
return bar4 (a, b, c, d, e, f, g, h, i, j, k);
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 }
diff --git a/gcc/testsuite/g++.dg/gomp/declare-simd-8.C b/gcc/testsuite/g++.dg/gomp/declare-simd-8.C
index ef183136833a997e2009af367acb575e02cb5b22..01c91e890914315ccd50e11cbeb5ff7581491a7d 100644
--- a/gcc/testsuite/g++.dg/gomp/declare-simd-8.C
+++ b/gcc/testsuite/g++.dg/gomp/declare-simd-8.C
@@ -4,7 +4,6 @@ template <int N, typename T>
struct S {
#pragma omp declare simd aligned(a : N * 2) aligned(b) linear(ref(b): N)
float foo (float *a, T *&b) { return *a + *b; }
- // { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-1 }
};
S<16, float> s;
diff --git a/gcc/testsuite/g++.dg/gomp/pr88182.C b/gcc/testsuite/g++.dg/gomp/pr88182.C
index 504f50376408543d4bbce55dbcc8f0f06b0fd805..ca29d000036e5f7d25b1fc9010a99ef72b5661cc 100644
--- a/gcc/testsuite/g++.dg/gomp/pr88182.C
+++ b/gcc/testsuite/g++.dg/gomp/pr88182.C
@@ -1,7 +1,11 @@
// { dg-do run }
// { dg-options "-O -fopenmp-simd -ftree-loop-if-convert -fno-ssa-phiopt" }
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch
+#else
#pragma omp declare simd simdlen(4) notinbranch
+#endif
__attribute__((noinline)) int
foo (double c1, double c2)
{
@@ -18,7 +22,6 @@ foo (double c1, double c2)
}
return res;
}
-// { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-15 }
__attribute__((noinline, noclone)) void
bar (double *x, double *y)
diff --git a/gcc/testsuite/gcc.dg/declare-simd.c b/gcc/testsuite/gcc.dg/declare-simd.c
index 2c8c1b7da4f3249c714849fa226bfa2fe64a2b88..1c71b60c97427705e2751088e24840e2613b4f03 100644
--- a/gcc/testsuite/gcc.dg/declare-simd.c
+++ b/gcc/testsuite/gcc.dg/declare-simd.c
@@ -3,7 +3,6 @@
#pragma omp declare simd linear (p2, p3)
extern void fn2 (float p1, float *p2, float *p3);
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target { { aarch64*-*-* } && lp64 } } .-1 } */
float *a, *b;
void fn1 (float *p1)
diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c
index add322873e64590ff3187f20907687ef34991fcb..c8a99a8c7070ca4657e9acb684ffd4798effd57f 100644
--- a/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-1.c
@@ -1,19 +1,30 @@
/* Test parsing of #pragma omp declare simd */
/* { dg-do compile } */
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) \
+ linear (c : 4) simdlen (2) notinbranch
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) \
linear (c : 4) simdlen (8) notinbranch
+#endif
#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a \
: 4) simdlen (4) inbranch
int f1 (int a, int *b, int c);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
+#endif
int f2 (int a, int *b, int c)
{
return a + *b + c;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnN2uva8l4_f2:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnM2uva8l4_f2:" 1 { target { aarch64*-*-* } } } } */
+
/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -23,34 +34,56 @@ int f2 (int a, int *b, int c)
/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (long long)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (long long)) linear (c : 4) simdlen (8)
+#endif
__extension__
long long f3 (long long a, long long *b, long long c);
int
f4 (int x)
{
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) aligned (b : 4 * sizeof (int))
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int))
+#endif
__extension__ __extension__ __extension__
extern int f5 (int a, int *b, int c);
{
x++;
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) linear (c)
+#else
#pragma omp declare simd simdlen (4) linear (c)
+#endif
extern int f6 (int a, int *b, int c);
}
return x;
}
+#ifdef __aarch64__
+#pragma omp declare simd simdlen (4)
+#else
#pragma omp declare simd simdlen (16)
+#endif
int
f7 (int x)
{
+#ifdef __aarch64__
+ #pragma omp declare simd simdlen (2) aligned (b : 2 * sizeof (int))
+#else
#pragma omp declare simd simdlen (8) aligned (b : 8 * sizeof (int))
+#endif
extern int f8 (int a, int *b, int c);
return x;
}
-/* { dg-warning "GCC does not currently support simdlen 16 for type 'int'" "" { target aarch64*-*-* } .-7 } */
+/* { dg-final { scan-assembler-times "_ZGVnM4v_f7:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN4v_f7:" 1 { target { aarch64*-*-* } } } } */
+
/* { dg-final { scan-assembler-times "_ZGVbM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -60,17 +93,27 @@ f7 (int x)
/* { dg-final { scan-assembler-times "_ZGVeM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVeN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
+#endif
int f12 (int c; int *b; int a; int a, int *b, int c);
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
+#endif
int
f13 (int c; int *b; int a; int a, int *b, int c)
{
return a + *b + c;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnM2uva8l4_f13:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN2uva8l4_f13:" 1 { target { aarch64*-*-* } } } } */
+
/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -80,7 +123,11 @@ f13 (int c; int *b; int a; int a, int *b, int c)
/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
+#endif
int
f14 (a, b, c)
int a, c;
@@ -89,7 +136,9 @@ f14 (a, b, c)
return a + *b + c;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-7 } */
+/* { dg-final { scan-assembler-times "_ZGVnM2uva8l4_f14:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN2uva8l4_f14:" 1 { target { aarch64*-*-* } } } } */
+
/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -99,14 +148,20 @@ f14 (a, b, c)
/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
+#ifdef __aarch64__
+#pragma omp declare simd uniform (a) aligned (b : 2 * sizeof (int)) linear (c : 4) simdlen (2)
+#else
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
+#endif
int
f15 (int a, int *b, int c)
{
return a + *b + c;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnM2uva8l4_f15:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN2uva8l4_f15:" 1 { target { aarch64*-*-* } } } } */
+
/* { dg-final { scan-assembler-times "_ZGVbM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -116,19 +171,33 @@ f15 (int a, int *b, int c)
/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
+#ifdef __aarch64__
+#pragma omp declare simd uniform (d) aligned (e : 2 * sizeof (int)) linear (f : 2) simdlen (2)
+#else
#pragma omp declare simd uniform (d) aligned (e : 8 * sizeof (int)) linear (f : 4) simdlen (8)
+#endif
int f15 (int d, int *e, int f);
+#ifdef __aarch64__
+#pragma omp declare simd aligned (g : sizeof (*g)) linear (h : 2 * sizeof (g[0]) + sizeof (h)) simdlen (2)
+#else
#pragma omp declare simd aligned (g : sizeof (*g)) linear (h : 2 * sizeof (g[0]) + sizeof (h)) simdlen (4)
+#endif
int f16 (long *g, int h);
+#ifdef __aarch64__
+#pragma omp declare simd aligned (h : sizeof (*h)) linear (g : 2 * sizeof (h[0]) + sizeof (g)) simdlen (2)
+#else
#pragma omp declare simd aligned (h : sizeof (*h)) linear (g : 2 * sizeof (h[0]) + sizeof (g)) simdlen (4)
+#endif
int f17 (int g, long *h)
{
return g + h[0];
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnM2l20va8_f17:" 1 { target { { aarch64*-*-* } && lp64 } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN2l20va8_f17:" 1 { target { { aarch64*-*-* } && lp64 } } } } */
+
/* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
@@ -146,7 +215,11 @@ int f17 (int g, long *h)
/* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
/* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
+#ifdef __aarch64__
+#pragma omp declare simd aligned (i : sizeof (*i)) linear (j : 2 * sizeof (i[0]) + sizeof (j)) simdlen (2)
+#else
#pragma omp declare simd aligned (i : sizeof (*i)) linear (j : 2 * sizeof (i[0]) + sizeof (j)) simdlen (4)
+#endif
int
f18 (j, i)
long *i;
@@ -155,7 +228,9 @@ f18 (j, i)
return j + i[0];
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } .-7 } */
+/* { dg-final { scan-assembler-times "_ZGVnM2l20va8_f18:" 1 { target { { aarch64*-*-* } && lp64 } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN2l20va8_f18:" 1 { target { { aarch64*-*-* } && lp64 } } } } */
+
/* { dg-final { scan-assembler-times "_ZGVbM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
diff --git a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c
index bf01c023541ae2100f63887901f4f330fbf1a12f..ba8e71008b5b2c6ef04bee31961a20ed7998708f 100644
--- a/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c
+++ b/gcc/testsuite/gcc.dg/gomp/declare-simd-3.c
@@ -4,8 +4,8 @@ f1 (int *p, int *q, short *s)
{
return *p + *q + *s;
}
-
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnM4l4ln4ln6_f1:" 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "_ZGVnN4l4ln4ln6_f1:" 1 { target { aarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVcM4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
@@ -15,14 +15,18 @@ f1 (int *p, int *q, short *s)
/* { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
+#ifdef __aarch64__
+#pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(4) uniform(t)
+#else
#pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t)
+#endif
int
f2 (int *p, short *q, int s, int r, int t)
{
return *p + *q + r;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
+/* { dg-final { scan-assembler-times "_ZGVnN4ls2ls4uls2u_f2:" 1 { target { aarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
/* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
diff --git a/gcc/testsuite/gcc.dg/gomp/pr87887-1.c b/gcc/testsuite/gcc.dg/gomp/pr87887-1.c
index 8b04ffd0809be4e6f5ab97c2e32e800edffbee4f..6e143aa0b5aa5ff9a9e13298fd44059377bc4f2e 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr87887-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr87887-1.c
@@ -10,6 +10,7 @@ foo (int x)
{
return (struct S) { x };
}
+/* { dg-warning "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 } */
#pragma omp declare simd
int
@@ -17,6 +18,7 @@ bar (struct S x)
{
return x.n;
}
+/* { dg-warning "unsupported argument type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 } */
#pragma omp declare simd uniform (x)
int
diff --git a/gcc/testsuite/gcc.dg/gomp/pr87895-1.c b/gcc/testsuite/gcc.dg/gomp/pr87895-1.c
index 7338f18d192072c4447957f3f20a32545c961d7f..22f5c691416470d6e0b9b02c97e519356bd39123 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr87895-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr87895-1.c
@@ -17,4 +17,3 @@ bar (int *x, int y)
if ((y == 0) ? (*x = 0) : *x)
return 0;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-5 } */
diff --git a/gcc/testsuite/gcc.dg/gomp/pr89246-1.c b/gcc/testsuite/gcc.dg/gomp/pr89246-1.c
index dfe629c1c6a51624cd94878c638606220cfe94eb..cdaec6b385169fc5ebb71dca48ef10c64c2cecfa 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr89246-1.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr89246-1.c
@@ -8,6 +8,7 @@ int foo (__int128 x)
{
return x;
}
+/* { dg-warning "unsupported argument type ‘__int128’ for ‘simd’ functions" { target aarch64*-*-* } .-4 } */
#pragma omp declare simd
extern int bar (int x);
diff --git a/gcc/testsuite/gcc.dg/gomp/pr99542.c b/gcc/testsuite/gcc.dg/gomp/pr99542.c
index b67ff5a37a20fdc2791b0aa9254a18d5ac43247e..f38e21da18580798bd2789c437cb0747da317efb 100644
--- a/gcc/testsuite/gcc.dg/gomp/pr99542.c
+++ b/gcc/testsuite/gcc.dg/gomp/pr99542.c
@@ -3,8 +3,8 @@
/* { dg-options "-O0 -fopenmp-simd" } */
#pragma omp declare simd
-extern int foo (__int128 x); /* { dg-warning "GCC does not currently support mixed size types for 'simd' function" "" { target aarch64*-*-* } } */
-/* { dg-warning "unsupported argument type '__int128' for simd" "" { target i?86-*-* x86_64-*-* } .-1 } */
+extern int foo (__int128 x);
+/* { dg-warning "unsupported argument type '__int128' for simd" "" { target i?86-*-* x86_64-*-* aarch64*-*-* } .-1 } */
#pragma omp declare simd uniform (x)
extern int baz (__int128 x);
diff --git a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c
index 9f7c84dc70ba4770c5f63f8af863e5577608d9a8..5fe4069c01c199a78c5f076f5a8ed1031da51cec 100644
--- a/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c
+++ b/gcc/testsuite/gcc.dg/gomp/simd-clones-2.c
@@ -6,7 +6,6 @@ int addit(int a, int b, int *c)
{
return a + b;
}
-/* { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } .-4 } */
/* { dg-final { scan-tree-dump {(?n)^__attribute__\(\(omp declare simd \(notinbranch aligned\(2:32\)\), omp declare simd \(inbranch uniform\(2\) linear\(1:66\)\)\)\)$} "optimized" } } */
#pragma omp declare simd uniform(a) aligned(a:32) linear(k:1) notinbranch
@@ -17,6 +16,13 @@ float setArray(float *a, float x, int k)
}
/* { dg-final { scan-tree-dump {(?n)^__attribute__\(\(omp declare simd \(notinbranch uniform\(0\) aligned\(0:32\) linear\(2:1\)\)\)\)$} "optimized" } } */
+/* { dg-final { scan-tree-dump "_ZGVnN2ua32vl_setArray" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnN4ua32vl_setArray" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnN2vvva32_addit" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnN4vvva32_addit" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnM2vl66u_addit" "optimized { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump "_ZGVnM4vl66u_addit" "optimized { target aarch64*-*-* } } } */
+
/* { dg-final { scan-tree-dump "_ZGVbN4ua32vl_setArray" "optimized" { target i?86-*-* x86_64-*-* } } } */
/* { dg-final { scan-tree-dump "_ZGVbN4vvva32_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */
/* { dg-final { scan-tree-dump "_ZGVbM4vl66u_addit" "optimized" { target i?86-*-* x86_64-*-* } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
index c44bfe511a5743198a647247c691075951f2258d..ec6d2daaa29ddc182f1b704d88bb598cc0eb6ad8 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c
@@ -12,8 +12,13 @@ int array[N];
#pragma omp declare simd simdlen(4) notinbranch
#pragma omp declare simd simdlen(4) notinbranch uniform(b) linear(c:3)
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch
+#pragma omp declare simd simdlen(2) notinbranch uniform(b) linear(c:3)
+#else
#pragma omp declare simd simdlen(8) notinbranch
#pragma omp declare simd simdlen(8) notinbranch uniform(b) linear(c:3)
+#endif
__attribute__((noinline)) int
foo (int a, int b, int c)
{
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
index feab989cfd595f9fdb839aa8bd3e8486751abf2f..13fc93614b4d06f4b441c5ce6931cd1576a2abc7 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c
@@ -12,8 +12,13 @@ int array[N] __attribute__((aligned (32)));
#pragma omp declare simd simdlen(4) notinbranch aligned(a:16) uniform(a) linear(b)
#pragma omp declare simd simdlen(4) notinbranch aligned(a:32) uniform(a) linear(b)
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch aligned(a:16) uniform(a) linear(b)
+#pragma omp declare simd simdlen(2) notinbranch aligned(a:32) uniform(a) linear(b)
+#else
#pragma omp declare simd simdlen(8) notinbranch aligned(a:16) uniform(a) linear(b)
#pragma omp declare simd simdlen(8) notinbranch aligned(a:32) uniform(a) linear(b)
+#endif
__attribute__((noinline)) void
foo (int *a, int b, int c)
{
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
index 42414671c254ffcd93169849d7a982861aa5ac0b..2f9f8306d672d94dbceba46beb8f1f740774ed33 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c
@@ -12,7 +12,11 @@ float d[N];
int e[N];
unsigned short f[N];
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(4) notinbranch uniform(b)
+#else
#pragma omp declare simd simdlen(8) notinbranch uniform(b)
+#endif
__attribute__((noinline)) float
foo (float a, float b, float c)
{
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
index 620cec36e4c023e1f52160327a3d5ba21540ad3b..0970818972057f4468250d82f6756baeb5578d8c 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c
@@ -10,7 +10,11 @@
int d[N], e[N];
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch uniform(b) linear(c:3)
+#else
#pragma omp declare simd simdlen(4) notinbranch uniform(b) linear(c:3)
+#endif
__attribute__((noinline)) long long int
foo (int a, int b, int c)
{
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
index 440091d70e83be80574a6fcf9e034c53aed15786..978cd4faa9bcefccaf2ab28091759b8f803c829b 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c
@@ -8,14 +8,24 @@
#define N 1024
#endif
-int a[N];
-long long int b[N];
-short c[N];
+#ifdef __aarch64__
+#define TYPE1 int
+#define TYPE2 int
+#define TYPE3 short
+#else
+#define TYPE1 int
+#define TYPE2 long long int
+#define TYPE3 short
+#endif
+
+TYPE1 a[N];
+TYPE2 b[N];
+TYPE3 c[N];
#pragma omp declare simd
#pragma omp declare simd uniform(b) linear(c:3)
-__attribute__((noinline)) short
-foo (int a, long long int b, short c)
+__attribute__((noinline)) TYPE3
+foo (TYPE1 a, TYPE2 b, TYPE3 c)
{
return a + b + c;
}
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
index 62246e28837272ef1e18860912643422f6dce018..68ea4716968efb63b0a342d36434cf7a20c5b5dc 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c
@@ -8,14 +8,24 @@
#define N 1024
#endif
-int a[N];
-long long int b[N];
-short c[N];
+#ifdef __aarch64__
+#define TYPE1 int
+#define TYPE2 int
+#define TYPE3 short
+#else
+#define TYPE1 int
+#define TYPE2 long long int
+#define TYPE3 short
+#endif
+
+TYPE1 a[N];
+TYPE2 b[N];
+TYPE3 c[N];
#pragma omp declare simd
#pragma omp declare simd uniform(b) linear(c:3)
-__attribute__((noinline)) short
-foo (int a, long long int b, int c)
+__attribute__((noinline)) TYPE3
+foo (TYPE1 a, TYPE2 b, TYPE1 c)
{
return a + b + c;
}
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
index 11ea2132689137cfb7175b176e39539b9197a330..29842825584fee5aeec81d43bac8574cf6c0e917 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c
@@ -12,14 +12,22 @@ int a[N], b[N];
long int c[N];
unsigned char d[N];
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch
+#else
#pragma omp declare simd simdlen(8) notinbranch
+#endif
__attribute__((noinline)) int
foo (long int a, int b, int c)
{
return a + b + c;
}
+#ifdef __aarch64__
+#pragma omp declare simd simdlen(2) notinbranch
+#else
#pragma omp declare simd simdlen(8) notinbranch
+#endif
__attribute__((noinline)) long int
bar (int a, int b, long int c)
{
diff --git a/gcc/testsuite/gcc.target/aarch64/declare-simd-1.c b/gcc/testsuite/gcc.target/aarch64/declare-simd-1.c
new file mode 100644
index 0000000000000000000000000000000000000000..aab8c17f0c442a7cda4dce23cc18162a0b7f676e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/declare-simd-1.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-fopenmp-simd" } */
+#ifdef __cplusplus
+extern "C" {
+#endif
+#pragma omp declare simd
+int __attribute__ ((const)) f00 (int a , char b) /* { dg-warning {GCC does not currently support a simdclone with simdlens 8 and 16 for these types.} } */
+{
+ return a + b;
+}
+
+#pragma omp declare simd
+long long __attribute__ ((const)) f01 (int a , short b) /* { dg-warning {GCC does not currently support a simdclone with simdlens 4 and 8 for these types.} } */
+{
+ return a + b;
+}
+
+#pragma omp declare simd linear(b)
+long long __attribute__ ((const)) f02 (short *b, int a) /* { dg-warning {GCC does not currently support a simdclone with simdlens 4 and 8 for these types.} } */
+{
+ return a + *b;
+}
+
+#pragma omp declare simd uniform(b)
+void f03 (char b, int a) /* { dg-warning {GCC does not currently support a simdclone with simdlens 8 and 16 for these types.} } */
+{
+}
+
+#pragma omp declare simd simdlen(4)
+double f04 (void) /* { dg-warning {GCC does not currently support simdlen 4 for type 'double'} } */
+{
+ return 4;
+}
+
+#pragma omp declare simd simdlen(16)
+void f05 (short a) /* { dg-warning {GCC does not currently support simdlen 16 for type 'short int'} } */
+{
+}
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/gcc/testsuite/gcc.target/aarch64/declare-simd-2.c b/gcc/testsuite/gcc.target/aarch64/declare-simd-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..abb128ffc9cd2c1353b99eb38aae72377746e6d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/declare-simd-2.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-fopenmp-simd" } */
+#ifdef __cplusplus
+extern "C" {
+#endif
+#pragma omp declare simd
+short __attribute__ ((const)) f00 (short a , char b)
+{
+ return a + b;
+}
+/* { dg-final { scan-assembler {_ZGVnN8vv_f00:} } } */
+/* { dg-final { scan-assembler {_ZGVnM8vv_f00:} } } */
+
+#pragma omp declare simd notinbranch
+short __attribute__ ((const)) f01 (int a , short b)
+{
+ return a + b;
+}
+/* { dg-final { scan-assembler {_ZGVnN4vv_f01:} } } */
+
+#pragma omp declare simd linear(b) inbranch
+int __attribute__ ((const)) f02 (int a, short *b)
+{
+ return a + *b;
+}
+/* { dg-final { scan-assembler {_ZGVnM4vl2_f02:} } } */
+
+#pragma omp declare simd uniform(a) notinbranch
+void f03 (char b, int a)
+{
+}
+/* { dg-final { scan-assembler {_ZGVnN8vu_f03:} } } */
+/* { dg-final { scan-assembler {_ZGVnN16vu_f03:} } } */
+
+#pragma omp declare simd simdlen(2)
+float f04 (double a)
+{
+ return (float) a;
+}
+/* { dg-final { scan-assembler {_ZGVnN2v_f04:} } } */
+/* { dg-final { scan-assembler {_ZGVnM2v_f04:} } } */
+
+#pragma omp declare simd uniform(a) linear (b)
+void f05 (short a, short *b, short c)
+{
+ *b += a + c;
+}
+
+/* { dg-final { scan-assembler {_ZGVnN4ul2v_f05:} } } */
+/* { dg-final { scan-assembler {_ZGVnN4ul2v_f05:} } } */
+/* { dg-final { scan-assembler {_ZGVnM8ul2v_f05:} } } */
+/* { dg-final { scan-assembler {_ZGVnM8ul2v_f05:} } } */
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90
index bbf70d9664a74601bed1d3352c0c33145e8fc8e7..8f76774fd6e0cc3a4ee327161496524392833179 100644
--- a/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/declare-simd-2.f90
@@ -1,6 +1,6 @@
! { dg-do compile }
-function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+function f1 (a, b, c, d, e, f)
integer, value :: a, b, c
integer :: d, e, f, f1
!$omp declare simd (f1) uniform(b) linear(c, d) linear(uval(e)) linear(ref(f))
@@ -12,7 +12,7 @@ function f1 (a, b, c, d, e, f) ! { dg-warning "GCC does not currently support mi
f = f + 1
f1 = a + b + c + d + e + f
end function f1
-integer function f2 (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+integer function f2 (a, b)
integer :: a, b
!$omp declare simd uniform(b) linear(ref(a):b)
a = a + 1
diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90
index f0c4e39efba140550f25c1b283d8eca66760f3a9..1f74da76ffe3f45b85e7f89534b7bf2ab923b4ff 100644
--- a/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/declare-simd-coarray-lib.f90
@@ -5,7 +5,7 @@
! Failed as TREE_TYPE(fndecl) did not include the
! hidden caf_token/caf_offset arguments.
!
-integer function f(x) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+integer function f(x)
integer :: x[*]
!$omp declare simd
f = x[1]
diff --git a/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90 b/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90
index 06c9a5d1ed8f9a5c0bbb4201e505f4309ef56222..6319df0558f37b95f1b2eb17374bdb4ecbc33295 100644
--- a/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/declare-variant-14.f90
@@ -35,13 +35,15 @@ contains
integer :: a, b
! At gimplification time, we can't decide yet which function to call.
- ! { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" } }
+ ! { dg-final { scan-tree-dump-times "f04 \\\(x" 2 "gimple" { target { !aarch64*-*-* } } } }
! After simd clones are created, the original non-clone test1 shall
! call f03 (score 6), the sse2/avx/avx2 clones too, but avx512f clones
! shall call f01 with score 8.
! { dg-final { scan-tree-dump-not "f04 \\\(x" "optimized" } }
- ! { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" } }
- ! { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" } }
+ ! { dg-final { scan-tree-dump-times "f03 \\\(x" 14 "optimized" { target { !aarch64*-*-* } } } }
+ ! { dg-final { scan-tree-dump-times "f03 \\\(x" 6 "optimized" { target { aarch64*-*-* } } } }
+ ! { dg-final { scan-tree-dump-times "f01 \\\(x" 4 "optimized" { target { !aarch64*-*-* } } } }
+ ! { dg-final { scan-tree-dump-times "f01 \\\(x" 0 "optimized" { target { aarch64*-*-* } } } }
a = f04 (x)
b = f04 (x)
test1 = a + b
diff --git a/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90 b/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90
index ea147bfa78ec716b7534f9b098c1fc0b98b1d397..6376baa6383c5527a6f9b8138d2b801f0fa53d5d 100644
--- a/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/pr79154-1.f90
@@ -1,7 +1,7 @@
! PR fortran/79154
! { dg-do compile }
-pure real function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+pure real function foo (a, b)
!$omp declare simd(foo) ! { dg-bogus "may not appear in PURE" }
real, intent(in) :: a, b
foo = a + b
@@ -20,7 +20,7 @@ pure real function baz (a, b)
real, intent(in) :: a, b
baz = a + b
end function baz
-elemental real function fooe (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+elemental real function fooe (a, b)
!$omp declare simd(fooe) ! { dg-bogus "may not appear in PURE" }
real, intent(in) :: a, b
fooe = a + b
diff --git a/gcc/testsuite/gfortran.dg/gomp/pr83977.f90 b/gcc/testsuite/gfortran.dg/gomp/pr83977.f90
index ea8e229fe5486a645cc7cc8aae748725f979c448..b8ad1a7e39c184fd084658477b183fc93071b357 100644
--- a/gcc/testsuite/gfortran.dg/gomp/pr83977.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/pr83977.f90
@@ -1,7 +1,7 @@
! PR middle-end/83977
! { dg-do compile }
-integer function foo (a, b) ! { dg-warning "GCC does not currently support mixed size types for 'simd' functions" "" { target aarch64*-*-* } }
+integer function foo (a, b)
integer :: a, b
!$omp declare simd uniform(b) linear(ref(a):b)
a = a + 1
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 64889fa6d346e57bccea306a9a357f11d74d5a59..81808d6aa45aa64d986a06e07e81a53c3bfa0c5d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4224,7 +4224,8 @@ proc check_effective_target_vect_simd_clones { } {
return [check_cached_effective_target_indexed vect_simd_clones {
expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
&& [check_effective_target_avx512f])
- || [istarget amdgcn-*-*] }}]
+ || [istarget amdgcn-*-*]
+ || [istarget aarch64*-*-*] }}]
}
# Return 1 if this is a AArch64 target supporting big endian
diff --git a/libgomp/testsuite/libgomp.c/declare-variant-1.c b/libgomp/testsuite/libgomp.c/declare-variant-1.c
index d16608f7e6dd45ea58ca6a0adef7ab56048ab1fd..6129f23a0f80585246957022d63608dc3a68f1ff 100644
--- a/libgomp/testsuite/libgomp.c/declare-variant-1.c
+++ b/libgomp/testsuite/libgomp.c/declare-variant-1.c
@@ -46,8 +46,10 @@ test1 (int x)
call f03 (score 6), the sse2/avx/avx2 clones too, but avx512f clones
shall call f01 with score 8. */
/* { dg-final { scan-ltrans-tree-dump-not "f04 \\\(x" "optimized" } } */
- /* { dg-final { scan-ltrans-tree-dump-times "f03 \\\(x" 14 "optimized" } } */
- /* { dg-final { scan-ltrans-tree-dump-times "f01 \\\(x" 4 "optimized" } } */
+ /* { dg-final { scan-ltrans-tree-dump-times "f03 \\\(x" 14 "optimized" { target { !aarch64*-*-* } } } } } */
+ /* { dg-final { scan-ltrans-tree-dump-times "f01 \\\(x" 4 "optimized" { target { !aarch64*-*-* } } } } } */
+ /* { dg-final { scan-ltrans-tree-dump-times "f03 \\\(x" 10 "optimized" { target { aarch64*-*-* } } } } } */
+ /* { dg-final { scan-ltrans-tree-dump-not "f01 \\\(x" "optimized" { target { aarch64*-*-* } } } } } */
int a = f04 (x);
int b = f04 (x);
return a + b;
diff --git a/libgomp/testsuite/libgomp.fortran/declare-simd-1.f90 b/libgomp/testsuite/libgomp.fortran/declare-simd-1.f90
index cb8f4df8d62e662582ff34f11b2b6f3e4c67f730..9d4452459aa76dacc2f3be2dd78ccd28b04fc379 100644
--- a/libgomp/testsuite/libgomp.fortran/declare-simd-1.f90
+++ b/libgomp/testsuite/libgomp.fortran/declare-simd-1.f90
@@ -1,5 +1,5 @@
! { dg-do run { target vect_simd_clones } }
-! { dg-options "-fno-inline" }
+! { dg-options "-fno-inline -cpp -D__aarch64__" }
! { dg-additional-options "-msse2" { target sse2_runtime } }
! { dg-additional-options "-mavx" { target avx_runtime } }
@@ -75,7 +75,11 @@ end module declare_simd_1_mod
end do
contains
function baz (x, y, z)
+#ifdef __aarch64__
+ !$omp declare simd (baz) simdlen (4) uniform (x, y)
+#else
!$omp declare simd (baz) simdlen (8) uniform (x, y)
+#endif
!$omp declare simd (baz)
integer, value :: y
real, value :: z
@@ -90,6 +94,10 @@ function bar (a, b, c)
real :: bar
double precision, value :: a
!$omp declare simd (bar)
+#ifdef __aarch64__
+ !$omp declare simd (bar) simdlen (2) linear (b : 2)
+#else
!$omp declare simd (bar) simdlen (4) linear (b : 2)
+#endif
bar = a + b * c
end function bar
next prev parent reply other threads:[~2023-10-16 15:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-26 14:44 Andre Vieira (lists)
2023-08-08 10:51 ` Richard Sandiford
2023-08-09 14:59 ` Andre Vieira (lists)
2023-08-09 16:55 ` Richard Sandiford
2023-08-09 17:07 ` Andre Vieira (lists)
2023-08-09 17:19 ` Jakub Jelinek
2023-08-09 17:27 ` Richard Sandiford
2023-08-09 17:53 ` Jakub Jelinek
2023-08-10 13:26 ` Richard Sandiford
2023-08-29 7:31 ` Andre Vieira (lists)
2023-10-16 15:03 ` Andre Vieira (lists) [this message]
2023-11-29 15:47 ` Richard Sandiford
2023-12-11 21:42 ` Thomas Schwinge
2023-12-12 8:13 ` Andre Vieira (lists)
2023-12-14 21:07 ` Update 'gcc.dg/vect/vect-simd-clone-*.c' GCN 'dg-warning's (was: [PATCH] aarch64: enable mixed-types for aarch64 simdclones) Thomas Schwinge
2023-12-12 8:10 ` [PATCH] aarch64: enable mixed-types for aarch64 simdclones Andrew Pinski
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