From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 3DC653851C19 for ; Tue, 30 Jun 2020 13:50:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3DC653851C19 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andre.simoesdiasvieira@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE23F1FB; Tue, 30 Jun 2020 06:50:51 -0700 (PDT) Received: from [10.57.55.248] (unknown [10.57.55.248]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 64AD13F71E; Tue, 30 Jun 2020 06:50:51 -0700 (PDT) Subject: Re: [PATCH][GCC][Arm] PR target/95646: Do not clobber callee saved registers with CMSE To: Christophe Lyon Cc: Kyrylo Tkachov , "gcc-patches@gcc.gnu.org" References: <602a84e8-f43a-ec3b-3887-2f35a7798b01@arm.com> <0b728ef5-5b93-03e6-acb2-e1825499f25c@arm.com> From: "Andre Vieira (lists)" Message-ID: <6e4c8b24-3f4d-8674-c19c-2780e6617960@arm.com> Date: Tue, 30 Jun 2020 14:50:49 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Jun 2020 13:50:53 -0000 On 29/06/2020 11:15, Christophe Lyon wrote: > On Mon, 29 Jun 2020 at 10:56, Andre Vieira (lists) > wrote: >> >> On 23/06/2020 21:52, Christophe Lyon wrote: >>> On Tue, 23 Jun 2020 at 15:28, Andre Vieira (lists) >>> wrote: >>>> On 23/06/2020 13:10, Kyrylo Tkachov wrote: >>>>>> -----Original Message----- >>>>>> From: Andre Vieira (lists) >>>>>> Sent: 22 June 2020 09:52 >>>>>> To: gcc-patches@gcc.gnu.org >>>>>> Cc: Kyrylo Tkachov >>>>>> Subject: [PATCH][GCC][Arm] PR target/95646: Do not clobber callee saved >>>>>> registers with CMSE >>>>>> >>>>>> Hi, >>>>>> >>>>>> As reported in bugzilla when the -mcmse option is used while compiling >>>>>> for size (-Os) with a thumb-1 target the generated code will clear the >>>>>> registers r7-r10. These however are callee saved and should be preserved >>>>>> accross ABI boundaries. The reason this happens is because these >>>>>> registers are made "fixed" when optimising for size with Thumb-1 in a >>>>>> way to make sure they are not used, as pushing and popping hi-registers >>>>>> requires extra moves to and from LO_REGS. >>>>>> >>>>>> To fix this, this patch uses 'callee_saved_reg_p', which accounts for >>>>>> this optimisation, instead of 'call_used_or_fixed_reg_p'. Be aware of >>>>>> 'callee_saved_reg_p''s definition, as it does still take call used >>>>>> registers into account, which aren't callee_saved in my opinion, so it >>>>>> is a rather misnoemer, works in our advantage here though as it does >>>>>> exactly what we need. >>>>>> >>>>>> Regression tested on arm-none-eabi. >>>>>> >>>>>> Is this OK for trunk? (Will eventually backport to previous versions if >>>>>> stable.) >>>>> Ok. >>>>> Thanks, >>>>> Kyrill >>>> As I was getting ready to push this I noticed I didn't add any skip-ifs >>>> to prevent this failing with specific target options. So here's a new >>>> version with those. >>>> >>>> Still OK? >>>> >>> Hi, >>> >>> This is not sufficient to skip arm-linux-gnueabi* configs built with >>> non-default cpu/fpu. >>> >>> For instance, with arm-linux-gnueabihf --with-cpu=cortex-a9 >>> --with-fpu=neon-fp16 --with-float=hard >>> I see: >>> FAIL: gcc.target/arm/pr95646.c (test for excess errors) >>> Excess errors: >>> cc1: error: ARMv8-M Security Extensions incompatible with selected FPU >>> cc1: error: target CPU does not support ARM mode >>> >>> and the testcase is compiled with -mcpu=cortex-m23 -mcmse -Os >> Resending as I don't think my earlier one made it to the lists (sorry if >> you are receiving this double!) >> >> I'm not following this, before I go off and try to reproduce it, what do >> you mean by 'the testcase is compiled with -mcpu=cortex-m23 -mcmse -Os'? >> These are the options you are seeing in the log file? Surely they should >> override the default options? Only thing I can think of is this might >> need an extra -mfloat-abi=soft to make sure it overrides the default >> float-abi. Could you give that a try? > No it doesn't make a difference alone. > > I also had to add: > -mfpu=auto (that clears the above warning) > -mthumb otherwise we now get cc1: error: target CPU does not support ARM mode > > Looks like some effective-target machinery is needed So I had a look at this,  I was pretty sure that -mfloat-abi=soft overwrote -mfpu=<>, which in large it does, as in no FP instructions will be generated but the error you see only checks for the right number of FP registers. Which doesn't check whether 'TARGET_HARD_FLOAT' is set or not. I'll fix this too and use the check-effective-target for armv8-m.base for this test as it is indeed a better approach than my bag of skip-ifs. I'm testing it locally to make sure my changes don't break anything. Cheers, Andre > > Christophe > > >> Cheers, >> Andre >>> Christophe >>> >>>> Cheers, >>>> Andre >>>>>> Cheers, >>>>>> Andre >>>>>> >>>>>> gcc/ChangeLog: >>>>>> 2020-06-22 Andre Vieira >>>>>> >>>>>> PR target/95646 >>>>>> * config/arm/arm.c: (cmse_nonsecure_entry_clear_before_return): >>>>>> Use 'callee_saved_reg_p' instead of >>>>>> 'calL_used_or_fixed_reg_p'. >>>>>> >>>>>> gcc/testsuite/ChangeLog: >>>>>> 2020-06-22 Andre Vieira >>>>>> >>>>>> PR target/95646 >>>>>> * gcc.target/arm/pr95646.c: New test.