* [PATCH 1/2] rs6000: Delete wg
@ 2019-06-03 22:30 Segher Boessenkool
2019-06-03 22:30 ` [PATCH 2/2] rs6000: Delete -mmfpgpr Segher Boessenkool
0 siblings, 1 reply; 2+ messages in thread
From: Segher Boessenkool @ 2019-06-03 22:30 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
The "wg" constraint is used for the floating point side on mfpgpr
instructions. Those instructions do not exist on any relevant
hardware. This patch deletes the constraint and the insns using it.
Tested on powerpc64-linux {-m32,-m64} and on powerpc64le-linux; p7 for BE,
and both p8 and p9 for LE. Committing to trunk.
Segher
2019-06-03 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wg"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wg.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.md (*mov<mode>_softfloat32, *movdi_internal64):
Delete "wg" alternatives.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 ---
gcc/config/rs6000/rs6000.c | 6 ------
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 26 +++++++++++---------------
gcc/doc/md.texi | 5 +----
5 files changed, 12 insertions(+), 29 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 8004a92..844e947 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -68,9 +68,6 @@ (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
"VSX vector register to hold vector float data or NO_REGS.")
-(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
- "If -mmfpgpr was used, a floating point register or NO_REGS.")
-
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 94795be..ba40536 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2511,7 +2511,6 @@ rs6000_debug_reg_global (void)
"wd reg_class = %s\n"
"we reg_class = %s\n"
"wf reg_class = %s\n"
- "wg reg_class = %s\n"
"wi reg_class = %s\n"
"wp reg_class = %s\n"
"wq reg_class = %s\n"
@@ -2530,7 +2529,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
@@ -3150,7 +3148,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wc - Reserved to represent individual CR bits (used in LLVM).
wd - Preferred register class for V2DFmode.
wf - Preferred register class for V4SFmode.
- wg - Float register for power6x move insns.
wi - FP or VSX register to hold 64-bit integers for VSX insns.
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
@@ -3182,9 +3179,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_ALTIVEC)
rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
- if (TARGET_MFPGPR) /* DFmode */
- rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
-
if (TARGET_POWERPC64)
{
rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 34fa36b..8ec1f35 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1260,7 +1260,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
- RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 47cbba8..c8e43c5 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7641,19 +7641,19 @@ (define_insn "*mov<mode>_softfloat32"
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFTGPR MFFGPR MFVSRD MTVSRD
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, wg, r, <f64_dm>")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, wg, r, <f64_dm>, r"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7674,21 +7674,19 @@ (define_insn "*mov<mode>_hardfloat64"
mt%0 %1
mf%1 %0
nop
- mftgpr %0,%1
- mffgpr %0,%1
mfvsrd %0,%x1
mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mftgpr, mffgpr, mftgpr, mffgpr")
+ *, mftgpr, mffgpr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
*, *, *, *, *,
*, *, *, *, *,
- *, *, *, p8v, p8v")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -8825,20 +8823,20 @@ (define_split
;; FPR store FPR load FPR move AVX store AVX store AVX load
;; AVX load VSX move P9 0 P9 -1 AVX 0/-1 VSX 0
;; VSX -1 P9 const AVX const From SPR To SPR SPR<->SPR
-;; FPR->GPR GPR->FPR VSX->GPR GPR->VSX
+;; VSX->GPR GPR->VSX
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r, r, r, r,
m, ^d, ^d, wY, Z, $v,
$wv, ^wi, wa, wa, wv, wi,
wi, wv, wv, r, *h, *h,
- ?r, ?wg, ?r, ?wi")
+ ?r, ?wi")
(match_operand:DI 1 "input_operand"
"r, YZ, r, I, L, nF,
^d, m, ^d, ^v, $wv, wY,
Z, ^wi, Oj, wM, OjwM, Oj,
wM, wS, wB, *h, r, 0,
- wg, r, wi, r"))]
+ wi, r"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@@ -8867,8 +8865,6 @@ (define_insn "*movdi_internal64"
mf%1 %0
mt%0 %1
nop
- mftgpr %0,%1
- mffgpr %0,%1
mfvsrd %0,%x1
mtvsrd %x0,%1"
[(set_attr "type"
@@ -8876,20 +8872,20 @@ (define_insn "*movdi_internal64"
fpstore, fpload, fpsimple, fpstore, fpstore, fpload,
fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical,
veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
- mftgpr, mffgpr, mftgpr, mffgpr")
+ mftgpr, mffgpr")
(set_attr "size" "64")
(set_attr "length"
"4, 4, 4, 4, 4, 20,
4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4,
4, 8, 4, 4, 4, 4,
- 4, 4, 4, 4")
+ 4, 4")
(set_attr "isa"
"*, *, *, *, *, *,
*, *, *, p9v, *, p9v,
*, *, p9v, p9v, *, *,
*, *, *, *, *, *,
- *, *, p8v, p8v")])
+ p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
; instruction.
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 4bc57d6..cf51326 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd},
-@code{wf}, @code{wg}, @code{wi},
+@code{wf}, @code{wi},
@code{wp}, @code{wq}, @code{ws},
@code{wt}, @code{wv}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
@@ -3256,9 +3256,6 @@ were used or NO_REGS.
@item wf
VSX vector register to hold vector float data or NO_REGS.
-@item wg
-If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
-
@item wi
FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
--
1.8.3.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH 2/2] rs6000: Delete -mmfpgpr
2019-06-03 22:30 [PATCH 1/2] rs6000: Delete wg Segher Boessenkool
@ 2019-06-03 22:30 ` Segher Boessenkool
0 siblings, 0 replies; 2+ messages in thread
From: Segher Boessenkool @ 2019-06-03 22:30 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This patch makes the -mmfpgpr option not do anything except warn that
the option is deprecated.
Tested on powerpc64-linux {-m32,-m64} and on powerpc64le-linux; p7 for BE,
and both p8 and p9 for LE. Committing to trunk.
Segher
2019-06-03 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.h (MASK_MFPGPR): Delete.
* config/rs6000/rs6000.c (direct_move_p): Adjust.
(rs6000_secondary_reload_simple_move): Adjust.
(rs6000_opt_masks): Neuter the "mfpgpr" option.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Adjust.
* config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED): Adjust
comment.
(power6x): Adjust.
* config/rs6000/rs6000.md (floatsi<mode>2_lfiwax): Adjust.
(floatunssi<mode>2_lfiwzx): Adjust.
(fix_trunc<mode>si2_stfiwx): Adjust.
(fixuns_trunc<mode>si2_stfiwx): Adjust.
* config/rs6000/rs6000.opt (mno-mfpgpr): New.
(mfpgpr): Mark as deprecated.
* doc/extend.texi (PowerPC Function Attributes): Delete mfpgpr.
(Basic PowerPC Built-in Functions Available on ISA 2.05): Adjust.
* doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mmfpgpr.
gcc/testsuite/
* gcc.target/powerpc/mmfpgpr.c: Delete.
---
gcc/config/rs6000/rs6000-c.c | 2 --
gcc/config/rs6000/rs6000-cpus.def | 10 ++++------
gcc/config/rs6000/rs6000.c | 30 ++++++++----------------------
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 10 ++++------
gcc/config/rs6000/rs6000.opt | 7 +++++--
gcc/doc/extend.texi | 11 ++---------
gcc/doc/invoke.texi | 10 +---------
gcc/testsuite/gcc.target/powerpc/mmfpgpr.c | 22 ----------------------
9 files changed, 24 insertions(+), 79 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/powerpc/mmfpgpr.c
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index bd1e97e..7854082 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -430,8 +430,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
if ((flags & OPTION_MASK_CMPB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
- if ((flags & OPTION_MASK_MFPGPR) != 0)
- rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
if ((flags & OPTION_MASK_POPCNTD) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
/* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 101efd5..14f8a0e 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -24,10 +24,9 @@
#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
- /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
- ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
- fre, fsqrt, etc. were no longer documented as optional. Group masks by
- server and embedded. */
+ /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
+ power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
+ as optional. Group masks by server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
| OPTION_MASK_CMPB \
| OPTION_MASK_RECIP_PRECISION \
@@ -130,7 +129,6 @@
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
- | OPTION_MASK_MFPGPR \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
@@ -236,7 +234,7 @@ RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
- | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
+ | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ba40536..3aa19db 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -7473,30 +7473,22 @@ gpr_or_gpr_p (rtx op0, rtx op1)
bool
direct_move_p (rtx op0, rtx op1)
{
- int regno0, regno1;
-
if (!REG_P (op0) || !REG_P (op1))
return false;
- if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
+ if (!TARGET_DIRECT_MOVE)
return false;
- regno0 = REGNO (op0);
- regno1 = REGNO (op1);
+ int regno0 = REGNO (op0);
+ int regno1 = REGNO (op1);
if (!HARD_REGISTER_NUM_P (regno0) || !HARD_REGISTER_NUM_P (regno1))
return false;
- if (INT_REGNO_P (regno0))
- return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
+ if (INT_REGNO_P (regno0) && VSX_REGNO_P (regno1))
+ return true;
- else if (INT_REGNO_P (regno1))
- {
- if (TARGET_MFPGPR && FP_REGNO_P (regno0))
- return true;
-
- else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
- return true;
- }
+ if (VSX_REGNO_P (regno0) && INT_REGNO_P (regno1))
+ return true;
return false;
}
@@ -19079,12 +19071,6 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
return true;
}
- /* Power6+: MFTGPR or MFFGPR. */
- else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
- && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
- || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
- return true;
-
/* Move to/from SPR. */
else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
&& ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
@@ -36452,7 +36438,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
- { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
+ { "mfpgpr", 0, false, true },
{ "modulo", OPTION_MASK_MODULO, false, true },
{ "mulhw", OPTION_MASK_MULHW, false, true },
{ "multiple", OPTION_MASK_MULTIPLE, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8ec1f35..3201152 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -509,7 +509,6 @@ extern int rs6000_vector_align[];
#define MASK_HTM OPTION_MASK_HTM
#define MASK_ISEL OPTION_MASK_ISEL
#define MASK_MFCRF OPTION_MASK_MFCRF
-#define MASK_MFPGPR OPTION_MASK_MFPGPR
#define MASK_MULHW OPTION_MASK_MULHW
#define MASK_MULTIPLE OPTION_MASK_MULTIPLE
#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c8e43c5..c49614c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5265,8 +5265,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax"
rtx src = operands[1];
rtx tmp;
- if (!MEM_P (src) && TARGET_POWERPC64
- && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
+ if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
tmp = convert_to_mode (DImode, src, false);
else
{
@@ -5341,8 +5340,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx"
rtx src = operands[1];
rtx tmp;
- if (!MEM_P (src) && TARGET_POWERPC64
- && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
+ if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
tmp = convert_to_mode (DImode, src, true);
else
{
@@ -5703,7 +5701,7 @@ (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
emit_insn (gen_stfiwx (dest, tmp));
DONE;
}
- else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE) && !MEM_P (dest))
+ else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE && !MEM_P (dest))
{
dest = gen_lowpart (DImode, dest);
emit_move_insn (dest, tmp);
@@ -5851,7 +5849,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
emit_insn (gen_stfiwx (dest, tmp));
DONE;
}
- else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
+ else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
{
dest = gen_lowpart (DImode, dest);
emit_move_insn (dest, tmp);
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 3a43536..342a349 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -144,9 +144,12 @@ mcmpb
Target Report Mask(CMPB) Var(rs6000_isa_flags)
Use PowerPC V2.05 compare bytes instruction.
+;; This option existed in the past, but now is always off.
+mno-mfpgpr
+Target RejectNegative Undocumented Ignore
+
mmfpgpr
-Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
-Use extended PowerPC V2.05 move floating point to/from GPR instructions.
+Target RejectNegative Undocumented Deprecated
maltivec
Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 777d974..2520835 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -5432,13 +5432,6 @@ Generate code that uses (does not use) the move from condition
register field instruction implemented on the POWER4 processor and
other processors that support the PowerPC V2.01 architecture.
-@item mfpgpr
-@itemx no-mfpgpr
-@cindex @code{target("mfpgpr")} function attribute, PowerPC
-Generate code that uses (does not use) the FP move to/from general
-purpose register instructions implemented on the POWER6X processor and
-other processors that support the extended PowerPC V2.05 architecture.
-
@item mulhw
@itemx no-mulhw
@cindex @code{target("mulhw")} function attribute, PowerPC
@@ -16879,8 +16872,8 @@ enabling the @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
@option{-mpowerpc-gfxopt}, @option{-mmfcrf}, @option{-mpopcntb},
@option{-mfprnd}, @option{-mcmpb}, @option{-mhard-dfp}, and
@option{-mrecip-precision} options. Specify the
-@option{-maltivec} and @option{-mfpgpr} options explicitly in
-combination with the above options if they are desired.
+@option{-maltivec} option explicitly in
+combination with the above options if desired.
The following functions require option @option{-mcmpb}.
@smallexample
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9e2fab5..91c9bb8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1076,7 +1076,7 @@ See RS/6000 and PowerPC Options.
-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol
-mfprnd -mno-fprnd @gol
--mcmpb -mno-cmpb -mmfpgpr -mno-mfpgpr -mhard-dfp -mno-hard-dfp @gol
+-mcmpb -mno-cmpb -mhard-dfp -mno-hard-dfp @gol
-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
-malign-power -malign-natural @gol
@@ -24014,8 +24014,6 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
@need 800
@itemx -mcmpb
@itemx -mno-cmpb
-@itemx -mmfpgpr
-@itemx -mno-mfpgpr
@itemx -mhard-dfp
@itemx -mno-hard-dfp
@opindex mpowerpc-gpopt
@@ -24034,8 +24032,6 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
@opindex mno-fprnd
@opindex mcmpb
@opindex mno-cmpb
-@opindex mmfpgpr
-@opindex mno-mfpgpr
@opindex mhard-dfp
@opindex mno-hard-dfp
You use these options to specify which instructions are available on the
@@ -24069,10 +24065,6 @@ processors that support the PowerPC V2.03 architecture.
The @option{-mcmpb} option allows GCC to generate the compare bytes
instruction implemented on the POWER6 processor and other processors
that support the PowerPC V2.05 architecture.
-The @option{-mmfpgpr} option allows GCC to generate the FP move to/from
-general-purpose register instructions implemented on the POWER6X
-processor and other processors that support the extended PowerPC V2.05
-architecture.
The @option{-mhard-dfp} option allows GCC to generate the decimal
floating-point instructions implemented on some POWER processors.
diff --git a/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c b/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c
deleted file mode 100644
index d7063a4..0000000
--- a/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power6x -mmfpgpr" } */
-/* { dg-final { scan-assembler "mffgpr" } } */
-/* { dg-final { scan-assembler "mftgpr" } } */
-
-/* Test that we generate the instructions to move between the GPR and FPR
- registers under power6x. */
-
-extern long return_long (void);
-extern double return_double (void);
-
-double return_double2 (void)
-{
- return (double) return_long ();
-}
-
-long return_long2 (void)
-{
- return (long) return_double ();
-}
--
1.8.3.1
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