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[46.223.203.173]) by smtp.gmail.com with ESMTPSA id ha17-20020a170906a89100b009dd8473559dsm4072784ejb.110.2023.11.13.06.47.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Nov 2023 06:47:58 -0800 (PST) Message-ID: <6f1a21c1-8f11-4d64-a10f-4397fb84f836@gmail.com> Date: Mon, 13 Nov 2023 15:47:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: rdapp.gcc@gmail.com Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. Content-Language: en-US To: =?UTF-8?B?6ZKf5bGF5ZOy?= , gcc-patches , palmer , "kito.cheng" , Jeff Law References: <8133F50F9A1CE3FD+2023111316104347931412@rivai.ai> <8b929bb2-1bf7-4303-922d-61dec54afe04@gmail.com> <0CB5AAAFF5F68D45+2023111316255749282118@rivai.ai> <2525a837-bf19-4cfa-b541-f02c9a18e921@gmail.com> <4826C16072662A07+2023111317301765628324@rivai.ai> <01707EE07942C1E2+2023111317380491743127@rivai.ai> <696d9a22-c1e9-4638-b908-e57eeb387220@gmail.com> <89EA159FD1F84ED5+2023111318361499234931@rivai.ai> <0f62500d-0909-4d96-96dd-e821d8e44625@gmail.com> <111EACD9132D9CCD+2023111321340190783659@rivai.ai> From: Robin Dapp In-Reply-To: <111EACD9132D9CCD+2023111321340190783659@rivai.ai> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: As per Jeff's remark I'm going to push the attached. Regards Robin Subject: [PATCH v4] RISC-V: vsetvl: Refine REG_EQUAL equality. This patch enhances the equality check for REG_EQUAL notes in the vsetvl pass by using the == operator instead of rtx_equal_p. With that, in situations like the following, a5 and a7 are not considered equal anymore. (insn 62 60 63 4 (set (reg:DI 17 a7 [orig:154 loop_len_54 ] [154]) (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174]) (reg:DI 30 t5 [219]))) 442 {umindi3} (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174]) (const_int 8 [0x8])) (nil))) (insn 63 62 65 4 (set (reg:DI 15 a5 [orig:175 _103 ] [175]) (minus:DI (reg:DI 15 a5 [orig:174 _100 ] [174]) (reg:DI 17 a7 [orig:154 loop_len_54 ] [154]))) 11 {subdi3} (nil)) (insn 65 63 66 4 (set (reg:DI 16 a6 [orig:153 loop_len_53 ] [153]) (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175]) (reg:DI 30 t5 [219]))) 442 {umindi3} (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175]) (const_int 8 [0x8])) (nil))) gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (source_equal_p): Use pointer equality for REG_EQUAL. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 6 ++++- .../rvv/autovec/partial/multiple_rgroup_zbb.c | 23 +++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 3fa25a6404d..8466b5d019e 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -560,7 +560,11 @@ source_equal_p (insn_info *insn1, insn_info *insn2) rtx note1 = find_reg_equal_equiv_note (rinsn1); rtx note2 = find_reg_equal_equiv_note (rinsn2); - if (note1 && note2 && rtx_equal_p (note1, note2)) + /* We could handle the case of similar-looking REG_EQUALs as well but + would need to verify that no insn in between modifies any of the source + operands. */ + if (note1 && note2 && rtx_equal_p (note1, note2) + && REG_NOTE_KIND (note1) == REG_EQUIV) return true; return false; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c new file mode 100644 index 00000000000..15178a2c848 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c @@ -0,0 +1,23 @@ +/* { dg-do compile } *. +/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */ + +#include + +void __attribute__ ((noipa)) +test (uint16_t *__restrict f, uint32_t *__restrict d, uint64_t *__restrict e, + uint16_t x, uint16_t x2, uint16_t x3, uint16_t x4, uint32_t y, + uint32_t y2, uint64_t z, int n) +{ + for (int i = 0; i < n; ++i) + { + f[i * 4 + 0] = x; + f[i * 4 + 1] = x2; + f[i * 4 + 2] = x3; + f[i * 4 + 3] = x4; + d[i * 2 + 0] = y; + d[i * 2 + 1] = y2; + e[i] = z; + } +} + +/* { dg-final { scan-assembler-times "vsetvli\tzero,\s*\[a-z0-9\]+,\s*e16,\s*m1,\s*ta,\s*ma" 4 } } */ -- 2.41.0