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[24.5.188.125]) by smtp.gmail.com with ESMTPSA id f2-20020a17090a638200b002992f49922csm3578650pjj.25.2024.03.01.10.59.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 Mar 2024 10:59:48 -0800 (PST) Message-ID: <70ba4f77-809c-4d99-8d69-fe2a6ac8a8ce@rivosinc.com> Date: Fri, 1 Mar 2024 10:59:47 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Content-Language: en-US To: "Li, Pan2" , Kito Cheng , =?UTF-8?B?6ZKf5bGF5ZOy?= Cc: gcc-patches , "Wang, Yanzhang" , "rdapp.gcc" , Jeff Law References: <20240223080558.2644800-1-pan2.li@intel.com> <20240228103532.2079576-1-pan2.li@intel.com> <1AA40984DD2A43FA+202402282158578616418@rivai.ai> From: Vineet Gupta In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Pan, On 2/28/24 17:23, Li, Pan2 wrote: > > Personally I prefer to remove --param=riscv-autovec-preference=none > and only allow > > mrvv-vector-bits, to avoid tricky(maybe) sematic of none preference. > However, let’s > > wait for a while in case there are some comments from others. > We are very interested in this topic. Could you please CC me and Palmer for future versions of the patchset. Thx, -Vineet >   > > Pan > >   > > *From:*Kito Cheng > *Sent:* Wednesday, February 28, 2024 10:55 PM > *To:* 钟居哲 > *Cc:* Li, Pan2 ; gcc-patches > ; Wang, Yanzhang ; > rdapp.gcc ; Jeff Law > *Subject:* Re: Re: [PATCH v3] RISC-V: Introduce gcc option > mrvv-vector-bits for RVV > >   > > Hmm, maybe only keep --param=riscv-autovec-preference=none and remove > other two if we think that might still useful? But anyway I have no > strong opinion to keep that, I mean I am ok to remove whole > --param=riscv-autovec-preference. > >   > > 钟居哲 於 2024年2月28日週三 21:59 寫道： > > I think it makes more sense to remove > --param=riscv-autovec-preference and add -mrvv-vector-bits.... > >   > > ------------------------------------------------------------------------ > > juzhe.zhong@rivai.ai > >   > > *From:* Kito Cheng > > *Date:* 2024-02-28 20:56 > > *To:* pan2.li > > *CC:* gcc-patches ; > juzhe.zhong ; yanzhang.wang > ; rdapp.gcc > ; jeffreyalaw > > > *Subject:* Re: [PATCH v3] RISC-V: Introduce gcc option > mrvv-vector-bits for RVV > > Take one more look, I think this option should work and > integrate with > > --param=riscv-autovec-preference= since they have similar jobs but > > slightly different. > >   > > We have 3 value for  --param=riscv-autovec-preference=: none, > scalable > > and fixed-vlmax > >   > > -mrvv-vector-bits=scalable is work like > > --param=riscv-autovec-preference=scalable and > > -mrvv-vector-bits=zvl is work like > > --param=riscv-autovec-preference=fixed-vlmax. > >   > > So I think...we need to do some conflict check, like: > >   > > -mrvv-vector-bits=zvl can't work with > --param=riscv-autovec-preference=scalable > > -mrvv-vector-bits=scalable can't work with > > --param=riscv-autovec-preference=fixed-vlmax > >   > > but it may not just alias since there is some useful > combinations like: > >   > > -mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none: > > NO auto vectorization but intrinsic code still could benefit > from the > > -mrvv-vector-bits=zvl option. > >   > > -mrvv-vector-bits=scalable with > --param=riscv-autovec-preference=none > > Should still work for VLS code gen, but just disable auto > > vectorization per the option semantic. > >   > > However here is something we need some fix, since > > --param=riscv-autovec-preference=none still disable VLS code > gen for > > now, you can see some example here: > > https://godbolt.org/z/fMTr3eW7K > >   > > But I think it's really the right behavior here, this part > might need > > to be fixed in vls_mode_valid_p and some other places. > >   > >   > > Anyway I think we need to check all use sites with > RVV_FIXED_VLMAX and > > RVV_SCALABLE, and need to make sure all use site of > RVV_FIXED_VLMAX > > also checked with RVV_VECTOR_BITS_ZVL. > >   > >   > >   > > > -/* Return the VLEN value associated with -march. > > > +static int > > > +riscv_convert_vector_bits (int min_vlen) > >   > > Not sure if we really need this function, it seems it always > returns min_vlen? > >   > > > +{ > > > +  int rvv_bits = 0; > > > + > > > +  switch (rvv_vector_bits) > > > +    { > > > +      case RVV_VECTOR_BITS_ZVL: > > > +      case RVV_VECTOR_BITS_SCALABLE: > > > +       rvv_bits = min_vlen; > > > +       break; > > > +      default: > > > +       gcc_unreachable (); > > > +    } > > > + > > > +  return rvv_bits; > > > +} > > > + > > > +/* Return the VLEN value associated with -march and > -mwrvv-vector-bits. > >   >