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[46.5.130.86]) by smtp.gmail.com with ESMTPSA id e6-20020a05600c218600b003fbc0a49b57sm15307167wme.6.2023.07.04.12.07.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Jul 2023 12:07:38 -0700 (PDT) Message-ID: <71107a6d-0062-7cf1-9f76-6c5fc1057173@gmail.com> Date: Tue, 4 Jul 2023 21:07:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Cc: rdapp.gcc@gmail.com Subject: Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI Content-Language: en-US To: Kito Cheng , Richard Biener , Robin Dapp via Gcc-patches , =?UTF-8?B?6ZKf5bGF5ZOy?= , Jeff Law , "kito.cheng" , palmer , palmer , richard.sandiford@arm.com References: <20230628094752.332289-1-juzhe.zhong@rivai.ai> <59DD619A76E2AC1A+2023062903025467496516@rivai.ai> <0f48c2b7-a24d-6223-3805-d755c8eb7a7c@gmail.com> <85bfdc0a-6b55-a72c-b8d8-656b40b0003a@gmail.com> <5c3171e3-fc51-05fa-a018-a1e750a3b4d0@gmail.com> <625bbf0c-0b52-3022-17dd-a7a9e49387a6@gmail.com> From: Robin Dapp In-Reply-To: <625bbf0c-0b52-3022-17dd-a7a9e49387a6@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_MANYTO,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_35_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > Kito (or somebody else), would you mind doing a RISC-V bootstrap? It would > take forever on my machine. Thank you. I did a bootstrap myself now and it finally finished. Going to commit the attached tomorrow. Regards Robin Subject: [PATCH] Change MODE_BITSIZE to MODE_PRECISION for MODE_VECTOR_BOOL. RISC-V lowers the TYPE_PRECISION for MODE_VECTOR_BOOL vectors in order to distinguish between VNx1BI, VNx2BI, VNx4BI and VNx8BI. This patch adjusts uses of MODE_VECTOR_BOOL to use GET_MODE_PRECISION instead of GET_MODE_BITSIZE. The RISC-V tests are provided by Juzhe. Co-Authored-By: Juzhe-Zhong gcc/c-family/ChangeLog: * c-common.cc (c_common_type_for_mode): Use GET_MODE_PRECISION. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Ditto. * simplify-rtx.cc (native_encode_rtx): Ditto. (native_decode_vector_rtx): Ditto. (simplify_const_vector_byte_offset): Ditto. (simplify_const_vector_subreg): Ditto. * tree.cc (build_truth_vector_type_for_mode): Ditto. * varasm.cc (output_constant_pool_2): Ditto. gcc/fortran/ChangeLog: * trans-types.cc (gfc_type_for_mode): Ditto. gcc/go/ChangeLog: * go-lang.cc (go_langhook_type_for_mode): Ditto. gcc/lto/ChangeLog: * lto-lang.cc (lto_type_for_mode): Ditto. gcc/rust/ChangeLog: * backend/rust-tree.cc (c_common_type_for_mode): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: New test. --- gcc/c-family/c-common.cc | 2 +- gcc/config/riscv/riscv-v.cc | 12 ++++---- gcc/fortran/trans-types.cc | 2 +- gcc/go/go-lang.cc | 2 +- gcc/lto/lto-lang.cc | 2 +- gcc/rust/backend/rust-tree.cc | 2 +- gcc/simplify-rtx.cc | 10 +++---- .../riscv/rvv/autovec/vls-vlmax/bitmask-1.c | 23 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-10.c | 22 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-11.c | 23 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-12.c | 23 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-13.c | 23 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-14.c | 24 +++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-2.c | 23 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-3.c | 23 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-4.c | 23 ++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-5.c | 25 ++++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-6.c | 27 +++++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-7.c | 30 +++++++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-8.c | 30 +++++++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-9.c | 30 +++++++++++++++++++ gcc/tree.cc | 2 +- gcc/varasm.cc | 8 ++++- 23 files changed, 374 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c diff --git a/gcc/c-family/c-common.cc b/gcc/c-family/c-common.cc index 34566a342bd..6ab63dae997 100644 --- a/gcc/c-family/c-common.cc +++ b/gcc/c-family/c-common.cc @@ -2458,7 +2458,7 @@ c_common_type_for_mode (machine_mode mode, int unsignedp) else if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL && valid_vector_subparts_p (GET_MODE_NUNITS (mode))) { - unsigned int elem_bits = vector_element_size (GET_MODE_BITSIZE (mode), + unsigned int elem_bits = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); tree bool_type = build_nonstandard_boolean_type (elem_bits); return build_vector_type_for_mode (bool_type, mode); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 3f9ee044e8e..0595e5726a7 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1141,11 +1141,13 @@ expand_const_vector (rtx target, rtx src) if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) { rtx elt; - gcc_assert ( - const_vec_duplicate_p (src, &elt) - && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); - rtx ops[] = {target, src}; - emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); + if (const_vec_duplicate_p (src, &elt)) + { + rtx ops[] = {target, src}; + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); + } + else + gcc_unreachable (); return; } diff --git a/gcc/fortran/trans-types.cc b/gcc/fortran/trans-types.cc index d718f28cc86..987e3d26c46 100644 --- a/gcc/fortran/trans-types.cc +++ b/gcc/fortran/trans-types.cc @@ -3403,7 +3403,7 @@ gfc_type_for_mode (machine_mode mode, int unsignedp) else if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL && valid_vector_subparts_p (GET_MODE_NUNITS (mode))) { - unsigned int elem_bits = vector_element_size (GET_MODE_BITSIZE (mode), + unsigned int elem_bits = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); tree bool_type = build_nonstandard_boolean_type (elem_bits); return build_vector_type_for_mode (bool_type, mode); diff --git a/gcc/go/go-lang.cc b/gcc/go/go-lang.cc index e85a4bfe949..d5c871a533c 100644 --- a/gcc/go/go-lang.cc +++ b/gcc/go/go-lang.cc @@ -414,7 +414,7 @@ go_langhook_type_for_mode (machine_mode mode, int unsignedp) if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL && valid_vector_subparts_p (GET_MODE_NUNITS (mode))) { - unsigned int elem_bits = vector_element_size (GET_MODE_BITSIZE (mode), + unsigned int elem_bits = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); tree bool_type = build_nonstandard_boolean_type (elem_bits); return build_vector_type_for_mode (bool_type, mode); diff --git a/gcc/lto/lto-lang.cc b/gcc/lto/lto-lang.cc index 52d7626e92e..14d419c2013 100644 --- a/gcc/lto/lto-lang.cc +++ b/gcc/lto/lto-lang.cc @@ -1050,7 +1050,7 @@ lto_type_for_mode (machine_mode mode, int unsigned_p) else if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL && valid_vector_subparts_p (GET_MODE_NUNITS (mode))) { - unsigned int elem_bits = vector_element_size (GET_MODE_BITSIZE (mode), + unsigned int elem_bits = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); tree bool_type = build_nonstandard_boolean_type (elem_bits); return build_vector_type_for_mode (bool_type, mode); diff --git a/gcc/rust/backend/rust-tree.cc b/gcc/rust/backend/rust-tree.cc index 8243d4cf5c6..66e859cd70c 100644 --- a/gcc/rust/backend/rust-tree.cc +++ b/gcc/rust/backend/rust-tree.cc @@ -5320,7 +5320,7 @@ c_common_type_for_mode (machine_mode mode, int unsignedp) && valid_vector_subparts_p (GET_MODE_NUNITS (mode))) { unsigned int elem_bits - = vector_element_size (GET_MODE_BITSIZE (mode), GET_MODE_NUNITS (mode)); + = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); tree bool_type = build_nonstandard_boolean_type (elem_bits); return build_vector_type_for_mode (bool_type, mode); } diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index 99cbdd47d93..d7315d82aa3 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -7076,7 +7076,7 @@ native_encode_rtx (machine_mode mode, rtx x, vec &bytes, /* CONST_VECTOR_ELT follows target memory order, so no shuffling is necessary. The only complication is that MODE_VECTOR_BOOL vectors can have several elements per byte. */ - unsigned int elt_bits = vector_element_size (GET_MODE_BITSIZE (mode), + unsigned int elt_bits = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); unsigned int elt = first_byte * BITS_PER_UNIT / elt_bits; if (elt_bits < BITS_PER_UNIT) @@ -7222,7 +7222,7 @@ native_decode_vector_rtx (machine_mode mode, const vec &bytes, { rtx_vector_builder builder (mode, npatterns, nelts_per_pattern); - unsigned int elt_bits = vector_element_size (GET_MODE_BITSIZE (mode), + unsigned int elt_bits = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); if (elt_bits < BITS_PER_UNIT) { @@ -7359,7 +7359,7 @@ simplify_const_vector_byte_offset (rtx x, poly_uint64 byte) { /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */ machine_mode mode = GET_MODE (x); - unsigned int elt_bits = vector_element_size (GET_MODE_BITSIZE (mode), + unsigned int elt_bits = vector_element_size (GET_MODE_PRECISION (mode), GET_MODE_NUNITS (mode)); /* The number of bits needed to encode one element from each pattern. */ unsigned int sequence_bits = CONST_VECTOR_NPATTERNS (x) * elt_bits; @@ -7414,10 +7414,10 @@ simplify_const_vector_subreg (machine_mode outermode, rtx x, /* Cope with MODE_VECTOR_BOOL by operating on bits rather than bytes. */ unsigned int x_elt_bits - = vector_element_size (GET_MODE_BITSIZE (innermode), + = vector_element_size (GET_MODE_PRECISION (innermode), GET_MODE_NUNITS (innermode)); unsigned int out_elt_bits - = vector_element_size (GET_MODE_BITSIZE (outermode), + = vector_element_size (GET_MODE_PRECISION (outermode), GET_MODE_NUNITS (outermode)); /* The number of bits needed to encode one element from every pattern diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c new file mode 100644 index 00000000000..81229fd62b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int64_t out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c new file mode 100644 index 00000000000..d891f3c16e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c new file mode 100644 index 00000000000..535641443ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 4 + +int +main () +{ + int mask[N] = {0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c new file mode 100644 index 00000000000..a7c12c3797b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ + +#include +#include +#define N 8 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c new file mode 100644 index 00000000000..726238c1cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */ + +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c new file mode 100644 index 00000000000..c369cf0b268 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c @@ -0,0 +1,24 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */ + +#include +#include +#define N 32 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c new file mode 100644 index 00000000000..a23e47171bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c new file mode 100644 index 00000000000..6ea8fdd89c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int16_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int16_t out[N] = {0}; + for (int16_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int16_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c new file mode 100644 index 00000000000..2d97c26abfd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c new file mode 100644 index 00000000000..b89b70e99a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */ + +#include +#include + +#define N 32 + +int +main () +{ + int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c new file mode 100644 index 00000000000..ac8d91e793b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */ + +#include +#include + +#define N 64 + +int +main () +{ + int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c new file mode 100644 index 00000000000..f538db23b1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ + +#include +#include + +#define N 128 + +int +main () +{ + uint8_t mask[N] + = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + uint8_t out[N] = {0}; + for (uint8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (uint8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c new file mode 100644 index 00000000000..5abb34c1686 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ + +#include +#include + +#define N 128 + +int +main () +{ + int mask[N] + = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c new file mode 100644 index 00000000000..6fdaa516534 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ + +#include +#include + +#define N 128 + +int +main () +{ + int64_t mask[N] + = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int64_t out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/tree.cc b/gcc/tree.cc index bd500ec72a5..420857b110c 100644 --- a/gcc/tree.cc +++ b/gcc/tree.cc @@ -10143,7 +10143,7 @@ build_truth_vector_type_for_mode (poly_uint64 nunits, machine_mode mask_mode) unsigned HOST_WIDE_INT esize; if (VECTOR_MODE_P (mask_mode)) { - poly_uint64 vsize = GET_MODE_BITSIZE (mask_mode); + poly_uint64 vsize = GET_MODE_PRECISION (mask_mode); esize = vector_element_size (vsize, nunits); } else diff --git a/gcc/varasm.cc b/gcc/varasm.cc index 8ae0a2555cd..53f0cc61922 100644 --- a/gcc/varasm.cc +++ b/gcc/varasm.cc @@ -4061,11 +4061,17 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x, unsigned int align) whole element. Often this is byte_mode and contains more than one element. */ unsigned int nelts = GET_MODE_NUNITS (mode); - unsigned int elt_bits = GET_MODE_BITSIZE (mode) / nelts; + unsigned int elt_bits = GET_MODE_PRECISION (mode) / nelts; unsigned int int_bits = MAX (elt_bits, BITS_PER_UNIT); scalar_int_mode int_mode = int_mode_for_size (int_bits, 0).require (); unsigned int mask = GET_MODE_MASK (GET_MODE_INNER (mode)); + /* We allow GET_MODE_PRECISION (mode) <= GET_MODE_BITSIZE (mode) but + only properly handle cases where the difference is less than a + byte. */ + gcc_assert (GET_MODE_BITSIZE (mode) - GET_MODE_PRECISION (mode) < + BITS_PER_UNIT); + /* Build the constant up one integer at a time. */ unsigned int elts_per_int = int_bits / elt_bits; for (unsigned int i = 0; i < nelts; i += elts_per_int) -- 2.41.0