[PATCH, i386] Fix movdi_internal to return MODE_TI with AVX512

["Shalnov, Sergey" <sergey.shalnov@intel.com>]

[-- Attachment #1: Type: text/plain, Size: 375 bytes --]

Hi,
I found wrong MODE_XI used in movdi_internal that cause zmm 
Generation with "-march=skylake-avx512 -mprefer-vector-width=128" 
options set. This patch fixes the mode and register type but keep using
AVX512 instruction set.

2017-11-28  Sergey Shalnov  <Sergey.Shalnov@intel.com>
gcc/
	* config/i386/i386.md: Fix AVX512 register width
	in AVX512 instruction.


[-- Attachment #2: 0009-Fix-AVX512-register-width-in-movdi_internal.patch --]
[-- Type: application/octet-stream, Size: 1358 bytes --]

From d46c73bb4c24839fab2c676e5745195ff5807d2c Mon Sep 17 00:00:00 2001
From: Sergey Shalnov <Sergey.Shalnov@intel.com>
Date: Tue, 28 Nov 2017 17:21:17 +0300
Subject: [PATCH 1/1] Fix AVX512 register width in movdi_internal

---
 gcc/config/i386/i386.md | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a14efc8..b4d73db 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2254,10 +2254,13 @@
 	      && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
 	    return "%vmovd\t{%1, %0|%0, %1}";
 	  return "%vmovq\t{%1, %0|%0, %1}";
+
 	case MODE_TI:
+	  /* Handle AVX512 registers set.  */
+	  if (EXT_REX_SSE_REG_P (operands[0])
+	      || EXT_REX_SSE_REG_P (operands[1]))
+	    return "vmovdqa64\t{%1, %0|%0, %1}";
 	  return "%vmovdqa\t{%1, %0|%0, %1}";
-	case MODE_XI:
-	  return "vmovdqa64\t{%g1, %g0|%g0, %g1}";
 
 	case MODE_V2SF:
 	  gcc_assert (!TARGET_AVX);
@@ -2349,7 +2352,7 @@
 	    (eq_attr "alternative" "12,13")
 	      (cond [(ior (match_operand 0 "ext_sse_reg_operand")
 			  (match_operand 1 "ext_sse_reg_operand"))
-		       (const_string "XI")
+		       (const_string "TI")
 		     (ior (not (match_test "TARGET_SSE2"))
 			  (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
 		       (const_string "V4SF")
-- 
1.8.3.1