From: Christophe LYON <christophe.lyon@foss.st.com>
To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 02/13] arm: Add tests for PR target/100757
Date: Tue, 28 Sep 2021 15:28:32 +0200 [thread overview]
Message-ID: <71756c7c-489a-8a26-23de-210503bc6552@foss.st.com> (raw)
In-Reply-To: <PAXPR08MB69265E89A01EDF7E17659E1793A89@PAXPR08MB6926.eurprd08.prod.outlook.com>
On 28/09/2021 13:12, Kyrylo Tkachov wrote:
>
>> -----Original Message-----
>> From: Gcc-patches <gcc-patches-
>> bounces+kyrylo.tkachov=arm.com@gcc.gnu.org> On Behalf Of Christophe
>> Lyon via Gcc-patches
>> Sent: 07 September 2021 10:15
>> To: gcc-patches@gcc.gnu.org
>> Subject: [PATCH 02/13] arm: Add tests for PR target/100757
>>
>> These tests currently trigger an ICE which is fixed later in the patch
>> series.
>>
>> The pr100757*.c testcases are derived from
>> gcc.c-torture/compile/20160205-1.c, forcing the use of MVE, and using
>> various types and return values different from 0 and 1 to avoid
>> commonalization with boolean masks. In addition, since we should not
>> need these masks, the tests make sure they are not present.
> Ok, but I'd rather it was committed together with the patch that fixes the ICE.
> I don't mind if it's a separate commit or rolled into that patch.
Sure, I'll wait for the main patch approval. I split it this way to
hopefully make the reviews easier, to exercise the testcase without the
fix proposal.
Thanks,
Christophe
>
> Thanks,
> Kyrill
>
>> 2021-09-01 Christophe Lyon <christophe.lyon@foss.st.com>
>>
>> gcc/testsuite/
>> PR target/100757
>> * gcc.target/arm/simd/pr100757-2.c: New.
>> * gcc.target/arm/simd/pr100757-3.c: New.
>> * gcc.target/arm/simd/pr100757-4.c: New.
>> * gcc.target/arm/simd/pr100757.c: New.
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c
>> b/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c
>> new file mode 100644
>> index 00000000000..c2262b4d81e
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-2.c
>> @@ -0,0 +1,20 @@
>> +/* { dg-do compile } */
>> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
>> +/* { dg-add-options arm_v8_1m_mve_fp } */
>> +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */
>> +/* Derived from gcc.c-torture/compile/20160205-1.c. */
>> +
>> +float a[32];
>> +int fn1(int d) {
>> + int c = 4;
>> + for (int b = 0; b < 32; b++)
>> + if (a[b] != 2.0f)
>> + c = 5;
>> + return c;
>> +}
>> +
>> +/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 4 } } */ /*
>> Constant 2.0f. */
>> +/* { dg-final { scan-assembler-times {\t.word\t4\n} 4 } } */ /* Initial value
>> for c. */
>> +/* { dg-final { scan-assembler-times {\t.word\t5\n} 4 } } */ /* Possible
>> value for c. */
>> +/* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */
>> +/* { dg-final { scan-assembler-not {\t.word\t0\n} } } */ /* 'false' mask. */
>> diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c
>> b/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c
>> new file mode 100644
>> index 00000000000..e604555c04c
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-3.c
>> @@ -0,0 +1,20 @@
>> +/* { dg-do compile } */
>> +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
>> +/* { dg-add-options arm_v8_1m_mve_fp } */
>> +/* { dg-additional-options "-O3 -funsafe-math-optimizations" } */
>> +/* Copied from gcc.c-torture/compile/20160205-1.c. */
>> +
>> +float a[32];
>> +float fn1(int d) {
>> + float c = 4.0f;
>> + for (int b = 0; b < 32; b++)
>> + if (a[b] != 2.0f)
>> + c = 5.0f;
>> + return c;
>> +}
>> +
>> +/* { dg-final { scan-assembler-times {\t.word\t1073741824\n} 4 } } */ /*
>> Constant 2.0f. */
>> +/* { dg-final { scan-assembler-times {\t.word\t1084227584\n} 4 } } */ /*
>> Initial value for c (4.0). */
>> +/* { dg-final { scan-assembler-times {\t.word\t1082130432\n} 4 } } */ /*
>> Possible value for c (5.0). */
>> +/* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */
>> +/* { dg-final { scan-assembler-not {\t.word\t0\n} } } */ /* 'false' mask. */
>> diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757-4.c
>> b/gcc/testsuite/gcc.target/arm/simd/pr100757-4.c
>> new file mode 100644
>> index 00000000000..c12040c517f
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757-4.c
>> @@ -0,0 +1,19 @@
>> +/* { dg-do compile } */
>> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
>> +/* { dg-add-options arm_v8_1m_mve } */
>> +/* { dg-additional-options "-O3" } */
>> +/* Derived from gcc.c-torture/compile/20160205-1.c. */
>> +
>> +unsigned int a[32];
>> +int fn1(int d) {
>> + int c = 2;
>> + for (int b = 0; b < 32; b++)
>> + if (a[b])
>> + c = 3;
>> + return c;
>> +}
>> +
>> +/* { dg-final { scan-assembler-times {\t.word\t0\n} 4 } } */ /* 'false' mask.
>> */
>> +/* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */
>> +/* { dg-final { scan-assembler-times {\t.word\t2\n} 4 } } */ /* Initial value
>> for c. */
>> +/* { dg-final { scan-assembler-times {\t.word\t3\n} 4 } } */ /* Possible
>> value for c. */
>> diff --git a/gcc/testsuite/gcc.target/arm/simd/pr100757.c
>> b/gcc/testsuite/gcc.target/arm/simd/pr100757.c
>> new file mode 100644
>> index 00000000000..41d6e4e2d7a
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/arm/simd/pr100757.c
>> @@ -0,0 +1,19 @@
>> +/* { dg-do compile } */
>> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
>> +/* { dg-add-options arm_v8_1m_mve } */
>> +/* { dg-additional-options "-O3" } */
>> +/* Derived from gcc.c-torture/compile/20160205-1.c. */
>> +
>> +int a[32];
>> +int fn1(int d) {
>> + int c = 2;
>> + for (int b = 0; b < 32; b++)
>> + if (a[b])
>> + c = 3;
>> + return c;
>> +}
>> +
>> +/* { dg-final { scan-assembler-times {\t.word\t0\n} 4 } } */ /* 'false' mask.
>> */
>> +/* { dg-final { scan-assembler-not {\t.word\t1\n} } } */ /* 'true' mask. */
>> +/* { dg-final { scan-assembler-times {\t.word\t2\n} 4 } } */ /* Initial value
>> for c. */
>> +/* { dg-final { scan-assembler-times {\t.word\t3\n} 4 } } */ /* Possible
>> value for c. */
>> --
>> 2.25.1
next prev parent reply other threads:[~2021-09-28 13:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-07 9:15 [PATCH 00/13] ARM/MVE use vectors of boolean for predicates Christophe Lyon
2021-09-07 9:15 ` [PATCH 01/13] arm: Add new tests for comparison vectorization with Neon and MVE Christophe Lyon
2021-09-28 11:11 ` Kyrylo Tkachov
2021-09-07 9:15 ` [PATCH 02/13] arm: Add tests for PR target/100757 Christophe Lyon
2021-09-28 11:12 ` Kyrylo Tkachov
2021-09-28 13:28 ` Christophe LYON [this message]
2021-09-07 9:15 ` [PATCH 03/13] arm: Add test for PR target/101325 Christophe Lyon
2021-09-28 11:14 ` Kyrylo Tkachov
2021-09-28 13:30 ` Christophe LYON
2021-10-11 12:43 ` Christophe LYON
2021-09-07 9:15 ` [PATCH 04/13] arm: Add GENERAL_AND_VPR_REGS regclass Christophe Lyon
2021-09-07 9:42 ` Richard Earnshaw
2021-09-07 12:05 ` Christophe LYON
2021-09-07 13:35 ` Richard Earnshaw
2021-09-08 7:48 ` Christophe LYON
2021-09-28 11:18 ` Kyrylo Tkachov
2021-09-28 13:32 ` Christophe LYON
2021-10-11 12:44 ` Christophe LYON
2021-09-13 8:33 ` [PATCH 00/13] ARM/MVE use vectors of boolean for predicates Christophe LYON
2021-09-20 9:21 ` Christophe LYON
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