From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id 55D673858C27 for ; Sat, 29 Apr 2023 15:05:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 55D673858C27 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1a9253d4551so7794805ad.0 for ; Sat, 29 Apr 2023 08:05:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682780754; x=1685372754; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=cp+CnApkHXd+gxcl2C6EwQN1NW6J9lPGIfxZAaMnzWk=; b=DUKoaXj/MtTTpfphyIZi6ZDW8pQMH+QR8oL01VtqaJdRe7s13/TTGVFsgnobCLjzdH +xa3VaxmTZv0CxlVD2QjwlskBoyQg3TaXlawZ1fQEQg/PCRO//tV9SOywT7o1TiAabS6 xithh69AzNZc8aPBsrZVPaZDy7zwPwTBQ3w3eq2RKAzr/dPpJ025CiNt283RZXJrA9+F /OOnnFLAXTCd/OGFygBtNRQ2K3KHQwgkSzNHC4eZiUT99VuHKo9bMdiN4XuaqE05eME7 PqYy9ylOaGJh6PEN6RAD3C2945d0MzKPC4957R2Ym3MWbSxBPfT0AwuM6E4pMfP9e2LH kvag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682780754; x=1685372754; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cp+CnApkHXd+gxcl2C6EwQN1NW6J9lPGIfxZAaMnzWk=; b=RqlnJoKSs5BYU+ktRanNZ8QbCCQ6QdSYwBSkNS6mGOZ3m6etCCXIqg4hdbe6xba3DH DGgEeGRUpBB3A6kkpbX8RG2q2d4wYvkp8sjJlQOnG49hT4KtVmrjvxp8BcXO+tl47eKj WU1a3puLutKScQJ85hk6Px9MSoHNm4JMEFBQuoPVzs4yP8Ottj5RLYqZdCEw1iEV+SpI NnGDkaA1Tm7PbAYqoouIpDnZUiSHx9juqjvWYw5hpg6I9d49xwqduQ1zWSxIn/VVQuDB GcfTPwlfZp3FkIRV3XkrMKgM3NpqJAqtLqVRdqAWssmJiJ5NaQuW4Pph+zhsgzyf7cUf Jkaw== X-Gm-Message-State: AC+VfDzawNCElaBGM/Twkx4h00Mw30yDVZY7va65/xt5S6DnP7d2QZUa b8Pf9If5s4MTdEz4i/9Mr3c= X-Google-Smtp-Source: ACHHUZ4TZQubGS3CgRHLWqhoLV7UdSfdU1LgUvqC64xnGV4uGMoZvsiryqaeGIq/JNYAiupAihhSww== X-Received: by 2002:a17:902:c94d:b0:1a6:6fe3:df9e with SMTP id i13-20020a170902c94d00b001a66fe3df9emr10820261pla.47.1682780753855; Sat, 29 Apr 2023 08:05:53 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::99f? ([2601:681:8600:13d0::99f]) by smtp.gmail.com with ESMTPSA id c10-20020a170902848a00b001a95f632340sm11782471plo.46.2023.04.29.08.05.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 29 Apr 2023 08:05:53 -0700 (PDT) Message-ID: <72057d65-d5d4-00fc-307a-709ab0a82822@gmail.com> Date: Sat, 29 Apr 2023 09:05:52 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET Content-Language: en-US To: "Li, Pan2" , "gcc-patches@gcc.gnu.org" Cc: "juzhe.zhong@rivai.ai" , "kito.cheng@sifive.com" , "Wang, Yanzhang" References: <20230428152102.1653600-1-pan2.li@intel.com> <2eeda95f-e645-6e73-7bc7-7b829a5bf70b@gmail.com> From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/28/23 20:55, Li, Pan2 wrote: > Thanks Jeff for comments. > > It makes sense to me. For the EQ operator we should have CONSTM1. That's not the way I interpret the RVV documentation. Of course it's not terribly clear. I guess one could do some experiments with qemu or try to dig into the sail code and figure out the intent from those. Does this mean s390 parts has similar issue here? Then for instructions like VMSEQ, we need to adjust the simplify_rtx up to a point. You'd have to refer to the s390 instruction set reference to understand precisely how the vector compares work. But as it stands this really isn't a simplify-rtx question, but a question of the semantics of risc-v. What happens with the high bits in the destination mask register is critical -- and if risc-v doesn't set them to all ones in this case, then that would mean that defining that macro is simply wrong for risc-v. jeff