Re: [PATCH] dwarf: Multi-register CFI address support

[Andrew Stubbs <ams@codesourcery.com>]

Ping.

On 21/09/2020 14:51, Andrew Stubbs wrote:
> Ping.
> 
> On 03/09/2020 16:29, Andrew Stubbs wrote:
>> On 28/08/2020 13:04, Andrew Stubbs wrote:
>>> Hi all,
>>>
>>> This patch introduces DWARF CFI support for architectures that 
>>> require multiple registers to hold pointers, such as the stack 
>>> pointer, frame pointer, and return address. The motivating case is 
>>> the AMD GCN architecture which has 64-bit address pointers, but 
>>> 32-bit registers.
>>>
>>> The current implementation permits program variables to span as many 
>>> registers as they need, but assumes that CFI expressions will only 
>>> need a single register for each frame value.
>>>
>>> To be fair, the DWARF standard makes a similar assumption; the 
>>> engineers working on LLVM and GDB, at AMD, have therefore invented 
>>> some new DWARF operators that they plan to propose for a future 
>>> standard. Only one is relevant here, however: DW_OP_LLVM_piece_end. 
>>> (Unfortunately this clashes with an AArch64 extension, but I think we 
>>> can cope using an alias -- only GCC dumps will be confusing.)
>>>
>>> My approach is to change the type representing a DWARF register 
>>> throughout the CFI code. This permits the register span information 
>>> to propagate to where it is needed.
>>>
>>> I've taken advantage of C++ struct copies and operator== to minimize 
>>> the amount of refactoring required. I'm not sure this meets the GCC 
>>> guidelines exactly, but if not I can change that once the basic form 
>>> is agreed. (I also considered an operator= to make assigning single 
>>> dwreg values transparent, but that hid too many invalid assumptions.)
>>>
>>> OK to commit? (Although, I'll hold off until AMD release the 
>>> compatible GDB.)
>>
>> Minor patch update, following Tom's feedback.
>>
>> Andrew
> 
>