From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18610 invoked by alias); 22 Sep 2014 10:49:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 18600 invoked by uid 89); 22 Sep 2014 10:49:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: na01-by2-obe.outbound.protection.outlook.com Received: from mail-by2on0064.outbound.protection.outlook.com (HELO na01-by2-obe.outbound.protection.outlook.com) (207.46.100.64) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 22 Sep 2014 10:49:14 +0000 Received: from BL2FFO11FD023.protection.gbl (10.173.160.30) by BL2FFO11HUB005.protection.gbl (10.173.160.225) with Microsoft SMTP Server (TLS) id 15.0.1029.15; Mon, 22 Sep 2014 10:49:10 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2FFO11FD023.mail.protection.outlook.com (10.173.161.102) with Microsoft SMTP Server (TLS) id 15.0.1029.15 via Frontend Transport; Mon, 22 Sep 2014 10:49:10 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1XW1BJ-0001Jx-GZ; Mon, 22 Sep 2014 03:49:21 -0700 From: Ajit Kumar Agarwal To: Richard Sandiford , Jeff Law CC: "gcc-patches@gcc.gnu.org" Subject: RE: [PATCH 0/5] Fix handling of word subregs of wide registers Date: Mon, 22 Sep 2014 10:49:00 -0000 References: <87ppetnsxd.fsf@e105548-lin.cambridge.arm.com> <541BC9A2.2030309@redhat.com> <87zjdwm5td.fsf@e105548-lin.cambridge.arm.com> <541C646E.8020505@redhat.com> <87ppeom83m.fsf@e105548-lin.cambridge.arm.com> In-Reply-To: <87ppeom83m.fsf@e105548-lin.cambridge.arm.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-RCIS-Action: ALLOW Message-ID: <72631d17-c273-4813-95b4-720cd50fc4c3@BL2FFO11FD023.protection.gbl> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(438002)(479174003)(377454003)(51704005)(13464003)(189002)(164054003)(24454002)(199003)(83072002)(87936001)(97756001)(31696002)(92566001)(83322001)(80022003)(74502003)(99396002)(2656002)(86362001)(85306004)(90102001)(93886004)(79102003)(92726001)(85852003)(64706001)(19580405001)(50986999)(20776003)(15975445006)(1496007)(19580395003)(47776003)(50466002)(104016003)(76482002)(107046002)(23726002)(6806004)(70736001)(76176999)(21056001)(54356999)(31966008)(4396001)(46102003)(44976005)(77982003)(81542003)(106116001)(46406003)(77096002)(95666004)(53416004)(81342003)(74662003)(74316001)(106466001)(120916001)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2FFO11HUB005;H:xsj-pvapsmtpgw01;FPR:;MLV:sfv;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 034215E98F Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=ajit.kumar.agarwal@xilinx.com; X-OriginatorOrg: xilinx.com X-SW-Source: 2014-09/txt/msg01793.txt.bz2 -----Original Message----- From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-owner@gcc.gnu.org] = On Behalf Of Richard Sandiford Sent: Monday, September 22, 2014 12:54 PM To: Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH 0/5] Fix handling of word subregs of wide registers Jeff Law writes: > On 09/19/14 01:23, Richard Sandiford wrote: >> Jeff Law writes: >>> On 09/18/14 04:07, Richard Sandiford wrote: >>>> This series is a cleaned-up version of: >>>> >>>> https://gcc.gnu.org/ml/gcc/2014-03/msg00163.html >>>> >>>> The underlying problem is that the semantics of subregs depend on=20 >>>> the word size. You can't have a subreg for byte 2 of a 4-byte=20 >>>> word, say, but you can have a subreg for word 2 of a 4-word value=20 >>>> (as well as lowpart subregs of that word, etc.). This causes=20 >>>> problems when an architecture has wider-than-word registers, since=20 >>>> the addressability of a word can then depend on which register=20 >>>> class is used. >>>> >>>> The register allocators need to fix up cases where a subreg turns=20 >>>> out to be invalid for a particular class. This is really an=20 >>>> extension of what we need to do for CANNOT_CHANGE_MODE_CLASS. >>>> >>>> Tested on x86_64-linux-gnu, powerpc64-linux-gnu and aarch64_be-elf. >>> I thought we fixed these problems long ago with the change to subreg_by= te?!? >> >> No, that was fixing something else. (I'm just about old enough to=20 >> remember that too!) The problem here is that (say): >> >> (subreg:SI (reg:DI X) 4) >> >> is independently addressable on little-endian AArch32 if X assigned=20 >> to a GPR, but not if X is assigned to a vector register. We need to=20 >> allow these kinds of subreg on pseudos in order to decompose=20 >> multiword arithmetic. It's then up to the RA to realise that a=20 >> reload would be needed if X were assigned to a vector register, since=20 >> the upper half of a vector register cannot be independently accessed. >> >> Note that you could write this example even with the old word-style=20 >> offsets and IIRC the effect would have been the same. > OK. So I kept thinking in terms of the byte offset stuff. But what=20 > you're tackling is related to the mess around the mode of the subreg=20 > having a different meaning if its smaller than a word vs word-sized or=20 > greater. > > Right? >>Yeah, that's right. Addressability is based on words, which is inconveni= ent when your registers are bigger than a word. If the architecture like Microblaze which doesn't support the 1 byte or 2 = byte registers. In this scenario what should be returned when SUBREG_WORD i= s used. Thanks, Richard