From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 59998 invoked by alias); 22 Aug 2019 14:43:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 59983 invoked by uid 89); 22 Aug 2019 14:43:11 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.9 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.1 spammy=ir, Ir X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 22 Aug 2019 14:43:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B4B39337; Thu, 22 Aug 2019 07:43:08 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.91]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5FF413F706; Thu, 22 Aug 2019 07:43:08 -0700 (PDT) To: gcc-patches@gcc.gnu.org From: "Richard Earnshaw (lists)" Subject: [Arm] Add 16-bit thumb alternatives to iorsi3_compare0[_scratch] Message-ID: <72ba3f0e-8bbd-0605-a4b7-0aaaffe74124@arm.com> Date: Thu, 22 Aug 2019 16:25:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------8D35530AA6032B0DC02F1FA7" X-SW-Source: 2019-08/txt/msg01576.txt.bz2 This is a multi-part message in MIME format. --------------8D35530AA6032B0DC02F1FA7 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 347 The iorsi3_compare0 and iorsi3_compare0_scratch patterns can make use of the 16-bit thumb orrs instruction if suitable registers are allocated. This patch adds the alternative to allow this to happen. * config/arm/arm.md (iorsi3_compare0): Add alternative for 16-bit thumb insn. (iorsi3_compare0_scratch): Likewise. Committed to trunk. R. --------------8D35530AA6032B0DC02F1FA7 Content-Type: text/x-patch; name="thumb-orrs.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="thumb-orrs.patch" Content-length: 1701 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 50e1b908f59..4ba246ceeee 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3339,27 +3339,33 @@ (define_peephole2 (define_insn "*iorsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") - (match_operand:SI 2 "arm_rhs_operand" "I,r")) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (compare:CC_NOOV + (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") + (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r,l,r") (ior:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "orrs%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "logics_imm,logics_reg")] + (set_attr "arch" "*,t2,*") + (set_attr "length" "4,2,4") + (set_attr "type" "logics_imm,logics_reg,logics_reg")] ) (define_insn "*iorsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") - (match_operand:SI 2 "arm_rhs_operand" "I,r")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=r,r"))] + (compare:CC_NOOV + (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") + (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r,l,r"))] "TARGET_32BIT" "orrs%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "logics_imm,logics_reg")] + (set_attr "arch" "*,t2,*") + (set_attr "length" "4,2,4") + (set_attr "type" "logics_imm,logics_reg,logics_reg")] ) (define_expand "xordi3" --------------8D35530AA6032B0DC02F1FA7--