From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 8A4DD383067C for ; Wed, 25 May 2022 20:29:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8A4DD383067C Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24PJjXp1012667; Wed, 25 May 2022 20:29:32 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g9hfp5krk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 May 2022 20:29:31 +0000 Received: from m0098420.ppops.net (m0098420.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 24PKTVKv021108; Wed, 25 May 2022 20:29:31 GMT Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g9hfp5kra-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 May 2022 20:29:31 +0000 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 24PKCxnv011328; Wed, 25 May 2022 20:29:30 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma02dal.us.ibm.com with ESMTP id 3g93v8ajbd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 May 2022 20:29:30 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 24PKTUXG41287992 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 25 May 2022 20:29:30 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 03DC1B2065; Wed, 25 May 2022 20:29:30 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 943E5B205F; Wed, 25 May 2022 20:29:29 +0000 (GMT) Received: from lexx (unknown [9.160.34.81]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 25 May 2022 20:29:29 +0000 (GMT) Message-ID: <7358d46022bb9da997c77c910a6c2b86518d3401.camel@vnet.ibm.com> Subject: Re: [PATCH, rs6000] Clean up the option_mask defines (part 2) From: will schmidt To: Segher Boessenkool , David Edelsohn Cc: GCC Patches , Will Schmidt Date: Wed, 25 May 2022 15:29:29 -0500 In-Reply-To: <6591013b62270c39c912f0c13c4cd12ffbaf75a2.camel@vnet.ibm.com> References: <6591013b62270c39c912f0c13c4cd12ffbaf75a2.camel@vnet.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: d460n56Vu7FRAbhtZELZjQOTg4-tOeZt X-Proofpoint-ORIG-GUID: yv_KefzUL0g2HSod-Yhr8fCNwAaKKKtB Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-25_05,2022-05-25_02,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 spamscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2205250095 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 May 2022 20:29:34 -0000 [PATCH, rs6000] Clean up the option_mask defines (part 2) Hi, This patch reworks most of the lingering MASK_* values to OPTION_MASK_* and removes the now redundant defines. Regtested OK on power10. OK for trunk? gcc/ * rs6000.h (RS6000_BTM_VSX, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_HTM, RS6000_BTM_POPCNTD, RS6000_BTM_DFP, RS6000_BTM_HARD_FLOAT, RS6000_BTM_LDBL128, RS6000_BTM_FLOAT128, RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA, RS6000_BTM_P10): Rework defines to use OPTION_MASK_. (MASK_DFP, MASK_DIRECT_MOVE, MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_MMA, MASK_MULTIPLE, MASK_NO_UPDATE, MASK_P8_VECTOR, MASK_P9_VECTOR, MASK_P9_MISC, MASK_POPCNTD, MASK_RECIP_PRECISION, MASK_SOFT_FLOAT, MASK_UPDATE, MASK_VSX, MASK_POWER10, MASK_P10_FUSION): Remove unused defines. * config/rs6000/rs6000-cpus.def (RS6000_CPU): Rework macro calls to use OPTION_MASK_ defines. * config/rs6000/darwin.h (TARGET_DEFAULT) Update define to use OPTION_MASK_MULTIPLE. * config/rs6000/darwin64-biarch.h (TARGET_DEFAULT): Same. diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 86556ccbbf58..6a8845eb3bb7 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -365,11 +365,11 @@ /* Default target flag settings. Despite the fact that STMW/LMW serializes, it's still a big code size win to use them. Use FSEL by default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD #define TARGET_IEEEQUAD 0 diff --git a/gcc/config/rs6000/darwin64-biarch.h b/gcc/config/rs6000/darwin64-biarch.h index 6a700c61c4c2..6515bcc8bf5a 100644 --- a/gcc/config/rs6000/darwin64-biarch.h +++ b/gcc/config/rs6000/darwin64-biarch.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) + | OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" /* Actually, there's really only 970 as an active option. */ diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index ca78bd8cf89f..4301b1bcb120 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -174,29 +174,31 @@ RS6000_CPU (NAME, CPU, FLAGS) where the arguments are the fields of struct rs6000_ptt. */ -RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) -RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) -RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | OPTION_MASK_MULHW - | OPTION_MASK_DLMZB) +RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) +RS6000_CPU ("405", PROCESSOR_PPC405, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW +RS6000_CPU ("440", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW +RS6000_CPU ("464", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | OPTION_MASK_PPC_GFXOPT - | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND - | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT - | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND - | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("476", PROCESSOR_PPC476, + OPTION_MASK_SOFT_FLOAT | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF + | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND | OPTION_MASK_CMPB + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("476fp", PROCESSOR_PPC476, + OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) -RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE) +RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE) RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT) @@ -204,35 +206,34 @@ RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) -RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) +RS6000_CPU ("801", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("821", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("823", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64 - | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB | MASK_NO_UPDATE) -RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) + | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB | OPTION_MASK_NO_UPDATE) +RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT) RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e5500", PROCESSOR_PPCE5500, MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 | OPTION_MASK_MFCRF | OPTION_MASK_ISEL) -RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("970", PROCESSOR_POWER4, - POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF - | MASK_POWERPC64) +RS6000_CPU ("860", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) RS6000_CPU ("cell", PROCESSOR_CELL, - POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF - | MASK_POWERPC64) -RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) + POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF + | MASK_POWERPC64) +RS6000_CPU ("ec603e", PROCESSOR_PPC603, OPTION_MASK_SOFT_FLOAT) RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64) RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) @@ -245,16 +246,16 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND) RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB - | OPTION_MASK_FPRND | OPTION_MASK_CMPB | MASK_DFP - | MASK_RECIP_PRECISION) + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP + | OPTION_MASK_RECIP_PRECISION) RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB - | OPTION_MASK_FPRND | OPTION_MASK_CMPB | MASK_DFP - | MASK_RECIP_PRECISION) + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP + | OPTION_MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index ef7f10e4efee..dcf632c1f1ad 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -505,31 +505,11 @@ extern int rs6000_vector_align[]; && (TARGET_P9_MINMAX || !flag_trapping_math)) /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. For now map OPTION_MASK_ back into MASK_. */ -#define MASK_DFP OPTION_MASK_DFP -#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE -#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD -#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW -#define MASK_P8_FUSION OPTION_MASK_P8_FUSION -#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT -#define MASK_HTM OPTION_MASK_HTM -#define MASK_MMA OPTION_MASK_MMA -#define MASK_MULTIPLE OPTION_MASK_MULTIPLE -#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE -#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR -#define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR -#define MASK_P9_MISC OPTION_MASK_P9_MISC -#define MASK_POPCNTD OPTION_MASK_POPCNTD -#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION -#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN -#define MASK_UPDATE OPTION_MASK_UPDATE -#define MASK_VSX OPTION_MASK_VSX -#define MASK_POWER10 OPTION_MASK_POWER10 -#define MASK_P10_FUSION OPTION_MASK_P10_FUSION #ifndef IN_LIBGCC2 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 #endif @@ -2241,31 +2221,31 @@ extern int frame_pointer_needed; target flags, and pick a random bit for ldbl128, which isn't in target_flags. */ #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALTIVEC OPTION_MASK_ALTIVEC /* VMX/altivec vectors. */ #define RS6000_BTM_CMPB OPTION_MASK_CMPB /* ISA 2.05: compare bytes. */ -#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ -#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ -#define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ -#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ +#define RS6000_BTM_VSX OPTION_MASK_VSX /* VSX (vector/scalar). */ +#define RS6000_BTM_P8_VECTOR OPTION_MASK_P8_VECTOR /* ISA 2.07 vector. */ +#define RS6000_BTM_P9_VECTOR OPTION_MASK_P9_VECTOR /* ISA 3.0 vector. */ +#define RS6000_BTM_P9_MISC OPTION_MASK_P9_MISC /* ISA 3.0 misc. non-vector */ #define RS6000_BTM_CRYPTO OPTION_MASK_CRYPTO /* crypto funcs. */ -#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ +#define RS6000_BTM_HTM OPTION_MASK_HTM /* hardware TM funcs. */ #define RS6000_BTM_FRE OPTION_MASK_POPCNTB /* FRE instruction. */ #define RS6000_BTM_FRES OPTION_MASK_PPC_GFXOPT /* FRES instruction. */ #define RS6000_BTM_FRSQRTE OPTION_MASK_PPC_GFXOPT /* FRSQRTE instruction. */ #define RS6000_BTM_FRSQRTES OPTION_MASK_POPCNTB /* FRSQRTES instruction. */ -#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ +#define RS6000_BTM_POPCNTD OPTION_MASK_POPCNTD /* Target supports ISA 2.06. */ #define RS6000_BTM_CELL OPTION_MASK_FPRND /* Target is cell powerpc. */ -#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ -#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ -#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ +#define RS6000_BTM_DFP OPTION_MASK_DFP /* Decimal floating point. */ +#define RS6000_BTM_HARD_FLOAT OPTION_MASK_SOFT_FLOAT /* Hardware floating point. */ +#define RS6000_BTM_LDBL128 OPTION_MASK_MULTIPLE /* 128-bit long double. */ #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ -#define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ -#define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ -#define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ -#define RS6000_BTM_P10 MASK_POWER10 +#define RS6000_BTM_FLOAT128 OPTION_MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ +#define RS6000_BTM_FLOAT128_HW OPTION_MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ +#define RS6000_BTM_MMA OPTION_MASK_MMA /* ISA 3.1 MMA. */ +#define RS6000_BTM_P10 OPTION_MASK_POWER10 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ | RS6000_BTM_P8_VECTOR \ | RS6000_BTM_P9_VECTOR \