From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id D4FE93858412 for ; Mon, 1 Aug 2022 02:00:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D4FE93858412 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2710kEdl020109; Mon, 1 Aug 2022 02:00:42 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3hp4k4sd8j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 01 Aug 2022 02:00:41 +0000 Received: from m0098419.ppops.net (m0098419.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2711dp0k019673; Mon, 1 Aug 2022 02:00:41 GMT Received: from ppma06ams.nl.ibm.com (66.31.33a9.ip4.static.sl-reverse.com [169.51.49.102]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3hp4k4sd17-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 01 Aug 2022 02:00:40 +0000 Received: from pps.filterd (ppma06ams.nl.ibm.com [127.0.0.1]) by ppma06ams.nl.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 2711pRU3010382; Mon, 1 Aug 2022 02:00:23 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma06ams.nl.ibm.com with ESMTP id 3hmuwhsjms-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 01 Aug 2022 02:00:23 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27120KMG27787728 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 1 Aug 2022 02:00:20 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 062F64C040; Mon, 1 Aug 2022 02:00:20 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B0894C044; Mon, 1 Aug 2022 02:00:18 +0000 (GMT) Received: from [9.200.45.162] (unknown [9.200.45.162]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 1 Aug 2022 02:00:18 +0000 (GMT) Message-ID: <765f6603-75ef-d093-e195-24c0d1552c60@linux.ibm.com> Date: Mon, 1 Aug 2022 10:00:13 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Ping [PATCH v3] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453] Content-Language: en-US From: HAO CHEN GUI To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner References: In-Reply-To: Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mhnWhRE4S7W9oD1XVeHeKeJ-2Oe5xlZ0 X-Proofpoint-GUID: TyIkNWGBUKf6ZXUeM34HPfI57kLlDrcB Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-31_20,2022-07-28_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2208010007 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Aug 2022 02:00:44 -0000 Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598685.html Thanks. On 22/7/2022 下午 3:07, HAO CHEN GUI wrote: > Hi, > This patch creates a new function - change_pseudo_and_mask. If recog fails, > the function converts a single pseudo to the pseudo AND with a mask if the > outer operator is IOR/XOR/PLUS and inner operator is ASHIFT or AND. The > conversion helps pattern to match rotate and mask insn on some targets. > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. > Is this okay for trunk? Any recommendations? Thanks a lot. > > ChangeLog > 2022-07-22 Haochen Gui > > gcc/ > PR target/93453 > * combine.cc (change_pseudo_and_mask): New. > (recog_for_combine): If recog fails, try again with the pattern > modified by change_pseudo_and_mask. > * config/rs6000/rs6000.md (plus_ior_xor): Remove. > (anonymous split pattern for plus_ior_xor): Remove. > > gcc/testsuite/ > PR target/93453 > * gcc.target/powerpc/pr93453-2.c: New. > * gcc.target/powerpc/rlwimi-2.c: Both 32/64 bit platforms generate the > same number of rlwimi. Reset the counter. > > patch.diff > diff --git a/gcc/combine.cc b/gcc/combine.cc > index a5fabf397f7..e1c1aa7da1c 100644 > --- a/gcc/combine.cc > +++ b/gcc/combine.cc > @@ -11599,6 +11599,48 @@ change_zero_ext (rtx pat) > return changed; > } > > +/* When the outer code of set_src is IOR/XOR/PLUS and the inner code is > + ASHIFT/AND, convert a pseudo to pseudo AND with a mask if its nonzero_bits > + is less than its mode mask. The nonzero_bits in later passes is not a > + superset of what is known in combine pass. So an insn with nonzero_bits > + can't be recoged later. */ > +static bool > +change_pseudo_and_mask (rtx pat) > +{ > + rtx src = SET_SRC (pat); > + if ((GET_CODE (src) == IOR > + || GET_CODE (src) == XOR > + || GET_CODE (src) == PLUS) > + && (((GET_CODE (XEXP (src, 0)) == ASHIFT > + || GET_CODE (XEXP (src, 0)) == AND) > + && REG_P (XEXP (src, 1))))) > + { > + rtx reg = XEXP (src, 1); > + machine_mode mode = GET_MODE (reg); > + unsigned HOST_WIDE_INT nonzero = nonzero_bits (reg, mode); > + if (nonzero < GET_MODE_MASK (mode)) > + { > + int shift; > + > + if (GET_CODE (XEXP (src, 0)) == ASHIFT) > + shift = INTVAL (XEXP (XEXP (src, 0), 1)); > + else > + shift = ctz_hwi (INTVAL (XEXP (XEXP (src, 0), 1))); > + > + if (shift > 0 > + && (HOST_WIDE_INT_1U << shift) - 1 >= nonzero) > + { > + unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << shift) - 1; > + rtx x = gen_rtx_AND (mode, reg, GEN_INT (mask)); > + SUBST (XEXP (SET_SRC (pat), 1), x); > + maybe_swap_commutative_operands (SET_SRC (pat)); > + return true; > + } > + } > + } > + return false; > +} > + > /* Like recog, but we receive the address of a pointer to a new pattern. > We try to match the rtx that the pointer points to. > If that fails, we may try to modify or replace the pattern, > @@ -11646,7 +11688,10 @@ recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) > } > } > else > - changed = change_zero_ext (pat); > + { > + changed = change_pseudo_and_mask (pat); > + changed |= change_zero_ext (pat); > + } > } > else if (GET_CODE (pat) == PARALLEL) > { > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index 1367a2cb779..2bd6bd5f908 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -4207,24 +4207,6 @@ (define_insn_and_split "*rotl3_insert_3_" > (ior:GPR (and:GPR (match_dup 3) (match_dup 4)) > (ashift:GPR (match_dup 1) (match_dup 2))))]) > > -(define_code_iterator plus_ior_xor [plus ior xor]) > - > -(define_split > - [(set (match_operand:GPR 0 "gpc_reg_operand") > - (plus_ior_xor:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand") > - (match_operand:SI 2 "const_int_operand")) > - (match_operand:GPR 3 "gpc_reg_operand")))] > - "nonzero_bits (operands[3], mode) > - < HOST_WIDE_INT_1U << INTVAL (operands[2])" > - [(set (match_dup 0) > - (ior:GPR (and:GPR (match_dup 3) > - (match_dup 4)) > - (ashift:GPR (match_dup 1) > - (match_dup 2))))] > -{ > - operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1); > -}) > - > (define_insn "*rotlsi3_insert_4" > [(set (match_operand:SI 0 "gpc_reg_operand" "=r") > (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0") > diff --git a/gcc/testsuite/gcc.target/powerpc/pr93453-2.c b/gcc/testsuite/gcc.target/powerpc/pr93453-2.c > new file mode 100644 > index 00000000000..a83a6511653 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr93453-2.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > + > +long foo (char a, long b) > +{ > + long c = a; > + c = c | (b << 12); > + return c; > +} > + > +long bar (long b, char a) > +{ > + long c = a; > + long m = -4096; > + c = c | (b & m); > + return c; > +} > + > +/* { dg-final { scan-assembler-times {\mrl[wd]imi\M} 2 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c > index bafa371db73..d4dadacc6cc 100644 > --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c > +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c > @@ -8,8 +8,7 @@ > /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ > /* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */ > > -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */ > -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */ > +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 } } */ > > /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */ > > >