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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2022 16:58:55.9214 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea68b496-aea1-4e79-372c-08da90f24040 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT059.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB9100 X-Spam-Status: No, score=-14.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 9/7/22 15:42, Kyrylo Tkachov wrote: > > >> -----Original Message----- >> From: Christophe Lyon >> Sent: Wednesday, September 7, 2022 2:41 PM >> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org >> Subject: Re: [PATCH] arm: Fix constant immediates predicates and >> constraints for some MVE builtins >> >> >> >> On 9/7/22 15:34, Kyrylo Tkachov wrote: >>> Hi Christophe, >>> >>>> -----Original Message----- >>>> From: Gcc-patches >>> bounces+kyrylo.tkachov=arm.com@gcc.gnu.org> On Behalf Of Christophe >>>> Lyon via Gcc-patches >>>> Sent: Wednesday, September 7, 2022 2:03 PM >>>> To: gcc-patches@gcc.gnu.org >>>> Subject: [PATCH] arm: Fix constant immediates predicates and constraints >> for >>>> some MVE builtins >>>> >>>> Several MVE builtins incorrectly use the same predicate/constraint >>>> pair for several modes, which does not match the specification. >>>> This patch uses the appropriate iterator instead. >>>> >>> >>> This looks ok to me. >>> I presume you've tested this appropriately? >> >> I tested it manually with an offending testcase. >> >> Unfortunately, the existing testcases all use '1' as immediate, so this >> does not really check the boundaries. We do plan to improve the existing >> tests in a later patch that will more generally improve the MVE tests. > > Sure, improving the tests is definitely worth it here. > I meant more in the context of a standard bootstrap and testsuite run. OK, just ran a bootstrap on arm-linux-gnueabihf, no issue, and regression tested on a cross arm-eabi with the default RUNTESTFLAGS/target-board, no issue either. Thanks, Christophe > Thanks, > Kyrill > >> >> Christophe >> >>> If so, ok for trunk. >>> Thanks, >>> Kyrill >>> >>>> 2022-09-06 Christophe Lyon >>>> >>>> gcc/ >>>> * config/arm/mve.md (mve_vqshluq_n_s): Use >>>> MVE_pred/MVE_constraint instead of mve_imm_7/Ra. >>>> (mve_vqshluq_m_n_s): Likewise. >>>> (mve_vqrshrnbq_n_): Use >>>> MVE_pred3/MVE_constraint3 >>>> instead of mve_imm_8/Rb. >>>> (mve_vqrshrunbq_n_s): Likewise. >>>> (mve_vqrshrntq_n_): Likewise. >>>> (mve_vqrshruntq_n_s): Likewise. >>>> (mve_vrshrnbq_n_): Likewise. >>>> (mve_vrshrntq_n_): Likewise. >>>> (mve_vqrshrnbq_m_n_): Likewise. >>>> (mve_vqrshrntq_m_n_): Likewise. >>>> (mve_vrshrnbq_m_n_): Likewise. >>>> (mve_vrshrntq_m_n_): Likewise. >>>> (mve_vqrshrunbq_m_n_s): Likewise. >>>> (mve_vsriq_n_>>> instead >>>> of mve_imm_selective_upto_8/Rg. >>>> (mve_vsriq_m_n_): Likewise. >>>> --- >>>> gcc/config/arm/mve.md | 30 +++++++++++++++--------------- >>>> 1 file changed, 15 insertions(+), 15 deletions(-) >>>> >>>> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md >>>> index c4dec01baac..714178609f7 100644 >>>> --- a/gcc/config/arm/mve.md >>>> +++ b/gcc/config/arm/mve.md >>>> @@ -1624,7 +1624,7 @@ (define_insn "mve_vqshluq_n_s" >>>> [ >>>> (set (match_operand:MVE_2 0 "s_register_operand" "=w") >>>> (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" >>>> "w") >>>> - (match_operand:SI 2 "mve_imm_7" "Ra")] >>>> + (match_operand:SI 2 "" >>>> "")] >>>> VQSHLUQ_N_S)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -2615,7 +2615,7 @@ (define_insn >> "mve_vqrshrnbq_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 >>>> "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb")] >>>> + (match_operand:SI 3 "" >>>> "")] >>>> VQRSHRNBQ_N)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -2630,7 +2630,7 @@ (define_insn "mve_vqrshrunbq_n_s" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 >>>> "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb")] >>>> + (match_operand:SI 3 "" >>>> "")] >>>> VQRSHRUNBQ_N_S)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -3570,7 +3570,7 @@ (define_insn "mve_vsriq_n_" >>>> (set (match_operand:MVE_2 0 "s_register_operand" "=w") >>>> (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" >>>> "0") >>>> (match_operand:MVE_2 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_selective_upto_8" >>>> "Rg")] >>>> + (match_operand:SI 3 "" >>>> "")] >>>> VSRIQ_N)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -4473,7 +4473,7 @@ (define_insn >> "mve_vqrshrntq_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb")] >>>> + (match_operand:SI 3 "" >>>> "")] >>>> VQRSHRNTQ_N)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -4489,7 +4489,7 @@ (define_insn "mve_vqrshruntq_n_s" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb")] >>>> + (match_operand:SI 3 "" >>>> "")] >>>> VQRSHRUNTQ_N_S)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -4777,7 +4777,7 @@ (define_insn >> "mve_vrshrnbq_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb")] >>>> + (match_operand:SI 3 "" >>>> "")] >>>> VRSHRNBQ_N)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -4793,7 +4793,7 @@ (define_insn "mve_vrshrntq_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb")] >>>> + (match_operand:SI 3 "" >>>> "")] >>>> VRSHRNTQ_N)) >>>> ] >>>> "TARGET_HAVE_MVE" >>>> @@ -4987,7 +4987,7 @@ (define_insn "mve_vqshluq_m_n_s" >>>> (set (match_operand:MVE_2 0 "s_register_operand" "=w") >>>> (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" >>>> "0") >>>> (match_operand:MVE_2 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_7" "Ra") >>>> + (match_operand:SI 3 "" >>>> "") >>>> (match_operand: 4 >>>> "vpr_register_operand" "Up")] >>>> VQSHLUQ_M_N_S)) >>>> ] >>>> @@ -5019,7 +5019,7 @@ (define_insn "mve_vsriq_m_n_" >>>> (set (match_operand:MVE_2 0 "s_register_operand" "=w") >>>> (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" >>>> "0") >>>> (match_operand:MVE_2 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") >>>> + (match_operand:SI 3 "" >>>> "") >>>> (match_operand: 4 >>>> "vpr_register_operand" "Up")] >>>> VSRIQ_M_N)) >>>> ] >>>> @@ -6138,7 +6138,7 @@ (define_insn >>>> "mve_vqrshrnbq_m_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb") >>>> + (match_operand:SI 3 "" >>>> "") >>>> (match_operand: 4 >>>> "vpr_register_operand" "Up")] >>>> VQRSHRNBQ_M_N)) >>>> ] >>>> @@ -6155,7 +6155,7 @@ (define_insn >>>> "mve_vqrshrntq_m_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb") >>>> + (match_operand:SI 3 "" >>>> "") >>>> (match_operand: 4 >>>> "vpr_register_operand" "Up")] >>>> VQRSHRNTQ_M_N)) >>>> ] >>>> @@ -6223,7 +6223,7 @@ (define_insn >>>> "mve_vrshrnbq_m_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb") >>>> + (match_operand:SI 3 "" >>>> "") >>>> (match_operand: 4 >>>> "vpr_register_operand" "Up")] >>>> VRSHRNBQ_M_N)) >>>> ] >>>> @@ -6240,7 +6240,7 @@ (define_insn >> "mve_vrshrntq_m_n_" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb") >>>> + (match_operand:SI 3 "" >>>> "") >>>> (match_operand: 4 >>>> "vpr_register_operand" "Up")] >>>> VRSHRNTQ_M_N)) >>>> ] >>>> @@ -6461,7 +6461,7 @@ (define_insn >> "mve_vqrshrunbq_m_n_s" >>>> (set (match_operand: 0 "s_register_operand" "=w") >>>> (unspec: [(match_operand: 1 >>>> "s_register_operand" "0") >>>> (match_operand:MVE_5 2 "s_register_operand" "w") >>>> - (match_operand:SI 3 "mve_imm_8" "Rb") >>>> + (match_operand:SI 3 "" >>>> "") >>>> (match_operand: 4 >>>> "vpr_register_operand" "Up")] >>>> VQRSHRUNBQ_M_N_S)) >>>> ] >>>> -- >>>> 2.34.1 >>>