From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 53762 invoked by alias); 12 May 2015 05:22:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 53750 invoked by uid 89); 12 May 2015 05:22:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.2 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS autolearn=no version=3.3.2 X-HELO: na01-bn1-obe.outbound.protection.outlook.com Received: from mail-bn1on0132.outbound.protection.outlook.com (HELO na01-bn1-obe.outbound.protection.outlook.com) (157.56.110.132) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA256 encrypted) ESMTPS; Tue, 12 May 2015 05:22:01 +0000 Received: from BN1PR02CA0048.namprd02.prod.outlook.com (10.141.56.48) by BN3PR02MB1110.namprd02.prod.outlook.com (25.162.168.140) with Microsoft SMTP Server (TLS) id 15.1.154.19; Tue, 12 May 2015 05:21:57 +0000 Received: from BY2FFO11FD006.protection.gbl (2a01:111:f400:7c0c::187) by BN1PR02CA0048.outlook.office365.com (2a01:111:e400:2a::48) with Microsoft SMTP Server (TLS) id 15.1.160.19 via Frontend Transport; Tue, 12 May 2015 05:21:57 +0000 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; codesourcery.com; dkim=none (message not signed) header.d=none; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from atltwp01.amd.com (165.204.84.221) by BY2FFO11FD006.mail.protection.outlook.com (10.1.14.127) with Microsoft SMTP Server id 15.1.160.8 via Frontend Transport; Tue, 12 May 2015 05:21:56 +0000 X-M-MSG: Received: from satlvexedge02.amd.com (satlvexedge02.amd.com [10.177.96.29]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.3.1) with ESMTPS id 209B8CAE616; Tue, 12 May 2015 01:21:55 -0400 (EDT) Received: from SATLEXDAG04.amd.com (10.181.40.9) by SATLVEXEDGE02.amd.com (10.177.96.29) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 12 May 2015 00:21:57 -0500 Received: from SATLEXDAG06.amd.com ([fe80::1557:d877:7f65:c17]) by satlexdag04.amd.com ([fe80::75a7:6e1c:3fca:9723%23]) with mapi id 14.03.0195.001; Tue, 12 May 2015 01:21:54 -0400 From: "Kumar, Venkataramanan" To: "sellcey@imgtec.com" CC: Segher Boessenkool , "Jeff Law (law@redhat.com)" , "gcc-patches@gcc.gnu.org" , "maxim.kuvyrkov@linaro.org" , Matthew Fortune , clm Subject: RE: [RFC]: Remove Mem/address type assumption in combiner Date: Tue, 12 May 2015 06:43:00 -0000 Message-ID: <7794A52CE4D579448B959EED7DD0A4723DD02CD7@satlexdag06.amd.com> References: <7794A52CE4D579448B959EED7DD0A4723DCF68C1@satlexdag06.amd.com> <1431366602.14613.210.camel@ubuntu-sellcey> In-Reply-To: <1431366602.14613.210.camel@ubuntu-sellcey> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BY2FFO11FD006;1:8W2bkGUM50schSxQyjqsuMJbh9/eWh73XSwlst5OZ/JlZboHts0O7NG+zuRZipEzVhFyz2n0i94UW0Qa4GjToPHWI8dh/9rPvgrZUE5zT01vJ+Re9MAxRzlAZmrgpHyuF3HJsLedVq0597qzP5s+DorEUK9UGcGAKXLUlnWIBs3dQSU61Ucv3yWzHc0pVayZ9qq2tfQVaM1oM1DO9ECcsU2Xofx+jZsRNqPTSTy1NSFzcqB7UfG8oMGr3myHXlYiDIvw5+XqnXbyee5uVU0eZyUu6DHx3ImUW3th5IoTcr+LCfSn86ErWa3znwsJC+Cr X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(377454003)(377424004)(13464003)(76104003)(24454002)(189002)(51704005)(199003)(23726002)(2920100001)(76176999)(101416001)(106466001)(62966003)(50986999)(54356999)(105586002)(102836002)(77156002)(2351001)(2656002)(46406003)(87936001)(5250100002)(97756001)(19580405001)(92566002)(33656002)(2900100001)(50466002)(55846006)(189998001)(15975445007)(46102003)(110136002)(53416004)(2950100001)(19580395003)(2501003)(86362001)(47776003);DIR:OUT;SFP:1102;SCL:1;SRVR:BN3PR02MB1110;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1110; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BN3PR02MB1110;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1110; X-Forefront-PRVS: 0574D4712B X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2015 05:21:56.3040 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR02MB1110 X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg01029.txt.bz2 Hi Steve,=20 Yes this is expected. As Segher pointed out, we need to change .md pattern= s in target to be based on shifts instead of mults. Regards, Venkat. -----Original Message----- From: Steve Ellcey [mailto:sellcey@imgtec.com]=20 Sent: Monday, May 11, 2015 11:20 PM To: Kumar, Venkataramanan Cc: Segher Boessenkool; Jeff Law (law@redhat.com); gcc-patches@gcc.gnu.org;= maxim.kuvyrkov@linaro.org; Matthew Fortune; clm Subject: RE: [RFC]: Remove Mem/address type assumption in combiner On Thu, 2015-05-07 at 11:01 +0000, Kumar, Venkataramanan wrote: > Hi Segher, >=20 > Thank you I committed as r222874.=20 > Ref: https://gcc.gnu.org/viewcvs/gcc?view=3Drevision&revision=3D222874 >=20 > Regards, > Venkat. Venkat, This patch broke a number of MIPS tests, specifically mips32r6 tests that l= ook for the lsa instruction (load scaled address) which shifts one register= and then adds it to a second register. I am not sure if this needs to be = addressed in combine.c or if we need to add a peephole optimization to mips= .md to handle the new instruction sequence. What do you think? Is the cha= nge here what you would expect to see from your patch? With this C code: signed short test (signed short *a, int index) { return a[index]; } GCC/combine for mips32r6 used to produce: (insn 8 7 9 2 (set (reg/f:SI 203) (plus:SI (mult:SI (reg:SI 5 $5 [ index ]) (const_int 2 [0x2])) (reg:SI 4 $4 [ a ]))) lsa.c:3 444 {lsa} (expr_list:REG_DEAD (reg:SI 5 $5 [ index ]) (expr_list:REG_DEAD (reg:SI 4 $4 [ a ]) (nil)))) (insn 15 10 16 2 (set (reg/i:SI 2 $2) (sign_extend:SI (mem:HI (reg/f:SI 203) [1 *_5+0 S2 A16]))) lsa.c:4 237 {*extendhisi2_seh} (expr_list:REG_DEAD (reg/f:SI 203) (nil))) And would generate: lsa $4,$5,$4,1 lh $2,0($4) =09 But now it produces: (insn 7 4 8 2 (set (reg:SI 202) (ashift:SI (reg:SI 5 $5 [ index ]) (const_int 1 [0x1]))) lsa.c:3 432 {*ashlsi3} (expr_list:REG_DEAD (reg:SI 5 $5 [ index ]) (nil))) (insn 8 7 9 2 (set (reg/f:SI 203) (plus:SI (reg:SI 4 $4 [ a ]) (reg:SI 202))) lsa.c:3 13 {*addsi3} (expr_list:REG_DEAD (reg:SI 4 $4 [ a ]) (expr_list:REG_DEAD (reg:SI 202) (nil))) (insn 15 10 16 2 (set (reg/i:SI 2 $2) (sign_extend:SI (mem:HI (reg/f:SI 203) [1 *_5+0 S2 A16]))) lsa.c:4 237 {*extendhisi2_seh} (expr_list:REG_DEAD (reg/f:SI 203) (nil))) Which generates: sll $5,$5,1 addu $4,$4,$5 lh $2,0($4) Steve Ellcey sellcey@imgtec.com