From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 4635A3858D35 for ; Mon, 22 May 2023 18:11:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4635A3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=us.ibm.com Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34MI1Rub025338; Mon, 22 May 2023 18:11:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : subject : from : to : cc : date : in-reply-to : references : content-type : mime-version : content-transfer-encoding; s=pp1; bh=zpgp21Ns2976jZRlDjB58YEpHhrYuJdlgQ7CKZrHn7g=; b=GimiJ4KKSZEJe2crhMhwp6aM8u4r+Lhb5HOhisJjtlQujAoHhcyx6hX7KG6Sx5NaWzRc /OjwT/yCO80TUSPkp4AGgkmQhw/YdKXWA1dfQuynvVejvhm9Z3Llqq50PL8wUzl3oNGf QvOPV7HELW7QeDQGd7wfnfU8+Y+HIQtW4fHFS6m2tdualD4PlJZDoJVe2msYFN7wP2KB GaaVDhsz3AKVOe49BZw519a7Yd48/NEoDk3r2ivKQVJf63V1jdsErpWctvQrXV+yRjwU qqmbFD3s5vJeQCpmCTgO1X6Do9vD91aLU9KLGZDqBtNDAn/p8WpSJcl1TEHu937vvJ+D Ug== Received: from ppma01dal.us.ibm.com (83.d6.3fa9.ip4.static.sl-reverse.com [169.63.214.131]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qrdacg8uq-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 May 2023 18:11:44 +0000 Received: from pps.filterd (ppma01dal.us.ibm.com [127.0.0.1]) by ppma01dal.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 34MHAM5C016415; Mon, 22 May 2023 17:36:53 GMT Received: from smtprelay04.dal12v.mail.ibm.com ([9.208.130.102]) by ppma01dal.us.ibm.com (PPS) with ESMTPS id 3qppdsp4rx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 May 2023 17:36:53 +0000 Received: from smtpav05.wdc07v.mail.ibm.com (smtpav05.wdc07v.mail.ibm.com [10.39.53.232]) by smtprelay04.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 34MHaplv58261952 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 22 May 2023 17:36:52 GMT Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 983D658063; Mon, 22 May 2023 17:36:51 +0000 (GMT) Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 12FBE5806B; Mon, 22 May 2023 17:36:51 +0000 (GMT) Received: from li-e362e14c-2378-11b2-a85c-87d605f3c641.ibm.com (unknown [9.163.31.184]) by smtpav05.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 22 May 2023 17:36:50 +0000 (GMT) Message-ID: <79d6f621a9f0420fb3f2571eaa65f9d332dd7545.camel@us.ibm.com> Subject: [PATCH v3] rs6000: Add buildin for mffscrn instructions From: Carl Love To: "Kewen.Lin" Cc: Peter Bergner , Segher Boessenkool , gcc-patches@gcc.gnu.org Date: Mon, 22 May 2023 10:36:50 -0700 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: xbT50irScEGomuey2tlkjLY57CfcVya- X-Proofpoint-ORIG-GUID: xbT50irScEGomuey2tlkjLY57CfcVya- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-22_12,2023-05-22_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=831 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305220134 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Kewen, Segher, GCC maintainers: Version 3, fixed various issues noted by Kewen. Retested on Power 10. No regression issues. Version 2, Fixed an issue with the test case. The dg-options line was missing. The following patch adds an overloaded builtin. There are two possible arguments for the builtin. The builtin definitions are: double __builtin_mffscrn (unsigned long int); double __builtin_mffscrn (double); The patch has been tested on Power 10 with no regressions. Please let me know if the patch is acceptable for mainline. Thanks. Carl ------------------------------------------- rs6000: Add builtin for mffscrn instructions This patch adds overloaded __builtin_mffscrn for the move From FPSCR Control & Set RN instruction with an immediate argument. It also adds the builtin with a floating point register argument. A new runnable test is added for the new builtin. gcc/ * config/rs6000/rs6000-builtins.def (__builtin_mffscrni, __builtin_mffscrnd): Add builtin definitions. * config/rs6000/rs6000-overload.def (__builtin_mffscrn): Add overloaded definition. * doc/extend.texi: Add documentation for __builtin_mffscrn. gcc/testsuite/ * gcc.target/powerpc/builtin-mffscrn.c: Add testcase for new builtin. --- gcc/config/rs6000/rs6000-builtins.def | 9 +- gcc/config/rs6000/rs6000-overload.def | 5 + gcc/doc/extend.texi | 10 ++ .../gcc.target/powerpc/builtin-mffscrn.c | 106 ++++++++++++++++++ 4 files changed, 129 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 92d9b46e1b9..ae08d2fbff7 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -2849,6 +2849,14 @@ const signed int __builtin_vsx_scalar_extract_exp (double); VSEEDP xsxexpdp_si {} +; Immediate instruction only uses the least significant two bits of the +; const int. + double __builtin_mffscrni (const int<2>); + MFFSCRNI rs6000_mffscrni {nosoft} + + double __builtin_mffscrnd (double); + MFFSCRNF rs6000_mffscrn {nosoft} + [power9-64] void __builtin_altivec_xst_len_r (vsc, void *, long); XST_LEN_R xst_len_r {} @@ -2875,7 +2883,6 @@ pure vsc __builtin_vsx_xl_len_r (void *, signed long); XL_LEN_R xl_len_r {} - ; Builtins requiring hardware support for IEEE-128 floating-point. [ieee128-hw] fpmath _Float128 __builtin_addf128_round_to_odd (_Float128, _Float128); diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def index 26dc662b8fb..39423bcec2b 100644 --- a/gcc/config/rs6000/rs6000-overload.def +++ b/gcc/config/rs6000/rs6000-overload.def @@ -78,6 +78,11 @@ ; like after a required newline, but nowhere else. Lines beginning with ; a semicolon are also treated as blank lines. +[MFFSCR, __builtin_mffscrn, __builtin_mffscrn] + double __builtin_mffscrn (const int<2>); + MFFSCRNI + double __builtin_mffscrn (double); + MFFSCRNF [BCDADD, __builtin_bcdadd, __builtin_vec_bcdadd] vsq __builtin_vec_bcdadd (vsq, vsq, const int); diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index ed8b9c8a87b..82f9932666a 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -18274,6 +18274,16 @@ The @code{__builtin_recipdiv}, and @code{__builtin_recipdivf} functions generate multiple instructions to implement division using the reciprocal estimate instructions. +double __builtin_mffscrn (const int); +double __builtin_mffscrn (double); + +The @code{__builtin_mffscrn} returns the contents of the control bits DRN, VE, +OE, UE, ZE, XE, NI, RN in the FPSCR are returned with RN updated appropriately. +In the case of the const int variant of the builtin, RN is set to the 2-bit +value specified in the builtin. In the case of the double builtin variant, the +2-bit value in the double argument that corresponds to the RN location in the +FPSCR is updated. + The following functions require @option{-mhard-float} and @option{-mmultiple} options. diff --git a/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c b/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c new file mode 100644 index 00000000000..69a7a17cfc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c @@ -0,0 +1,106 @@ +/* { dg-do run } */ +/* { dg-require-effective-target p9modulo_hw } */ +/* { dg-options "-mdejagnu-cpu=power9" } */ + +#include + +#ifdef DEBUG +#include +#endif + +#define MASK 0x3 +#define EXPECTED1 0x1 +#define EXPECTED2 0x2 + +void abort (void); + +int +main() +{ + unsigned long mask, result, expected; + double double_arg; + + union convert_t { + double d; + unsigned long ul; + } val; + + /* Test immediate version of __builtin_mffscrn. */ + /* Read FPSCR and set RN bits in FPSCR[62:63]. */ + val.d = __builtin_mffscrn (EXPECTED2); + + /* Read FPSCR, bits [62:63] should have been set to 0x2 by previous builtin + call. */ + val.d = __builtin_mffscrn (EXPECTED1); + /* The expected result is the argument for the previous call to + __builtin_mffscrn. */ + expected = EXPECTED2; + result = MASK & val.ul; + + if (EXPECTED2 != result) +#ifdef DEBUG + printf("Result of mffscrn immediate doesn't match EXPECTED2. Result was 0x%lx\n", + result); +#else + abort(); +#endif + + /* Read FPSCR, bits [62:63] should have been set to 0x1 by previous builtin + call*/ + val.d = __builtin_mffscrn (EXPECTED1); + expected = EXPECTED1; + result = MASK & val.ul; + + if (EXPECTED1 != result) +#ifdef DEBUG + printf("Result of mffscrn immediate doesn't match EXPECTED1. Result was 0x%lx\n", + result); +#else + abort(); +#endif + + + /* Test double argument version of __builtin_mffscrn */ + val.ul = EXPECTED2; + double_arg = val.d; + + /* Read FPSCR and set RN bits in FPSCR[62:63]. */ + val.d = __builtin_mffscrn (double_arg); + + /* Read FPSCR, bits [62:63] should have been set to 0x2 by previous builtin + call. */ + + val.ul = EXPECTED1; + double_arg = val.d; + + val.d = __builtin_mffscrn (double_arg); + /* The expected result is the argument for the previous call to + __builtin_mffscrn. */ + expected = EXPECTED2; + result = MASK & val.ul; + + if (EXPECTED2 != result) +#ifdef DEBUG + printf("Result of mffscrn double arg doesn't match EXPECTED2. Result was 0x%lx\n", + result); +#else + abort(); +#endif + + /* Read FPSCR, bits [62:63] should have been set to 0x1 by previous builtin + call*/ + val.ul = EXPECTED1; + double_arg = val.d; + + val.d = __builtin_mffscrn (double_arg); + expected = EXPECTED1; + result = MASK & val.ul; + + if (EXPECTED1 != result) +#ifdef DEBUG + printf("Result of mffscrn double arg doesn't match EXPECTED1. Result was 0x%lx\n", + result); +#else + abort(); +#endif +} -- 2.37.2