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From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: richard.sandiford <richard.sandiford@arm.com>
Cc: rguenther <rguenther@suse.de>,
	 gcc-patches <gcc-patches@gcc.gnu.org>,
	 linkw <linkw@linux.ibm.com>
Subject: Re: Re: [PATCH V3] VECT: Change flow of decrement IV
Date: Tue, 6 Jun 2023 16:02:39 +0800	[thread overview]
Message-ID: <7C18CE8ABBD87C3F+2023060616023879734690@rivai.ai> (raw)
In-Reply-To: <mpt7csm3x91.fsf@arm.com>

[-- Attachment #1: Type: text/plain, Size: 830 bytes --]

Hi, Richard and Richi.
Recently, we have some tries on our downstream RVV LLVM.
We change "get_vector_length" (same IR like GCC "select_vl") into "umin", turns out LLVM SCEV analysis succeed.
The unroll PASS works in LLVM.

I think Richard's  suggestion is very reasonable.

I didn't have the time take a look at how LLVM do now but I will take a look at it in the future. 

Thanks.


juzhe.zhong@rivai.ai
 
From: Richard Sandiford
Date: 2023-06-02 19:43
To: juzhe.zhong\@rivai.ai
CC: rguenther; gcc-patches; linkw
Subject: Re: [PATCH V3] VECT: Change flow of decrement IV
"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai> writes:
> Thanks Richi. I am gonna merge it after Richard's final approve.
 
Thanks for checking, but no need to wait for a second ack from me!
Please go ahead and commit.
 
Richard
 

      parent reply	other threads:[~2023-06-06  8:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-01  4:36 juzhe.zhong
2023-06-01  5:00 ` juzhe.zhong
2023-06-01  5:24   ` Kewen.Lin
2023-06-01  8:09     ` juzhe.zhong
2023-06-02  8:56   ` Richard Biener
2023-06-02  8:58     ` juzhe.zhong
2023-06-02 11:43       ` Richard Sandiford
2023-06-02 11:50         ` Li, Pan2
2023-06-06  8:02         ` juzhe.zhong [this message]

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