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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Dell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DS7PR19MB4501.namprd19.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 874cdb64-5af0-421c-5f38-08daade0e30e X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2022 12:37:41.9683 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 945c199a-83a2-4e80-9f8c-5a91be5752dd X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: m5DUYY6t0W1sIMnss4jHRL/gt1nSfihNy3ZoYML3WLCILX4/Se+jPByDis9qYJ4d4d6kCq/yqAmGiMAsii4eyQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR19MB5702 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_06,2022-10-14_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 impostorscore=0 malwarescore=0 adultscore=0 suspectscore=0 priorityscore=1501 phishscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210140072 X-Proofpoint-GUID: BtwZuSUMV8it0V-RD4zpR3nX4YPUsFEp X-Proofpoint-ORIG-GUID: BtwZuSUMV8it0V-RD4zpR3nX4YPUsFEp X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 phishscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210140072 X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > On Oct 13, 2022, at 9:07 PM, Jeff Law via Gcc-patches wrote: >=20 >=20 > On 10/13/22 17:56, Segher Boessenkool wrote: >>=20 >> h8300 fails during GCC build: >> /home/segher/src/gcc/libgcc/unwind.inc: In function '_Unwind_SjLj_RaiseE= xception': >> /home/segher/src/gcc/libgcc/unwind.inc:141:1: error: could not split ins= n >> 141 | } >> | ^ >> (insn 69 256 327 (set (mem/f:SI (pre_dec:SI (reg/f:SI 7 sp)) [12 S4 A32= ]) >> (reg/f:SI 7 sp)) "/home/segher/src/gcc/libgcc/unwind.inc":118:12= 19 {*movsi} >> (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) >> (nil))) >> during RTL pass: final >> which looks like a backend bug, I don't see a pattern that could split >> this (without needing an extra clobber)? >=20 > I'm aware of this -- its invalid RTL: >=20 > Uses of the register outside of an address are not permitted within the > same insn as a use in an embedded side effect expression because such > insns behave differently on different machines and hence must be treated > as ambiguous and disallowed. I had a bit of a fight with this sort of thing in pdp11, where in fact such= operations are executed differently on different machine models. The solu= tion I picked is to create two sets of machine-specific constraint codes, o= ne for "register N" and the other for "autoinc/dec of any register other th= an N" and pairing those. (You can see this in pdp11.md, the mov defi= nition.) But the pdp11 case is actually not as restrictive as the rule you mentioned= . The problem case is register N source, autoinc/dec rN destination. The = opposite case, which we see here -- autoinc/dec Rn source, Rn destination -= - is just fine. Perhaps not all that important, but the ISA definition doe= s not object to it. So I'm not sure why there would be a general rule that= says it's considered ambiguous when the target machine architecture says i= t is not. paul