* [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series
@ 2021-04-26 20:21 acsawdey
2021-04-26 20:21 ` [PATCH,rs6000 1/2] combine patterns for add-add fusion acsawdey
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: acsawdey @ 2021-04-26 20:21 UTC (permalink / raw)
To: gcc-patches; +Cc: segher, wschmidt, will_schmidt, Aaron Sawdey
From: Aaron Sawdey <acsawdey@linux.ibm.com>
Two more sets of combine patterns for p10 fusion. These require
the "Add insn types for fusion pairs" patch I posted earlier today.
If ok I would like to put these in gcc 12 trunk and backport for 11.2.
Thanks,
Aaron
Aaron Sawdey (2):
combine patterns for add-add fusion
Fusion patterns for add-logical/logical-add
gcc/config/rs6000/fusion.md | 908 +++++++++++++-----
gcc/config/rs6000/genfusion.pl | 127 ++-
gcc/config/rs6000/rs6000-cpus.def | 8 +-
gcc/config/rs6000/rs6000.c | 9 +
gcc/config/rs6000/rs6000.opt | 12 +
.../gcc.target/powerpc/fusion-p10-addadd.c | 41 +
.../gcc.target/powerpc/fusion-p10-logadd.c | 98 ++
7 files changed, 925 insertions(+), 278 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/fusion-p10-addadd.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c
--
2.27.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH,rs6000 1/2] combine patterns for add-add fusion 2021-04-26 20:21 [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series acsawdey @ 2021-04-26 20:21 ` acsawdey 2021-05-19 21:29 ` Segher Boessenkool 2021-04-26 20:21 ` [PATCH,rs6000 2/2] Fusion patterns for add-logical/logical-add acsawdey 2021-05-11 13:50 ` [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series Aaron Sawdey 2 siblings, 1 reply; 7+ messages in thread From: acsawdey @ 2021-04-26 20:21 UTC (permalink / raw) To: gcc-patches; +Cc: segher, wschmidt, will_schmidt, Aaron Sawdey From: Aaron Sawdey <acsawdey@linux.ibm.com> This patch adds a function to genfusion.pl to add a couple more patterns so combine can do fusion of pairs of add and vaddudm instructions. gcc/ChangeLog: * gcc/config/rs6000/genfusion.pl (gen_addadd): New function. * gcc/config/rs6000/fusion.md: Regenerate file. * gcc/config/rs6000/rs6000-cpus.def: Add OPTION_MASK_P10_FUSION_2ADD to masks. * gcc/config/rs6000/rs6000.c (rs6000_option_override_internal): Handle default value of OPTION_MASK_P10_FUSION_2ADD. * gcc/config/rs6000/rs6000.opt: Add -mpower10-fusion-2add. gcc/testsuite/ChangeLog: * gcc.target/powerpc/fusion-p10-addadd.c: New file. --- gcc/config/rs6000/fusion.md | 36 +++++++++++++++ gcc/config/rs6000/genfusion.pl | 44 +++++++++++++++++++ gcc/config/rs6000/rs6000-cpus.def | 4 +- gcc/config/rs6000/rs6000.c | 3 ++ gcc/config/rs6000/rs6000.opt | 4 ++ .../gcc.target/powerpc/fusion-p10-addadd.c | 41 +++++++++++++++++ 6 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/fusion-p10-addadd.c diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 6d71bc2df73..6dfe1fa4508 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -2658,3 +2658,39 @@ (define_insn "*fuse_vxor_vxor" [(set_attr "type" "fused_vector") (set_attr "cost" "6") (set_attr "length" "8")]) + +;; add-add fusion pattern generated by gen_addadd +(define_insn "*fuse_add_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR + (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2ADD)" + "@ + add %3,%1,%0\;add %3,%3,%2 + add %3,%1,%0\;add %3,%3,%2 + add %3,%1,%0\;add %3,%3,%2 + add %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fuse_arithlog") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; vaddudm-vaddudm fusion pattern generated by gen_addadd +(define_insn "*fuse_vaddudm_vaddudm" + [(set (match_operand:V2DI 3 "altivec_register_operand" "=0,1,&v,v") + (plus:V2DI + (plus:V2DI (match_operand:V2DI 0 "altivec_register_operand" "v,v,v,v") + (match_operand:V2DI 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:V2DI 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:V2DI 4 "=X,X,X,&v"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2ADD)" + "@ + vaddudm %3,%1,%0\;vaddudm %3,%3,%2 + vaddudm %3,%1,%0\;vaddudm %3,%3,%2 + vaddudm %3,%1,%0\;vaddudm %3,%3,%2 + vaddudm %4,%1,%0\;vaddudm %3,%4,%2" + [(set_attr "type" "fuse_vec") + (set_attr "cost" "6") + (set_attr "length" "8")]) diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index ce48fd94f95..8ed3c3617ec 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -240,8 +240,52 @@ EOF } } +sub gen_addadd +{ + my ($kind, $vchr, $op, $ty, $mode, $pred, $constraint); + KIND: foreach $kind ('scalar','vector') { + if ( $kind eq 'vector' ) { + $vchr = "v"; + $op = "vaddudm"; + $ty = "fuse_vec"; + $mode = "V2DI"; + $pred = "altivec_register_operand"; + $constraint = "v"; + } else { + $vchr = ""; + $op = "add"; + $ty = "fuse_arithlog"; + $mode = "GPR"; + $pred = "gpc_reg_operand"; + $constraint = "r"; + } + my $c4 = "${constraint},${constraint},${constraint},${constraint}"; + print <<"EOF"; + +;; ${op}-${op} fusion pattern generated by gen_addadd +(define_insn "*fuse_${op}_${op}" + [(set (match_operand:${mode} 3 "${pred}" "=0,1,&${constraint},${constraint}") + (plus:${mode} + (plus:${mode} (match_operand:${mode} 0 "${pred}" "${c4}") + (match_operand:${mode} 1 "${pred}" "%${c4}")) + (match_operand:${mode} 2 "${pred}" "${c4}"))) + (clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint}"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2ADD)" + "@ + ${op} %3,%1,%0\\;${op} %3,%3,%2 + ${op} %3,%1,%0\\;${op} %3,%3,%2 + ${op} %3,%1,%0\\;${op} %3,%3,%2 + ${op} %4,%1,%0\\;${op} %3,%4,%2" + [(set_attr "type" "${ty}") + (set_attr "cost" "6") + (set_attr "length" "8")]) +EOF + } +} + gen_ld_cmpi_p10(); gen_2logical(); +gen_addadd(); exit(0); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index cbbb42c1b3a..d46a91dd11b 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -85,7 +85,8 @@ | OTHER_POWER10_MASKS \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_P10_FUSION_LD_CMPI \ - | OPTION_MASK_P10_FUSION_2LOGICAL) + | OPTION_MASK_P10_FUSION_2LOGICAL \ + | OPTION_MASK_P10_FUSION_2ADD) /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ @@ -135,6 +136,7 @@ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_P10_FUSION_LD_CMPI \ | OPTION_MASK_P10_FUSION_2LOGICAL \ + | OPTION_MASK_P10_FUSION_2ADD \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 844fee88cf3..9488a54a1d7 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4467,6 +4467,9 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL; + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD; + /* Turn off vector pair/mma options on non-power10 systems. */ else if (!TARGET_POWER10 && TARGET_MMA) { diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 0dbdf753673..fc14325ed33 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -502,6 +502,10 @@ mpower10-fusion-2logical Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags) Fuse certain integer operations together for better performance on power10. +mpower10-fusion-2add +Target Undocumented Mask(P10_FUSION_2ADD) Var(rs6000_isa_flags) +Fuse certain add operations together for better performance on power10. + mcrypto Target Mask(CRYPTO) Var(rs6000_isa_flags) Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-addadd.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-addadd.c new file mode 100644 index 00000000000..41d71dbf3cb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-addadd.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-options "-mdejagnu-cpu=power10 -O3 -dp" } */ + +long addadd0(long a, long b, long c) +{ + return a+b+c; +} +long addadd1(long a, long b, long c, long *t) +{ + long r=a+b+c; + *t = b; + return r; +} +long addadd2(long s, long a, long b, long c) +{ + return b+c+a; +} + +typedef vector long vlong; +vlong vaddadd(vlong a, vlong b, vlong c) +{ + return a+b+c; +} +vlong vaddadd1(vlong a, vlong b, vlong c, vlong *t) +{ + vlong r=a+b+c; + *t = b; + return r; +} +vlong vaddadd2(vlong s, vlong a, vlong b, vlong c) +{ + return a+b+c; +} + +/* { dg-final { scan-assembler-times "fuse_add_add/0" 1 } } */ +/* { dg-final { scan-assembler-times "fuse_add_add/1" 1 } } */ +/* { dg-final { scan-assembler-times "fuse_add_add/2" 1 } } */ +/* { dg-final { scan-assembler-times "fuse_vaddudm_vaddudm/0" 1 } } */ +/* { dg-final { scan-assembler-times "fuse_vaddudm_vaddudm/1" 1 } } */ +/* { dg-final { scan-assembler-times "fuse_vaddudm_vaddudm/2" 1 } } */ -- 2.27.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH,rs6000 1/2] combine patterns for add-add fusion 2021-04-26 20:21 ` [PATCH,rs6000 1/2] combine patterns for add-add fusion acsawdey @ 2021-05-19 21:29 ` Segher Boessenkool 0 siblings, 0 replies; 7+ messages in thread From: Segher Boessenkool @ 2021-05-19 21:29 UTC (permalink / raw) To: acsawdey; +Cc: gcc-patches, wschmidt, will_schmidt On Mon, Apr 26, 2021 at 03:21:29PM -0500, acsawdey@linux.ibm.com wrote: > This patch adds a function to genfusion.pl to add a couple > more patterns so combine can do fusion of pairs of add and > vaddudm instructions. > +sub gen_addadd > +{ > + my ($kind, $vchr, $op, $ty, $mode, $pred, $constraint); Does spelling out $type conflict with anything? :-) > + KIND: foreach $kind ('scalar','vector') { Why put a label on this? It isn't used. > --- a/gcc/config/rs6000/rs6000.c > +++ b/gcc/config/rs6000/rs6000.c > @@ -4467,6 +4467,9 @@ rs6000_option_override_internal (bool global_init_p) > if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0) > rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL; > > + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0) Line too long. Just break before the &&? > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-addadd.c > @@ -0,0 +1,41 @@ > +/* { dg-do compile { target { powerpc*-*-* } } } */ Just omit the target, anything in gcc.target/powerpc/ is run only for powerpc already. You can also omit the dg-do coompletely, "compile" is the default, but it can be nice documentation. > +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ Do we know it does not work on darwin? If not, please don't disable it there -- if we do that unnecessarily all the time, much tooo little is tested on darwin. Okay for trunk, and a backport to 11 later. Thanks! And the previous patch is fine for backport as well of course. Segher ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH,rs6000 2/2] Fusion patterns for add-logical/logical-add 2021-04-26 20:21 [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series acsawdey 2021-04-26 20:21 ` [PATCH,rs6000 1/2] combine patterns for add-add fusion acsawdey @ 2021-04-26 20:21 ` acsawdey 2021-05-19 22:15 ` Segher Boessenkool 2021-05-11 13:50 ` [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series Aaron Sawdey 2 siblings, 1 reply; 7+ messages in thread From: acsawdey @ 2021-04-26 20:21 UTC (permalink / raw) To: gcc-patches; +Cc: segher, wschmidt, will_schmidt, Aaron Sawdey From: Aaron Sawdey <acsawdey@linux.ibm.com> This patch modifies the function in genfusion.pl for generating the logical-logical patterns so that it can also generate the add-logical and logical-add patterns which are very similar. gcc/ChangeLog: * config/rs6000/genfusion.pl (gen_logical_addsubf): Refactor to add generation of logical-add and add-logical fusion pairs. * config/rs6000/rs6000-cpus.def: Add new fusion to ISA 3.1 mask and powerpc mask. * config/rs6000/rs6000.c (rs6000_option_override_internal): Turn on logical-add and add-logical fusion by default. * config/rs6000.opt: Add -mpower10-fusion-logical-add and -mpower10-fusion-add-logical options. * config/rs6000/fusion.md: Regenerate file. gcc/testsuite/ChangeLog: * gcc.target/powerpc/fusion-p10-logadd.c: New file. --- gcc/config/rs6000/fusion.md | 876 ++++++++++++------ gcc/config/rs6000/genfusion.pl | 87 +- gcc/config/rs6000/rs6000-cpus.def | 4 + gcc/config/rs6000/rs6000.c | 6 + gcc/config/rs6000/rs6000.opt | 8 + .../gcc.target/powerpc/fusion-p10-logadd.c | 98 ++ 6 files changed, 798 insertions(+), 281 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 6dfe1fa4508..6c7c94c44c1 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -355,11 +355,11 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero" (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> and (define_insn "*fuse_and_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -373,11 +373,11 @@ (define_insn "*fuse_and_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> and (define_insn "*fuse_andc_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -391,11 +391,11 @@ (define_insn "*fuse_andc_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> and (define_insn "*fuse_eqv_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -409,11 +409,11 @@ (define_insn "*fuse_eqv_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> and (define_insn "*fuse_nand_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -427,11 +427,11 @@ (define_insn "*fuse_nand_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> and (define_insn "*fuse_nor_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -445,11 +445,11 @@ (define_insn "*fuse_nor_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> and (define_insn "*fuse_or_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -463,11 +463,11 @@ (define_insn "*fuse_or_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> and (define_insn "*fuse_orc_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -481,11 +481,11 @@ (define_insn "*fuse_orc_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> and (define_insn "*fuse_xor_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -499,11 +499,47 @@ (define_insn "*fuse_xor_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> and +(define_insn "*fuse_add_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;and %3,%3,%2 + add %3,%1,%0\;and %3,%3,%2 + add %3,%1,%0\;and %3,%3,%2 + add %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> and +(define_insn "*fuse_subf_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;and %3,%3,%2 + subf %3,%1,%0\;and %3,%3,%2 + subf %3,%1,%0\;and %3,%3,%2 + subf %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> andc (define_insn "*fuse_and_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -517,11 +553,11 @@ (define_insn "*fuse_and_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> andc (define_insn "*fuse_andc_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -535,11 +571,11 @@ (define_insn "*fuse_andc_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> andc (define_insn "*fuse_eqv_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -553,11 +589,11 @@ (define_insn "*fuse_eqv_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> andc (define_insn "*fuse_nand_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -571,11 +607,11 @@ (define_insn "*fuse_nand_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> andc (define_insn "*fuse_nor_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -589,11 +625,11 @@ (define_insn "*fuse_nor_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> andc (define_insn "*fuse_or_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -607,11 +643,11 @@ (define_insn "*fuse_or_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> andc (define_insn "*fuse_orc_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -625,11 +661,11 @@ (define_insn "*fuse_orc_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> andc (define_insn "*fuse_xor_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -643,11 +679,11 @@ (define_insn "*fuse_xor_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> eqv (define_insn "*fuse_and_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -661,11 +697,11 @@ (define_insn "*fuse_and_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> eqv (define_insn "*fuse_andc_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -679,11 +715,11 @@ (define_insn "*fuse_andc_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> eqv (define_insn "*fuse_eqv_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -697,11 +733,11 @@ (define_insn "*fuse_eqv_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> eqv (define_insn "*fuse_nand_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -715,11 +751,11 @@ (define_insn "*fuse_nand_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> eqv (define_insn "*fuse_nor_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -733,11 +769,11 @@ (define_insn "*fuse_nor_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> eqv (define_insn "*fuse_or_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -751,11 +787,11 @@ (define_insn "*fuse_or_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> eqv (define_insn "*fuse_orc_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -769,11 +805,11 @@ (define_insn "*fuse_orc_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> eqv (define_insn "*fuse_xor_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -787,11 +823,11 @@ (define_insn "*fuse_xor_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> nand (define_insn "*fuse_and_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -805,11 +841,11 @@ (define_insn "*fuse_and_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> nand (define_insn "*fuse_andc_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -823,11 +859,11 @@ (define_insn "*fuse_andc_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> nand (define_insn "*fuse_eqv_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -841,11 +877,11 @@ (define_insn "*fuse_eqv_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> nand (define_insn "*fuse_nand_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -859,11 +895,11 @@ (define_insn "*fuse_nand_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> nand (define_insn "*fuse_nor_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -877,11 +913,11 @@ (define_insn "*fuse_nor_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> nand (define_insn "*fuse_or_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -895,11 +931,11 @@ (define_insn "*fuse_or_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> nand (define_insn "*fuse_orc_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -913,11 +949,11 @@ (define_insn "*fuse_orc_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> nand (define_insn "*fuse_xor_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -931,11 +967,47 @@ (define_insn "*fuse_xor_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> nand +(define_insn "*fuse_add_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;nand %3,%3,%2 + add %3,%1,%0\;nand %3,%3,%2 + add %3,%1,%0\;nand %3,%3,%2 + add %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> nand +(define_insn "*fuse_subf_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;nand %3,%3,%2 + subf %3,%1,%0\;nand %3,%3,%2 + subf %3,%1,%0\;nand %3,%3,%2 + subf %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> nor (define_insn "*fuse_and_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -949,11 +1021,11 @@ (define_insn "*fuse_and_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> nor (define_insn "*fuse_andc_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -967,11 +1039,11 @@ (define_insn "*fuse_andc_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> nor (define_insn "*fuse_eqv_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -985,11 +1057,11 @@ (define_insn "*fuse_eqv_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> nor (define_insn "*fuse_nand_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1003,11 +1075,11 @@ (define_insn "*fuse_nand_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> nor (define_insn "*fuse_nor_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1021,11 +1093,11 @@ (define_insn "*fuse_nor_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> nor (define_insn "*fuse_or_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1039,11 +1111,11 @@ (define_insn "*fuse_or_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> nor (define_insn "*fuse_orc_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1057,11 +1129,11 @@ (define_insn "*fuse_orc_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> nor (define_insn "*fuse_xor_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1075,11 +1147,47 @@ (define_insn "*fuse_xor_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> nor +(define_insn "*fuse_add_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;nor %3,%3,%2 + add %3,%1,%0\;nor %3,%3,%2 + add %3,%1,%0\;nor %3,%3,%2 + add %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> nor +(define_insn "*fuse_subf_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;nor %3,%3,%2 + subf %3,%1,%0\;nor %3,%3,%2 + subf %3,%1,%0\;nor %3,%3,%2 + subf %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> or (define_insn "*fuse_and_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1093,11 +1201,11 @@ (define_insn "*fuse_and_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> or (define_insn "*fuse_andc_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1111,11 +1219,11 @@ (define_insn "*fuse_andc_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> or (define_insn "*fuse_eqv_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1129,11 +1237,11 @@ (define_insn "*fuse_eqv_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> or (define_insn "*fuse_nand_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1147,11 +1255,11 @@ (define_insn "*fuse_nand_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> or (define_insn "*fuse_nor_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1165,11 +1273,11 @@ (define_insn "*fuse_nor_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> or (define_insn "*fuse_or_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1183,11 +1291,11 @@ (define_insn "*fuse_or_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> or (define_insn "*fuse_orc_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1201,11 +1309,11 @@ (define_insn "*fuse_orc_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> or (define_insn "*fuse_xor_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1219,11 +1327,47 @@ (define_insn "*fuse_xor_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> or +(define_insn "*fuse_add_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;or %3,%3,%2 + add %3,%1,%0\;or %3,%3,%2 + add %3,%1,%0\;or %3,%3,%2 + add %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> or +(define_insn "*fuse_subf_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;or %3,%3,%2 + subf %3,%1,%0\;or %3,%3,%2 + subf %3,%1,%0\;or %3,%3,%2 + subf %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> orc (define_insn "*fuse_and_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1237,11 +1381,11 @@ (define_insn "*fuse_and_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> orc (define_insn "*fuse_andc_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1255,11 +1399,11 @@ (define_insn "*fuse_andc_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> orc (define_insn "*fuse_eqv_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1273,11 +1417,11 @@ (define_insn "*fuse_eqv_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> orc (define_insn "*fuse_nand_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1291,11 +1435,11 @@ (define_insn "*fuse_nand_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> orc (define_insn "*fuse_nor_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1309,11 +1453,11 @@ (define_insn "*fuse_nor_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> orc (define_insn "*fuse_or_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1327,11 +1471,11 @@ (define_insn "*fuse_or_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> orc (define_insn "*fuse_orc_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1345,11 +1489,11 @@ (define_insn "*fuse_orc_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> orc (define_insn "*fuse_xor_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1363,11 +1507,11 @@ (define_insn "*fuse_xor_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> xor (define_insn "*fuse_and_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1381,11 +1525,11 @@ (define_insn "*fuse_and_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> xor (define_insn "*fuse_andc_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1399,11 +1543,11 @@ (define_insn "*fuse_andc_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> xor (define_insn "*fuse_eqv_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1417,11 +1561,11 @@ (define_insn "*fuse_eqv_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> xor (define_insn "*fuse_nand_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1435,11 +1579,11 @@ (define_insn "*fuse_nand_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> xor (define_insn "*fuse_nor_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1453,11 +1597,11 @@ (define_insn "*fuse_nor_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> xor (define_insn "*fuse_or_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1471,11 +1615,11 @@ (define_insn "*fuse_or_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> xor (define_insn "*fuse_orc_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1489,11 +1633,11 @@ (define_insn "*fuse_orc_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> xor (define_insn "*fuse_xor_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1507,11 +1651,227 @@ (define_insn "*fuse_xor_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nor -> add +(define_insn "*fuse_nor_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nor %3,%1,%0\;add %3,%3,%2 + nor %3,%1,%0\;add %3,%3,%2 + nor %3,%1,%0\;add %3,%3,%2 + nor %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nand -> add +(define_insn "*fuse_nand_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nand %3,%1,%0\;add %3,%3,%2 + nand %3,%1,%0\;add %3,%3,%2 + nand %3,%1,%0\;add %3,%3,%2 + nand %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar or -> add +(define_insn "*fuse_or_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + or %3,%1,%0\;add %3,%3,%2 + or %3,%1,%0\;add %3,%3,%2 + or %3,%1,%0\;add %3,%3,%2 + or %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar and -> add +(define_insn "*fuse_and_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + and %3,%1,%0\;add %3,%3,%2 + and %3,%1,%0\;add %3,%3,%2 + and %3,%1,%0\;add %3,%3,%2 + and %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nor -> subf +(define_insn "*fuse_nor_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nor %3,%1,%0\;subf %3,%3,%2 + nor %3,%1,%0\;subf %3,%3,%2 + nor %3,%1,%0\;subf %3,%3,%2 + nor %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nand -> subf +(define_insn "*fuse_nand_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nand %3,%1,%0\;subf %3,%3,%2 + nand %3,%1,%0\;subf %3,%3,%2 + nand %3,%1,%0\;subf %3,%3,%2 + nand %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar or -> subf +(define_insn "*fuse_or_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + or %3,%1,%0\;subf %3,%3,%2 + or %3,%1,%0\;subf %3,%3,%2 + or %3,%1,%0\;subf %3,%3,%2 + or %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar and -> subf +(define_insn "*fuse_and_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + and %3,%1,%0\;subf %3,%3,%2 + and %3,%1,%0\;subf %3,%3,%2 + and %3,%1,%0\;subf %3,%3,%2 + and %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nor -> rsubf +(define_insn "*fuse_nor_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nor %3,%1,%0\;subf %3,%2,%3 + nor %3,%1,%0\;subf %3,%2,%3 + nor %3,%1,%0\;subf %3,%2,%3 + nor %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nand -> rsubf +(define_insn "*fuse_nand_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nand %3,%1,%0\;subf %3,%2,%3 + nand %3,%1,%0\;subf %3,%2,%3 + nand %3,%1,%0\;subf %3,%2,%3 + nand %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar or -> rsubf +(define_insn "*fuse_or_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + or %3,%1,%0\;subf %3,%2,%3 + or %3,%1,%0\;subf %3,%2,%3 + or %3,%1,%0\;subf %3,%2,%3 + or %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar and -> rsubf +(define_insn "*fuse_and_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + and %3,%1,%0\;subf %3,%2,%3 + and %3,%1,%0\;subf %3,%2,%3 + and %3,%1,%0\;subf %3,%2,%3 + and %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vand (define_insn "*fuse_vand_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1525,11 +1885,11 @@ (define_insn "*fuse_vand_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vand (define_insn "*fuse_vandc_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1543,11 +1903,11 @@ (define_insn "*fuse_vandc_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vand (define_insn "*fuse_veqv_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1561,11 +1921,11 @@ (define_insn "*fuse_veqv_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vand (define_insn "*fuse_vnand_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1579,11 +1939,11 @@ (define_insn "*fuse_vnand_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vand (define_insn "*fuse_vnor_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1597,11 +1957,11 @@ (define_insn "*fuse_vnor_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vand (define_insn "*fuse_vor_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1615,11 +1975,11 @@ (define_insn "*fuse_vor_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vand (define_insn "*fuse_vorc_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1633,11 +1993,11 @@ (define_insn "*fuse_vorc_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vand (define_insn "*fuse_vxor_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1651,11 +2011,11 @@ (define_insn "*fuse_vxor_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vandc (define_insn "*fuse_vand_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1669,11 +2029,11 @@ (define_insn "*fuse_vand_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vandc (define_insn "*fuse_vandc_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1687,11 +2047,11 @@ (define_insn "*fuse_vandc_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vandc (define_insn "*fuse_veqv_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1705,11 +2065,11 @@ (define_insn "*fuse_veqv_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vandc (define_insn "*fuse_vnand_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1723,11 +2083,11 @@ (define_insn "*fuse_vnand_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vandc (define_insn "*fuse_vnor_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1741,11 +2101,11 @@ (define_insn "*fuse_vnor_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vandc (define_insn "*fuse_vor_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1759,11 +2119,11 @@ (define_insn "*fuse_vor_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vandc (define_insn "*fuse_vorc_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1777,11 +2137,11 @@ (define_insn "*fuse_vorc_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vandc (define_insn "*fuse_vxor_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1795,11 +2155,11 @@ (define_insn "*fuse_vxor_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> veqv (define_insn "*fuse_vand_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1813,11 +2173,11 @@ (define_insn "*fuse_vand_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> veqv (define_insn "*fuse_vandc_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1831,11 +2191,11 @@ (define_insn "*fuse_vandc_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> veqv (define_insn "*fuse_veqv_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1849,11 +2209,11 @@ (define_insn "*fuse_veqv_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> veqv (define_insn "*fuse_vnand_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1867,11 +2227,11 @@ (define_insn "*fuse_vnand_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> veqv (define_insn "*fuse_vnor_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1885,11 +2245,11 @@ (define_insn "*fuse_vnor_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> veqv (define_insn "*fuse_vor_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1903,11 +2263,11 @@ (define_insn "*fuse_vor_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> veqv (define_insn "*fuse_vorc_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1921,11 +2281,11 @@ (define_insn "*fuse_vorc_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> veqv (define_insn "*fuse_vxor_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1939,11 +2299,11 @@ (define_insn "*fuse_vxor_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnand (define_insn "*fuse_vand_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1957,11 +2317,11 @@ (define_insn "*fuse_vand_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnand (define_insn "*fuse_vandc_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1975,11 +2335,11 @@ (define_insn "*fuse_vandc_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnand (define_insn "*fuse_veqv_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1993,11 +2353,11 @@ (define_insn "*fuse_veqv_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnand (define_insn "*fuse_vnand_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2011,11 +2371,11 @@ (define_insn "*fuse_vnand_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnand (define_insn "*fuse_vnor_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2029,11 +2389,11 @@ (define_insn "*fuse_vnor_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnand (define_insn "*fuse_vor_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2047,11 +2407,11 @@ (define_insn "*fuse_vor_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnand (define_insn "*fuse_vorc_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2065,11 +2425,11 @@ (define_insn "*fuse_vorc_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnand (define_insn "*fuse_vxor_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2083,11 +2443,11 @@ (define_insn "*fuse_vxor_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnor (define_insn "*fuse_vand_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2101,11 +2461,11 @@ (define_insn "*fuse_vand_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnor (define_insn "*fuse_vandc_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2119,11 +2479,11 @@ (define_insn "*fuse_vandc_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnor (define_insn "*fuse_veqv_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2137,11 +2497,11 @@ (define_insn "*fuse_veqv_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnor (define_insn "*fuse_vnand_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2155,11 +2515,11 @@ (define_insn "*fuse_vnand_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnor (define_insn "*fuse_vnor_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2173,11 +2533,11 @@ (define_insn "*fuse_vnor_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnor (define_insn "*fuse_vor_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2191,11 +2551,11 @@ (define_insn "*fuse_vor_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnor (define_insn "*fuse_vorc_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2209,11 +2569,11 @@ (define_insn "*fuse_vorc_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnor (define_insn "*fuse_vxor_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2227,11 +2587,11 @@ (define_insn "*fuse_vxor_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vor (define_insn "*fuse_vand_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2245,11 +2605,11 @@ (define_insn "*fuse_vand_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vor (define_insn "*fuse_vandc_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2263,11 +2623,11 @@ (define_insn "*fuse_vandc_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vor (define_insn "*fuse_veqv_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2281,11 +2641,11 @@ (define_insn "*fuse_veqv_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vor (define_insn "*fuse_vnand_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2299,11 +2659,11 @@ (define_insn "*fuse_vnand_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vor (define_insn "*fuse_vnor_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2317,11 +2677,11 @@ (define_insn "*fuse_vnor_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vor (define_insn "*fuse_vor_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2335,11 +2695,11 @@ (define_insn "*fuse_vor_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vor (define_insn "*fuse_vorc_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2353,11 +2713,11 @@ (define_insn "*fuse_vorc_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vor (define_insn "*fuse_vxor_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2371,11 +2731,11 @@ (define_insn "*fuse_vxor_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vorc (define_insn "*fuse_vand_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2389,11 +2749,11 @@ (define_insn "*fuse_vand_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vorc (define_insn "*fuse_vandc_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2407,11 +2767,11 @@ (define_insn "*fuse_vandc_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vorc (define_insn "*fuse_veqv_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2425,11 +2785,11 @@ (define_insn "*fuse_veqv_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vorc (define_insn "*fuse_vnand_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2443,11 +2803,11 @@ (define_insn "*fuse_vnand_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vorc (define_insn "*fuse_vnor_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2461,11 +2821,11 @@ (define_insn "*fuse_vnor_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vorc (define_insn "*fuse_vor_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2479,11 +2839,11 @@ (define_insn "*fuse_vor_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vorc (define_insn "*fuse_vorc_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2497,11 +2857,11 @@ (define_insn "*fuse_vorc_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vorc (define_insn "*fuse_vxor_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2515,11 +2875,11 @@ (define_insn "*fuse_vxor_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vxor (define_insn "*fuse_vand_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2533,11 +2893,11 @@ (define_insn "*fuse_vand_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vxor (define_insn "*fuse_vandc_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2551,11 +2911,11 @@ (define_insn "*fuse_vandc_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vxor (define_insn "*fuse_veqv_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2569,11 +2929,11 @@ (define_insn "*fuse_veqv_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vxor (define_insn "*fuse_vnand_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2587,11 +2947,11 @@ (define_insn "*fuse_vnand_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vxor (define_insn "*fuse_vnor_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2605,11 +2965,11 @@ (define_insn "*fuse_vnor_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vxor (define_insn "*fuse_vor_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2623,11 +2983,11 @@ (define_insn "*fuse_vor_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vxor (define_insn "*fuse_vorc_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2641,11 +3001,11 @@ (define_insn "*fuse_vorc_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vxor (define_insn "*fuse_vxor_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2673,7 +3033,7 @@ (define_insn "*fuse_add_add" add %3,%1,%0\;add %3,%3,%2 add %3,%1,%0\;add %3,%3,%2 add %4,%1,%0\;add %3,%4,%2" - [(set_attr "type" "fuse_arithlog") + [(set_attr "type" "fused_arith_logical") (set_attr "cost" "6") (set_attr "length" "8")]) @@ -2691,6 +3051,6 @@ (define_insn "*fuse_vaddudm_vaddudm" vaddudm %3,%1,%0\;vaddudm %3,%3,%2 vaddudm %3,%1,%0\;vaddudm %3,%3,%2 vaddudm %4,%1,%0\;vaddudm %3,%4,%2" - [(set_attr "type" "fuse_vec") + [(set_attr "type" "fused_vector") (set_attr "cost" "6") (set_attr "length" "8")]) diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 8ed3c3617ec..7768d434bd2 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -144,23 +144,32 @@ sub gen_ld_cmpi_p10 } } -sub gen_2logical +sub gen_logical_addsubf { my @logicals = ( "and", "andc", "eqv", "nand", "nor", "or", "orc", "xor" ); + my %logicals_addsub = ( "and"=>1, "nand"=>1, "nor"=>1, "or"=>1 ); + my @addsub = ( "add", "subf" ); + my %isaddsub = ( "add"=>1, "subf"=>1 ); my %complement = ( "and"=> 0, "andc"=> 1, "eqv"=> 0, "nand"=> 3, - "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0 ); + "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0, + "add"=> 0, "subf"=> 0 ); my %invert = ( "and"=> 0, "andc"=> 0, "eqv"=> 1, "nand"=> 0, - "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0 ); + "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0, + "add"=> 0, "subf"=> 0 ); my %commute2 = ( "and"=> 1, "andc"=> 0, "eqv"=> 1, "nand"=> 0, "nor"=> 0, "or"=> 1, "orc"=> 0, "xor"=> 1 ); my %rtlop = ( "and"=>"and", "andc"=>"and", "eqv"=>"xor", "nand"=>"ior", - "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor" ); + "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor", + "add"=>"plus", "subf"=>"minus" ); - my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, $outer_op, - $outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp, $inner_inv, - $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, - $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn, $fuse_type); + my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, @outer_ops, + $outer_op, $outer_comp, $outer_inv, $outer_rtl, $inner, @inner_ops, + $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4, + $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, + $target_flag, $ftype, $insn, $is_rsubf, $outer_32, $outer_42, + $outer_name, $fuse_type); KIND: foreach $kind ('scalar','vector') { + @outer_ops = @logicals; if ( $kind eq 'vector' ) { $vchr = "v"; $mode = "VM"; @@ -173,14 +182,37 @@ sub gen_2logical $pred = "gpc_reg_operand"; $constraint = "r"; $fuse_type = "fused_arith_logical"; + push (@outer_ops, @addsub); + push (@outer_ops, ( "rsubf" )); } $c4 = "${constraint},${constraint},${constraint},${constraint}"; - OUTER: foreach $outer ( @logicals ) { + OUTER: foreach $outer ( @outer_ops ) { + $outer_name = "${vchr}${outer}"; + if ( $outer eq "rsubf" ) { + $is_rsubf = 1; + $outer = "subf"; + } else { + $is_rsubf = 0; + } $outer_op = "${vchr}${outer}"; $outer_comp = $complement{$outer}; $outer_inv = $invert{$outer}; $outer_rtl = $rtlop{$outer}; - INNER: foreach $inner ( @logicals ) { + @inner_ops = @logicals; + $ftype = "logical-logical"; + $target_flag = "TARGET_P10_FUSION_2LOGICAL"; + if ( exists $isaddsub{$outer} ) { + @inner_ops = keys %logicals_addsub; + $ftype = "logical-add"; + $target_flag = "TARGET_P10_FUSION_LOGADD"; + } elsif ( $kind ne 'vector' && exists $logicals_addsub{$outer} ) { + push (@inner_ops, @addsub); + } + INNER: foreach $inner ( @inner_ops ) { + if ( exists $isaddsub{$inner} ) { + $ftype = "add-logical"; + $target_flag = "TARGET_P10_FUSION_ADDLOG"; + } $inner_comp = $complement{$inner}; $inner_inv = $invert{$inner}; $inner_rtl = $rtlop{$inner}; @@ -197,7 +229,7 @@ sub gen_2logical if ( ($inner_comp & 2) == 2 ) { $inner_arg1 = "(not:${mode} $inner_arg1)"; } - $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} + $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; if ( $inner_inv == 1 ) { $inner_exp = "(not:${mode} $inner_exp)"; @@ -209,26 +241,35 @@ sub gen_2logical if ( ($outer_comp & 2) == 2 ) { $inner_exp = "(not:${mode} $inner_exp)"; } - $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} + if ( $is_rsubf == 1 ) { + $outer_exp = "(${outer_rtl}:${mode} ${outer_arg2} + ${inner_exp})"; + $outer_32 = "%2,%3"; + $outer_42 = "%2,%4"; + } else { + $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; + $outer_32 = "%3,%2"; + $outer_42 = "%4,%2"; + } if ( $outer_inv == 1 ) { $outer_exp = "(not:${mode} $outer_exp)"; } $insn = <<"EOF"; -;; logical-logical fusion pattern generated by gen_2logical -;; $kind $inner_op -> $outer_op -(define_insn "*fuse_${inner_op}_${outer_op}" +;; $ftype fusion pattern generated by gen_logical_addsubf +;; $kind $inner_op -> $outer_name +(define_insn "*fuse_${inner_op}_${outer_name}" [(set (match_operand:${mode} 3 "${pred}" "=0,1,&${constraint},${constraint}") ${outer_exp}) (clobber (match_scratch:${mode} 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION && $target_flag)" "@ - ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2" + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}" [(set_attr "type" "$fuse_type") (set_attr "cost" "6") (set_attr "length" "8")]) @@ -247,14 +288,14 @@ sub gen_addadd if ( $kind eq 'vector' ) { $vchr = "v"; $op = "vaddudm"; - $ty = "fuse_vec"; + $ty = "fused_vector"; $mode = "V2DI"; $pred = "altivec_register_operand"; $constraint = "v"; } else { $vchr = ""; $op = "add"; - $ty = "fuse_arithlog"; + $ty = "fused_arith_logical"; $mode = "GPR"; $pred = "gpc_reg_operand"; $constraint = "r"; @@ -284,7 +325,7 @@ EOF } gen_ld_cmpi_p10(); -gen_2logical(); +gen_logical_addsubf(); gen_addadd(); exit(0); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index d46a91dd11b..52ce84835f7 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,6 +86,8 @@ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_P10_FUSION_LD_CMPI \ | OPTION_MASK_P10_FUSION_2LOGICAL \ + | OPTION_MASK_P10_FUSION_LOGADD \ + | OPTION_MASK_P10_FUSION_ADDLOG \ | OPTION_MASK_P10_FUSION_2ADD) /* Flags that need to be turned off if -mno-power9-vector. */ @@ -136,6 +138,8 @@ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_P10_FUSION_LD_CMPI \ | OPTION_MASK_P10_FUSION_2LOGICAL \ + | OPTION_MASK_P10_FUSION_LOGADD \ + | OPTION_MASK_P10_FUSION_ADDLOG \ | OPTION_MASK_P10_FUSION_2ADD \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9488a54a1d7..d7ae73827c5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4467,6 +4467,12 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL; + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LOGADD) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LOGADD; + + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ADDLOG) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ADDLOG; + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index fc14325ed33..07ce9aba18b 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -502,6 +502,14 @@ mpower10-fusion-2logical Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags) Fuse certain integer operations together for better performance on power10. +mpower10-fusion-logical-add +Target Undocumented Mask(P10_FUSION_LOGADD) Var(rs6000_isa_flags) +Fuse certain integer operations together for better performance on power10. + +mpower10-fusion-add-logical +Target Undocumented Mask(P10_FUSION_ADDLOG) Var(rs6000_isa_flags) +Fuse certain integer operations together for better performance on power10. + mpower10-fusion-2add Target Undocumented Mask(P10_FUSION_2ADD) Var(rs6000_isa_flags) Fuse certain add operations together for better performance on power10. diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c new file mode 100644 index 00000000000..0367abe6aad --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c @@ -0,0 +1,98 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-options "-mdejagnu-cpu=power10 -O3 -dp" } */ + +#include <altivec.h> +#include <stdint.h> + +#define ADD(a,b) ((a)+(b)) +#define SUB1(a,b) ((a)-(b)) +#define SUB2(a,b) ((b)-(a)) + +/* and/andc/eqv/nand/nor/or/orc/xor */ +#define AND(a,b) ((a)&(b)) +#define NAND(a,b) (~((a)&(b))) +#define NOR(a,b) (~((a)|(b))) +#define OR(a,b) ((a)|(b)) +#define TEST1(type, func) \ + type func ## _add_T_ ## type (type a, type b, type c) { return ADD(func(a,b),c); } \ + type func ## _sub1_T_ ## type (type a, type b, type c) { return SUB1(func(a,b),c); } \ + type func ## _sub2_T_ ## type (type a, type b, type c) { return SUB2(func(a,b),c); } \ + type func ## _rev_add_T_ ## type (type a, type b, type c) { return ADD(c,func(a,b)); } \ + type func ## _rev_sub1_T_ ## type (type a, type b, type c) { return SUB1(c,func(a,b)); } \ + type func ## _rev_sub2_T_ ## type (type a, type b, type c) { return SUB2(c,func(a,b)); } +#define TEST2(type, func) \ + type func ## _and_T_ ## type (type a, type b, type c) { return AND(func(a,b),c); } \ + type func ## _nand_T_ ## type (type a, type b, type c) { return NAND(func(a,b),c); } \ + type func ## _or_T_ ## type (type a, type b, type c) { return OR(func(a,b),c); } \ + type func ## _nor_T_ ## type (type a, type b, type c) { return NOR(func(a,b),c); } \ + type func ## _rev_and_T_ ## type (type a, type b, type c) { return AND(c,func(a,b)); } \ + type func ## _rev_nand_T_ ## type (type a, type b, type c) { return NAND(c,func(a,b)); } \ + type func ## _rev_or_T_ ## type (type a, type b, type c) { return OR(c,func(a,b)); } \ + type func ## _rev_nor_T_ ## type (type a, type b, type c) { return NOR(c,func(a,b)); } +#define TEST(type) \ + TEST1(type,AND) \ + TEST1(type,NAND) \ + TEST1(type,NOR) \ + TEST1(type,OR) \ + TEST2(type,ADD) \ + TEST2(type,SUB1) \ + TEST2(type,SUB2) + +typedef vector bool char vboolchar_t; +typedef vector unsigned int vuint_t; + +TEST(uint8_t); +TEST(int8_t); +TEST(uint16_t); +TEST(int16_t); +TEST(uint32_t); +TEST(int32_t); +TEST(uint64_t); +TEST(int64_t); + +/* { dg-final { scan-assembler-times "fuse_nand_rsubf/0" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_rsubf/2" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_rsubf/0" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_rsubf/2" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nand/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nor/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_add_or/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_and_rsubf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_and_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_add/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_add/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_or_rsubf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_or_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nand/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nand/1" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nor/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nor/1" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_or/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_or/1" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_and_add/0" 6 } } */ +/* { dg-final { scan-assembler-times "fuse_or_add/0" 6 } } */ +/* { dg-final { scan-assembler-times "fuse_add_and/0" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_add_and/2" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_and/0" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_and/1" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nand/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nor/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_add_or/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_and_rsubf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_and_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_add/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_add/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_or_rsubf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_or_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_and/2" 16 } } */ +/* { dg-final { scan-assembler-times "fuse_and_add/2" 22 } } */ +/* { dg-final { scan-assembler-times "fuse_or_add/2" 22 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nand/2" 24 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nor/2" 24 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_or/2" 24 } } */ + -- 2.27.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH,rs6000 2/2] Fusion patterns for add-logical/logical-add 2021-04-26 20:21 ` [PATCH,rs6000 2/2] Fusion patterns for add-logical/logical-add acsawdey @ 2021-05-19 22:15 ` Segher Boessenkool 2021-05-24 19:41 ` Aaron Sawdey 0 siblings, 1 reply; 7+ messages in thread From: Segher Boessenkool @ 2021-05-19 22:15 UTC (permalink / raw) To: acsawdey; +Cc: gcc-patches, wschmidt, will_schmidt On Mon, Apr 26, 2021 at 03:21:30PM -0500, acsawdey@linux.ibm.com wrote: > This patch modifies the function in genfusion.pl for generating > the logical-logical patterns so that it can also generate the > add-logical and logical-add patterns which are very similar. > + $outer_32 = "%2,%3"; > + $outer_42 = "%2,%4"; I think you had trouble thinking of good names here :-) > +mpower10-fusion-logical-add > +Target Undocumented Mask(P10_FUSION_LOGADD) Var(rs6000_isa_flags) > +Fuse certain integer operations together for better performance on power10. > + > +mpower10-fusion-add-logical > +Target Undocumented Mask(P10_FUSION_ADDLOG) Var(rs6000_isa_flags) > +Fuse certain integer operations together for better performance on power10. Do you not want to say something a little more precise here? > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c > @@ -0,0 +1,98 @@ > +/* { dg-do compile { target { powerpc*-*-* } } } */ > +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ Same issues here as in the previous patch. Other than those things, okay for trunk and backport to 11. Thanks! Segher ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH,rs6000 2/2] Fusion patterns for add-logical/logical-add 2021-05-19 22:15 ` Segher Boessenkool @ 2021-05-24 19:41 ` Aaron Sawdey 0 siblings, 0 replies; 7+ messages in thread From: Aaron Sawdey @ 2021-05-24 19:41 UTC (permalink / raw) To: gcc-patches; +Cc: segher, Aaron Sawdey One last addendum to this. I discovered that that needs a "sort" in front of "keys %logicals_addsub" because otherwise you may get the operators in different orders sometimes which leads to fusion.md having the patterns in different orders which isn't helpful for sane debugging. Segher and I discussed it offline so I'm posting the final patch for posterity. Also coming will be some updates to the test cases. Things optimize differently with -m32 apparently so I'll have to add different counts of the counts of the different fusion patterns for "{ target ilp32 }" as the current counts in those files only apply to "{ target lp64 }". Aaron gcc/ChangeLog: * config/rs6000/genfusion.pl (gen_logical_addsubf): Refactor to add generation of logical-add and add-logical fusion pairs. * config/rs6000/rs6000-cpus.def: Add new fusion to ISA 3.1 mask and powerpc mask. * config/rs6000/rs6000.c (rs6000_option_override_internal): Turn on logical-add and add-logical fusion by default. * config/rs6000.opt: Add -mpower10-fusion-logical-add and -mpower10-fusion-add-logical options. * config/rs6000/fusion.md: Regenerate file. gcc/testsuite/ChangeLog: * gcc.target/powerpc/fusion-p10-logadd.c: New file. --- gcc/config/rs6000/fusion.md | 872 +++++++++++++----- gcc/config/rs6000/genfusion.pl | 83 +- gcc/config/rs6000/rs6000-cpus.def | 4 + gcc/config/rs6000/rs6000.c | 8 + gcc/config/rs6000/rs6000.opt | 12 +- .../gcc.target/powerpc/fusion-p10-logadd.c | 97 ++ 6 files changed, 797 insertions(+), 279 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 4d810e6ba13..51912106663 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -355,11 +355,11 @@ (define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero" (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> and (define_insn "*fuse_and_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -373,11 +373,11 @@ (define_insn "*fuse_and_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> and (define_insn "*fuse_andc_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -391,11 +391,11 @@ (define_insn "*fuse_andc_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> and (define_insn "*fuse_eqv_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -409,11 +409,11 @@ (define_insn "*fuse_eqv_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> and (define_insn "*fuse_nand_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -427,11 +427,11 @@ (define_insn "*fuse_nand_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> and (define_insn "*fuse_nor_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -445,11 +445,11 @@ (define_insn "*fuse_nor_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> and (define_insn "*fuse_or_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -463,11 +463,11 @@ (define_insn "*fuse_or_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> and (define_insn "*fuse_orc_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -481,11 +481,11 @@ (define_insn "*fuse_orc_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> and (define_insn "*fuse_xor_and" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -499,11 +499,47 @@ (define_insn "*fuse_xor_and" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> and +(define_insn "*fuse_add_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;and %3,%3,%2 + add %3,%1,%0\;and %3,%3,%2 + add %3,%1,%0\;and %3,%3,%2 + add %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> and +(define_insn "*fuse_subf_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;and %3,%3,%2 + subf %3,%1,%0\;and %3,%3,%2 + subf %3,%1,%0\;and %3,%3,%2 + subf %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> andc (define_insn "*fuse_and_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -517,11 +553,11 @@ (define_insn "*fuse_and_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> andc (define_insn "*fuse_andc_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -535,11 +571,11 @@ (define_insn "*fuse_andc_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> andc (define_insn "*fuse_eqv_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -553,11 +589,11 @@ (define_insn "*fuse_eqv_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> andc (define_insn "*fuse_nand_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -571,11 +607,11 @@ (define_insn "*fuse_nand_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> andc (define_insn "*fuse_nor_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -589,11 +625,11 @@ (define_insn "*fuse_nor_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> andc (define_insn "*fuse_or_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -607,11 +643,11 @@ (define_insn "*fuse_or_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> andc (define_insn "*fuse_orc_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -625,11 +661,11 @@ (define_insn "*fuse_orc_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> andc (define_insn "*fuse_xor_andc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -643,11 +679,11 @@ (define_insn "*fuse_xor_andc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> eqv (define_insn "*fuse_and_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -661,11 +697,11 @@ (define_insn "*fuse_and_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> eqv (define_insn "*fuse_andc_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -679,11 +715,11 @@ (define_insn "*fuse_andc_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> eqv (define_insn "*fuse_eqv_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -697,11 +733,11 @@ (define_insn "*fuse_eqv_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> eqv (define_insn "*fuse_nand_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -715,11 +751,11 @@ (define_insn "*fuse_nand_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> eqv (define_insn "*fuse_nor_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -733,11 +769,11 @@ (define_insn "*fuse_nor_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> eqv (define_insn "*fuse_or_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -751,11 +787,11 @@ (define_insn "*fuse_or_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> eqv (define_insn "*fuse_orc_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -769,11 +805,11 @@ (define_insn "*fuse_orc_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> eqv (define_insn "*fuse_xor_eqv" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -787,11 +823,11 @@ (define_insn "*fuse_xor_eqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> nand (define_insn "*fuse_and_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -805,11 +841,11 @@ (define_insn "*fuse_and_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> nand (define_insn "*fuse_andc_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -823,11 +859,11 @@ (define_insn "*fuse_andc_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> nand (define_insn "*fuse_eqv_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -841,11 +877,11 @@ (define_insn "*fuse_eqv_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> nand (define_insn "*fuse_nand_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -859,11 +895,11 @@ (define_insn "*fuse_nand_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> nand (define_insn "*fuse_nor_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -877,11 +913,11 @@ (define_insn "*fuse_nor_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> nand (define_insn "*fuse_or_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -895,11 +931,11 @@ (define_insn "*fuse_or_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> nand (define_insn "*fuse_orc_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -913,11 +949,11 @@ (define_insn "*fuse_orc_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> nand (define_insn "*fuse_xor_nand" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -931,11 +967,47 @@ (define_insn "*fuse_xor_nand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> nand +(define_insn "*fuse_add_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;nand %3,%3,%2 + add %3,%1,%0\;nand %3,%3,%2 + add %3,%1,%0\;nand %3,%3,%2 + add %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> nand +(define_insn "*fuse_subf_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;nand %3,%3,%2 + subf %3,%1,%0\;nand %3,%3,%2 + subf %3,%1,%0\;nand %3,%3,%2 + subf %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> nor (define_insn "*fuse_and_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -949,11 +1021,11 @@ (define_insn "*fuse_and_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> nor (define_insn "*fuse_andc_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -967,11 +1039,11 @@ (define_insn "*fuse_andc_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> nor (define_insn "*fuse_eqv_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -985,11 +1057,11 @@ (define_insn "*fuse_eqv_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> nor (define_insn "*fuse_nand_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1003,11 +1075,11 @@ (define_insn "*fuse_nand_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> nor (define_insn "*fuse_nor_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1021,11 +1093,11 @@ (define_insn "*fuse_nor_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> nor (define_insn "*fuse_or_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1039,11 +1111,11 @@ (define_insn "*fuse_or_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> nor (define_insn "*fuse_orc_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1057,11 +1129,11 @@ (define_insn "*fuse_orc_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> nor (define_insn "*fuse_xor_nor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1075,11 +1147,47 @@ (define_insn "*fuse_xor_nor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> nor +(define_insn "*fuse_add_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;nor %3,%3,%2 + add %3,%1,%0\;nor %3,%3,%2 + add %3,%1,%0\;nor %3,%3,%2 + add %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> nor +(define_insn "*fuse_subf_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;nor %3,%3,%2 + subf %3,%1,%0\;nor %3,%3,%2 + subf %3,%1,%0\;nor %3,%3,%2 + subf %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> or (define_insn "*fuse_and_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1093,11 +1201,11 @@ (define_insn "*fuse_and_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> or (define_insn "*fuse_andc_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1111,11 +1219,11 @@ (define_insn "*fuse_andc_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> or (define_insn "*fuse_eqv_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1129,11 +1237,11 @@ (define_insn "*fuse_eqv_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> or (define_insn "*fuse_nand_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1147,11 +1255,11 @@ (define_insn "*fuse_nand_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> or (define_insn "*fuse_nor_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1165,11 +1273,11 @@ (define_insn "*fuse_nor_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> or (define_insn "*fuse_or_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1183,11 +1291,11 @@ (define_insn "*fuse_or_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> or (define_insn "*fuse_orc_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1201,11 +1309,11 @@ (define_insn "*fuse_orc_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> or (define_insn "*fuse_xor_or" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1219,11 +1327,47 @@ (define_insn "*fuse_xor_or" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar add -> or +(define_insn "*fuse_add_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + add %3,%1,%0\;or %3,%3,%2 + add %3,%1,%0\;or %3,%3,%2 + add %3,%1,%0\;or %3,%3,%2 + add %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; add-logical fusion pattern generated by gen_logical_addsubf +;; scalar subf -> or +(define_insn "*fuse_subf_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_ADDLOG)" + "@ + subf %3,%1,%0\;or %3,%3,%2 + subf %3,%1,%0\;or %3,%3,%2 + subf %3,%1,%0\;or %3,%3,%2 + subf %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> orc (define_insn "*fuse_and_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1237,11 +1381,11 @@ (define_insn "*fuse_and_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> orc (define_insn "*fuse_andc_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1255,11 +1399,11 @@ (define_insn "*fuse_andc_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> orc (define_insn "*fuse_eqv_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1273,11 +1417,11 @@ (define_insn "*fuse_eqv_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> orc (define_insn "*fuse_nand_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1291,11 +1435,11 @@ (define_insn "*fuse_nand_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> orc (define_insn "*fuse_nor_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1309,11 +1453,11 @@ (define_insn "*fuse_nor_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> orc (define_insn "*fuse_or_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1327,11 +1471,11 @@ (define_insn "*fuse_or_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> orc (define_insn "*fuse_orc_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1345,11 +1489,11 @@ (define_insn "*fuse_orc_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> orc (define_insn "*fuse_xor_orc" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1363,11 +1507,11 @@ (define_insn "*fuse_xor_orc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar and -> xor (define_insn "*fuse_and_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1381,11 +1525,11 @@ (define_insn "*fuse_and_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar andc -> xor (define_insn "*fuse_andc_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1399,11 +1543,11 @@ (define_insn "*fuse_andc_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar eqv -> xor (define_insn "*fuse_eqv_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1417,11 +1561,11 @@ (define_insn "*fuse_eqv_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nand -> xor (define_insn "*fuse_nand_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1435,11 +1579,11 @@ (define_insn "*fuse_nand_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar nor -> xor (define_insn "*fuse_nor_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1453,11 +1597,11 @@ (define_insn "*fuse_nor_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar or -> xor (define_insn "*fuse_or_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1471,11 +1615,11 @@ (define_insn "*fuse_or_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar orc -> xor (define_insn "*fuse_orc_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1489,11 +1633,11 @@ (define_insn "*fuse_orc_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; scalar xor -> xor (define_insn "*fuse_xor_xor" [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") - (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] @@ -1507,11 +1651,227 @@ (define_insn "*fuse_xor_xor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar and -> add +(define_insn "*fuse_and_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + and %3,%1,%0\;add %3,%3,%2 + and %3,%1,%0\;add %3,%3,%2 + and %3,%1,%0\;add %3,%3,%2 + and %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nand -> add +(define_insn "*fuse_nand_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nand %3,%1,%0\;add %3,%3,%2 + nand %3,%1,%0\;add %3,%3,%2 + nand %3,%1,%0\;add %3,%3,%2 + nand %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nor -> add +(define_insn "*fuse_nor_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nor %3,%1,%0\;add %3,%3,%2 + nor %3,%1,%0\;add %3,%3,%2 + nor %3,%1,%0\;add %3,%3,%2 + nor %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar or -> add +(define_insn "*fuse_or_add" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (plus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + or %3,%1,%0\;add %3,%3,%2 + or %3,%1,%0\;add %3,%3,%2 + or %3,%1,%0\;add %3,%3,%2 + or %4,%1,%0\;add %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar and -> subf +(define_insn "*fuse_and_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + and %3,%1,%0\;subf %3,%3,%2 + and %3,%1,%0\;subf %3,%3,%2 + and %3,%1,%0\;subf %3,%3,%2 + and %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nand -> subf +(define_insn "*fuse_nand_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nand %3,%1,%0\;subf %3,%3,%2 + nand %3,%1,%0\;subf %3,%3,%2 + nand %3,%1,%0\;subf %3,%3,%2 + nand %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nor -> subf +(define_insn "*fuse_nor_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nor %3,%1,%0\;subf %3,%3,%2 + nor %3,%1,%0\;subf %3,%3,%2 + nor %3,%1,%0\;subf %3,%3,%2 + nor %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar or -> subf +(define_insn "*fuse_or_subf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + or %3,%1,%0\;subf %3,%3,%2 + or %3,%1,%0\;subf %3,%3,%2 + or %3,%1,%0\;subf %3,%3,%2 + or %4,%1,%0\;subf %3,%4,%2" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar and -> rsubf +(define_insn "*fuse_and_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + and %3,%1,%0\;subf %3,%2,%3 + and %3,%1,%0\;subf %3,%2,%3 + and %3,%1,%0\;subf %3,%2,%3 + and %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nand -> rsubf +(define_insn "*fuse_nand_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nand %3,%1,%0\;subf %3,%2,%3 + nand %3,%1,%0\;subf %3,%2,%3 + nand %3,%1,%0\;subf %3,%2,%3 + nand %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar nor -> rsubf +(define_insn "*fuse_nor_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + nor %3,%1,%0\;subf %3,%2,%3 + nor %3,%1,%0\;subf %3,%2,%3 + nor %3,%1,%0\;subf %3,%2,%3 + nor %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-add fusion pattern generated by gen_logical_addsubf +;; scalar or -> rsubf +(define_insn "*fuse_or_rsubf" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") + (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)" + "@ + or %3,%1,%0\;subf %3,%2,%3 + or %3,%1,%0\;subf %3,%2,%3 + or %3,%1,%0\;subf %3,%2,%3 + or %4,%1,%0\;subf %3,%2,%4" + [(set_attr "type" "fused_arith_logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vand (define_insn "*fuse_vand_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1525,11 +1885,11 @@ (define_insn "*fuse_vand_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vand (define_insn "*fuse_vandc_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1543,11 +1903,11 @@ (define_insn "*fuse_vandc_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vand (define_insn "*fuse_veqv_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1561,11 +1921,11 @@ (define_insn "*fuse_veqv_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vand (define_insn "*fuse_vnand_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1579,11 +1939,11 @@ (define_insn "*fuse_vnand_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vand (define_insn "*fuse_vnor_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1597,11 +1957,11 @@ (define_insn "*fuse_vnor_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vand (define_insn "*fuse_vor_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1615,11 +1975,11 @@ (define_insn "*fuse_vor_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vand (define_insn "*fuse_vorc_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1633,11 +1993,11 @@ (define_insn "*fuse_vorc_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vand (define_insn "*fuse_vxor_vand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1651,11 +2011,11 @@ (define_insn "*fuse_vxor_vand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vandc (define_insn "*fuse_vand_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1669,11 +2029,11 @@ (define_insn "*fuse_vand_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vandc (define_insn "*fuse_vandc_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1687,11 +2047,11 @@ (define_insn "*fuse_vandc_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vandc (define_insn "*fuse_veqv_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1705,11 +2065,11 @@ (define_insn "*fuse_veqv_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vandc (define_insn "*fuse_vnand_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1723,11 +2083,11 @@ (define_insn "*fuse_vnand_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vandc (define_insn "*fuse_vnor_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1741,11 +2101,11 @@ (define_insn "*fuse_vnor_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vandc (define_insn "*fuse_vor_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1759,11 +2119,11 @@ (define_insn "*fuse_vor_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vandc (define_insn "*fuse_vorc_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1777,11 +2137,11 @@ (define_insn "*fuse_vorc_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vandc (define_insn "*fuse_vxor_vandc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1795,11 +2155,11 @@ (define_insn "*fuse_vxor_vandc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> veqv (define_insn "*fuse_vand_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1813,11 +2173,11 @@ (define_insn "*fuse_vand_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> veqv (define_insn "*fuse_vandc_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1831,11 +2191,11 @@ (define_insn "*fuse_vandc_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> veqv (define_insn "*fuse_veqv_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1849,11 +2209,11 @@ (define_insn "*fuse_veqv_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> veqv (define_insn "*fuse_vnand_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1867,11 +2227,11 @@ (define_insn "*fuse_vnand_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> veqv (define_insn "*fuse_vnor_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1885,11 +2245,11 @@ (define_insn "*fuse_vnor_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> veqv (define_insn "*fuse_vor_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1903,11 +2263,11 @@ (define_insn "*fuse_vor_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> veqv (define_insn "*fuse_vorc_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1921,11 +2281,11 @@ (define_insn "*fuse_vorc_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> veqv (define_insn "*fuse_vxor_veqv" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1939,11 +2299,11 @@ (define_insn "*fuse_vxor_veqv" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnand (define_insn "*fuse_vand_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1957,11 +2317,11 @@ (define_insn "*fuse_vand_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnand (define_insn "*fuse_vandc_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1975,11 +2335,11 @@ (define_insn "*fuse_vandc_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnand (define_insn "*fuse_veqv_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -1993,11 +2353,11 @@ (define_insn "*fuse_veqv_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnand (define_insn "*fuse_vnand_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2011,11 +2371,11 @@ (define_insn "*fuse_vnand_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnand (define_insn "*fuse_vnor_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2029,11 +2389,11 @@ (define_insn "*fuse_vnor_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnand (define_insn "*fuse_vor_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2047,11 +2407,11 @@ (define_insn "*fuse_vor_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnand (define_insn "*fuse_vorc_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2065,11 +2425,11 @@ (define_insn "*fuse_vorc_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnand (define_insn "*fuse_vxor_vnand" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2083,11 +2443,11 @@ (define_insn "*fuse_vxor_vnand" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnor (define_insn "*fuse_vand_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2101,11 +2461,11 @@ (define_insn "*fuse_vand_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnor (define_insn "*fuse_vandc_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2119,11 +2479,11 @@ (define_insn "*fuse_vandc_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnor (define_insn "*fuse_veqv_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2137,11 +2497,11 @@ (define_insn "*fuse_veqv_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnor (define_insn "*fuse_vnand_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2155,11 +2515,11 @@ (define_insn "*fuse_vnand_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnor (define_insn "*fuse_vnor_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2173,11 +2533,11 @@ (define_insn "*fuse_vnor_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnor (define_insn "*fuse_vor_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2191,11 +2551,11 @@ (define_insn "*fuse_vor_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnor (define_insn "*fuse_vorc_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2209,11 +2569,11 @@ (define_insn "*fuse_vorc_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnor (define_insn "*fuse_vxor_vnor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2227,11 +2587,11 @@ (define_insn "*fuse_vxor_vnor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vor (define_insn "*fuse_vand_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2245,11 +2605,11 @@ (define_insn "*fuse_vand_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vor (define_insn "*fuse_vandc_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2263,11 +2623,11 @@ (define_insn "*fuse_vandc_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vor (define_insn "*fuse_veqv_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2281,11 +2641,11 @@ (define_insn "*fuse_veqv_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vor (define_insn "*fuse_vnand_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2299,11 +2659,11 @@ (define_insn "*fuse_vnand_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vor (define_insn "*fuse_vnor_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2317,11 +2677,11 @@ (define_insn "*fuse_vnor_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vor (define_insn "*fuse_vor_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2335,11 +2695,11 @@ (define_insn "*fuse_vor_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vor (define_insn "*fuse_vorc_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2353,11 +2713,11 @@ (define_insn "*fuse_vorc_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vor (define_insn "*fuse_vxor_vor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2371,11 +2731,11 @@ (define_insn "*fuse_vxor_vor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vorc (define_insn "*fuse_vand_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2389,11 +2749,11 @@ (define_insn "*fuse_vand_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vorc (define_insn "*fuse_vandc_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2407,11 +2767,11 @@ (define_insn "*fuse_vandc_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vorc (define_insn "*fuse_veqv_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2425,11 +2785,11 @@ (define_insn "*fuse_veqv_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vorc (define_insn "*fuse_vnand_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2443,11 +2803,11 @@ (define_insn "*fuse_vnand_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vorc (define_insn "*fuse_vnor_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2461,11 +2821,11 @@ (define_insn "*fuse_vnor_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vorc (define_insn "*fuse_vor_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2479,11 +2839,11 @@ (define_insn "*fuse_vor_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vorc (define_insn "*fuse_vorc_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2497,11 +2857,11 @@ (define_insn "*fuse_vorc_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vorc (define_insn "*fuse_vxor_vorc" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2515,11 +2875,11 @@ (define_insn "*fuse_vxor_vorc" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vxor (define_insn "*fuse_vand_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2533,11 +2893,11 @@ (define_insn "*fuse_vand_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vxor (define_insn "*fuse_vandc_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2551,11 +2911,11 @@ (define_insn "*fuse_vandc_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vxor (define_insn "*fuse_veqv_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2569,11 +2929,11 @@ (define_insn "*fuse_veqv_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vxor (define_insn "*fuse_vnand_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2587,11 +2947,11 @@ (define_insn "*fuse_vnand_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vxor (define_insn "*fuse_vnor_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2605,11 +2965,11 @@ (define_insn "*fuse_vnor_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vxor (define_insn "*fuse_vor_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2623,11 +2983,11 @@ (define_insn "*fuse_vor_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vxor (define_insn "*fuse_vorc_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] @@ -2641,11 +3001,11 @@ (define_insn "*fuse_vorc_vxor" (set_attr "cost" "6") (set_attr "length" "8")]) -;; logical-logical fusion pattern generated by gen_2logical +;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vxor (define_insn "*fuse_vxor_vxor" [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") - (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:VM 4 "=X,X,X,&r"))] diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 1fd46cc0604..1285dd42043 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -144,23 +144,32 @@ sub gen_ld_cmpi_p10 } } -sub gen_2logical +sub gen_logical_addsubf { my @logicals = ( "and", "andc", "eqv", "nand", "nor", "or", "orc", "xor" ); + my %logicals_addsub = ( "and"=>1, "nand"=>1, "nor"=>1, "or"=>1 ); + my @addsub = ( "add", "subf" ); + my %isaddsub = ( "add"=>1, "subf"=>1 ); my %complement = ( "and"=> 0, "andc"=> 1, "eqv"=> 0, "nand"=> 3, - "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0 ); + "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0, + "add"=> 0, "subf"=> 0 ); my %invert = ( "and"=> 0, "andc"=> 0, "eqv"=> 1, "nand"=> 0, - "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0 ); + "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0, + "add"=> 0, "subf"=> 0 ); my %commute2 = ( "and"=> 1, "andc"=> 0, "eqv"=> 1, "nand"=> 0, "nor"=> 0, "or"=> 1, "orc"=> 0, "xor"=> 1 ); my %rtlop = ( "and"=>"and", "andc"=>"and", "eqv"=>"xor", "nand"=>"ior", - "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor" ); + "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor", + "add"=>"plus", "subf"=>"minus" ); - my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, $outer_op, - $outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp, $inner_inv, - $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, - $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn, $fuse_type); + my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, @outer_ops, + $outer_op, $outer_comp, $outer_inv, $outer_rtl, $inner, @inner_ops, + $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4, + $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, + $target_flag, $ftype, $insn, $is_rsubf, $outer_32, $outer_42, + $outer_name, $fuse_type); KIND: foreach $kind ('scalar','vector') { + @outer_ops = @logicals; if ( $kind eq 'vector' ) { $vchr = "v"; $mode = "VM"; @@ -173,14 +182,37 @@ sub gen_2logical $pred = "gpc_reg_operand"; $constraint = "r"; $fuse_type = "fused_arith_logical"; + push (@outer_ops, @addsub); + push (@outer_ops, ( "rsubf" )); } $c4 = "${constraint},${constraint},${constraint},${constraint}"; - OUTER: foreach $outer ( @logicals ) { + OUTER: foreach $outer ( @outer_ops ) { + $outer_name = "${vchr}${outer}"; + if ( $outer eq "rsubf" ) { + $is_rsubf = 1; + $outer = "subf"; + } else { + $is_rsubf = 0; + } $outer_op = "${vchr}${outer}"; $outer_comp = $complement{$outer}; $outer_inv = $invert{$outer}; $outer_rtl = $rtlop{$outer}; - INNER: foreach $inner ( @logicals ) { + @inner_ops = @logicals; + $ftype = "logical-logical"; + $target_flag = "TARGET_P10_FUSION_2LOGICAL"; + if ( exists $isaddsub{$outer} ) { + @inner_ops = sort keys %logicals_addsub; + $ftype = "logical-add"; + $target_flag = "TARGET_P10_FUSION_LOGADD"; + } elsif ( $kind ne 'vector' && exists $logicals_addsub{$outer} ) { + push (@inner_ops, @addsub); + } + INNER: foreach $inner ( @inner_ops ) { + if ( exists $isaddsub{$inner} ) { + $ftype = "add-logical"; + $target_flag = "TARGET_P10_FUSION_ADDLOG"; + } $inner_comp = $complement{$inner}; $inner_inv = $invert{$inner}; $inner_rtl = $rtlop{$inner}; @@ -197,7 +229,7 @@ sub gen_2logical if ( ($inner_comp & 2) == 2 ) { $inner_arg1 = "(not:${mode} $inner_arg1)"; } - $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} + $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; if ( $inner_inv == 1 ) { $inner_exp = "(not:${mode} $inner_exp)"; @@ -209,26 +241,35 @@ sub gen_2logical if ( ($outer_comp & 2) == 2 ) { $inner_exp = "(not:${mode} $inner_exp)"; } - $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} + if ( $is_rsubf == 1 ) { + $outer_exp = "(${outer_rtl}:${mode} ${outer_arg2} + ${inner_exp})"; + $outer_32 = "%2,%3"; + $outer_42 = "%2,%4"; + } else { + $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; + $outer_32 = "%3,%2"; + $outer_42 = "%4,%2"; + } if ( $outer_inv == 1 ) { $outer_exp = "(not:${mode} $outer_exp)"; } $insn = <<"EOF"; -;; logical-logical fusion pattern generated by gen_2logical -;; $kind $inner_op -> $outer_op -(define_insn "*fuse_${inner_op}_${outer_op}" +;; $ftype fusion pattern generated by gen_logical_addsubf +;; $kind $inner_op -> $outer_name +(define_insn "*fuse_${inner_op}_${outer_name}" [(set (match_operand:${mode} 3 "${pred}" "=0,1,&${constraint},${constraint}") ${outer_exp}) (clobber (match_scratch:${mode} 4 "=X,X,X,&r"))] - "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "(TARGET_P10_FUSION && $target_flag)" "@ - ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2" + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}" [(set_attr "type" "$fuse_type") (set_attr "cost" "6") (set_attr "length" "8")]) @@ -284,7 +325,7 @@ EOF } gen_ld_cmpi_p10(); -gen_2logical(); +gen_logical_addsubf(); gen_addadd; exit(0); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index d46a91dd11b..52ce84835f7 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,6 +86,8 @@ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_P10_FUSION_LD_CMPI \ | OPTION_MASK_P10_FUSION_2LOGICAL \ + | OPTION_MASK_P10_FUSION_LOGADD \ + | OPTION_MASK_P10_FUSION_ADDLOG \ | OPTION_MASK_P10_FUSION_2ADD) /* Flags that need to be turned off if -mno-power9-vector. */ @@ -136,6 +138,8 @@ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_P10_FUSION_LD_CMPI \ | OPTION_MASK_P10_FUSION_2LOGICAL \ + | OPTION_MASK_P10_FUSION_LOGADD \ + | OPTION_MASK_P10_FUSION_ADDLOG \ | OPTION_MASK_P10_FUSION_2ADD \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9f03256065e..835af7708f9 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4477,6 +4477,14 @@ rs6000_option_override_internal (bool global_init_p) && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL; + if (TARGET_POWER10 + && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LOGADD) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LOGADD; + + if (TARGET_POWER10 + && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ADDLOG) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ADDLOG; + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0) rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index e30dc040651..0538db387dc 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -500,11 +500,19 @@ Fuse certain integer operations together for better performance on power10. mpower10-fusion-2logical Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags) -Fuse certain integer operations together for better performance on power10. +Fuse pairs of scalar or vector logical operations together for better performance on power10. + +mpower10-fusion-logical-add +Target Undocumented Mask(P10_FUSION_LOGADD) Var(rs6000_isa_flags) +Fuse scalar logical op with add/subf for better performance on power10. + +mpower10-fusion-add-logical +Target Undocumented Mask(P10_FUSION_ADDLOG) Var(rs6000_isa_flags) +Fuse scalar add/subf with logical op for better performance on power10. mpower10-fusion-2add Target Undocumented Mask(P10_FUSION_2ADD) Var(rs6000_isa_flags) -Fuse certain add operations together for better performance on power10. +Fuse dependent pairs of add or vaddudm instructions for better performance on power10. mcrypto Target Mask(CRYPTO) Var(rs6000_isa_flags) diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c new file mode 100644 index 00000000000..b7022b2b61d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c @@ -0,0 +1,97 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power10 -O3 -dp" } */ + +#include <altivec.h> +#include <stdint.h> + +#define ADD(a,b) ((a)+(b)) +#define SUB1(a,b) ((a)-(b)) +#define SUB2(a,b) ((b)-(a)) + +/* and/andc/eqv/nand/nor/or/orc/xor */ +#define AND(a,b) ((a)&(b)) +#define NAND(a,b) (~((a)&(b))) +#define NOR(a,b) (~((a)|(b))) +#define OR(a,b) ((a)|(b)) +#define TEST1(type, func) \ + type func ## _add_T_ ## type (type a, type b, type c) { return ADD(func(a,b),c); } \ + type func ## _sub1_T_ ## type (type a, type b, type c) { return SUB1(func(a,b),c); } \ + type func ## _sub2_T_ ## type (type a, type b, type c) { return SUB2(func(a,b),c); } \ + type func ## _rev_add_T_ ## type (type a, type b, type c) { return ADD(c,func(a,b)); } \ + type func ## _rev_sub1_T_ ## type (type a, type b, type c) { return SUB1(c,func(a,b)); } \ + type func ## _rev_sub2_T_ ## type (type a, type b, type c) { return SUB2(c,func(a,b)); } +#define TEST2(type, func) \ + type func ## _and_T_ ## type (type a, type b, type c) { return AND(func(a,b),c); } \ + type func ## _nand_T_ ## type (type a, type b, type c) { return NAND(func(a,b),c); } \ + type func ## _or_T_ ## type (type a, type b, type c) { return OR(func(a,b),c); } \ + type func ## _nor_T_ ## type (type a, type b, type c) { return NOR(func(a,b),c); } \ + type func ## _rev_and_T_ ## type (type a, type b, type c) { return AND(c,func(a,b)); } \ + type func ## _rev_nand_T_ ## type (type a, type b, type c) { return NAND(c,func(a,b)); } \ + type func ## _rev_or_T_ ## type (type a, type b, type c) { return OR(c,func(a,b)); } \ + type func ## _rev_nor_T_ ## type (type a, type b, type c) { return NOR(c,func(a,b)); } +#define TEST(type) \ + TEST1(type,AND) \ + TEST1(type,NAND) \ + TEST1(type,NOR) \ + TEST1(type,OR) \ + TEST2(type,ADD) \ + TEST2(type,SUB1) \ + TEST2(type,SUB2) + +typedef vector bool char vboolchar_t; +typedef vector unsigned int vuint_t; + +TEST(uint8_t); +TEST(int8_t); +TEST(uint16_t); +TEST(int16_t); +TEST(uint32_t); +TEST(int32_t); +TEST(uint64_t); +TEST(int64_t); + +/* { dg-final { scan-assembler-times "fuse_nand_rsubf/0" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_rsubf/2" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_rsubf/0" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_rsubf/2" 2 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nand/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nor/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_add_or/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_and_rsubf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_and_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_add/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_add/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_or_rsubf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_or_subf/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nand/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nand/1" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nor/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nor/1" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_or/0" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_or/1" 4 } } */ +/* { dg-final { scan-assembler-times "fuse_and_add/0" 6 } } */ +/* { dg-final { scan-assembler-times "fuse_or_add/0" 6 } } */ +/* { dg-final { scan-assembler-times "fuse_add_and/0" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_add_and/2" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_and/0" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_and/1" 8 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nand/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_add_nor/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_add_or/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_and_rsubf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_and_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_add/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nand_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_add/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_nor_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_or_rsubf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_or_subf/2" 12 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_and/2" 16 } } */ +/* { dg-final { scan-assembler-times "fuse_and_add/2" 22 } } */ +/* { dg-final { scan-assembler-times "fuse_or_add/2" 22 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nand/2" 24 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_nor/2" 24 } } */ +/* { dg-final { scan-assembler-times "fuse_subf_or/2" 24 } } */ + -- 2.27.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series 2021-04-26 20:21 [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series acsawdey 2021-04-26 20:21 ` [PATCH,rs6000 1/2] combine patterns for add-add fusion acsawdey 2021-04-26 20:21 ` [PATCH,rs6000 2/2] Fusion patterns for add-logical/logical-add acsawdey @ 2021-05-11 13:50 ` Aaron Sawdey 2 siblings, 0 replies; 7+ messages in thread From: Aaron Sawdey @ 2021-05-11 13:50 UTC (permalink / raw) To: gcc-patches; +Cc: Segher Boessenkool Ping. Aaron Sawdey, Ph.D. sawdey@linux.ibm.com IBM Linux on POWER Toolchain > On Apr 26, 2021, at 3:21 PM, acsawdey@linux.ibm.com wrote: > > From: Aaron Sawdey <acsawdey@linux.ibm.com> > > Two more sets of combine patterns for p10 fusion. These require > the "Add insn types for fusion pairs" patch I posted earlier today. > > If ok I would like to put these in gcc 12 trunk and backport for 11.2. > > Thanks, > Aaron > > Aaron Sawdey (2): > combine patterns for add-add fusion > Fusion patterns for add-logical/logical-add > > gcc/config/rs6000/fusion.md | 908 +++++++++++++----- > gcc/config/rs6000/genfusion.pl | 127 ++- > gcc/config/rs6000/rs6000-cpus.def | 8 +- > gcc/config/rs6000/rs6000.c | 9 + > gcc/config/rs6000/rs6000.opt | 12 + > .../gcc.target/powerpc/fusion-p10-addadd.c | 41 + > .../gcc.target/powerpc/fusion-p10-logadd.c | 98 ++ > 7 files changed, 925 insertions(+), 278 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/powerpc/fusion-p10-addadd.c > create mode 100644 gcc/testsuite/gcc.target/powerpc/fusion-p10-logadd.c > > -- > 2.27.0 > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-05-24 19:41 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-04-26 20:21 [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series acsawdey 2021-04-26 20:21 ` [PATCH,rs6000 1/2] combine patterns for add-add fusion acsawdey 2021-05-19 21:29 ` Segher Boessenkool 2021-04-26 20:21 ` [PATCH,rs6000 2/2] Fusion patterns for add-logical/logical-add acsawdey 2021-05-19 22:15 ` Segher Boessenkool 2021-05-24 19:41 ` Aaron Sawdey 2021-05-11 13:50 ` [PATCH,rs6000 0/2] p10 add-add and add-logical fusion series Aaron Sawdey
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