From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 03A59384A00F for ; Tue, 17 Nov 2020 18:42:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 03A59384A00F Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0AHIYwr0140293; Tue, 17 Nov 2020 13:42:02 -0500 Received: from ppma03wdc.us.ibm.com (ba.79.3fa9.ip4.static.sl-reverse.com [169.63.121.186]) by mx0a-001b2d01.pphosted.com with ESMTP id 34vehg3mwu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Nov 2020 13:42:02 -0500 Received: from pps.filterd (ppma03wdc.us.ibm.com [127.0.0.1]) by ppma03wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 0AHIftTp009432; Tue, 17 Nov 2020 18:42:01 GMT Received: from b03cxnp07028.gho.boulder.ibm.com (b03cxnp07028.gho.boulder.ibm.com [9.17.130.15]) by ppma03wdc.us.ibm.com with ESMTP id 34t6v90p7v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Nov 2020 18:42:01 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0AHIfxPo17564234 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 17 Nov 2020 18:41:59 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B4E3A6E04E; Tue, 17 Nov 2020 18:41:59 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EE9D16E04C; Tue, 17 Nov 2020 18:41:58 +0000 (GMT) Received: from [9.160.103.180] (unknown [9.160.103.180]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 17 Nov 2020 18:41:58 +0000 (GMT) Subject: Re: [PATCH,rs6000] Make MMA builtins use opaque modes To: acsawdey@linux.ibm.com, gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, wschmidt@linux.ibm.com References: <20201117174804.2218917-1-acsawdey@linux.ibm.com> From: Peter Bergner Message-ID: <7a81891c-cad1-b83a-bd8c-0e132d7a607f@linux.ibm.com> Date: Tue, 17 Nov 2020 12:41:58 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.4.3 MIME-Version: 1.0 In-Reply-To: <20201117174804.2218917-1-acsawdey@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-17_07:2020-11-17, 2020-11-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 mlxlogscore=832 phishscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011170133 X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Nov 2020 18:42:05 -0000 On 11/17/20 11:48 AM, acsawdey@linux.ibm.com wrote: > -;; The MMA patterns use the multi-register PXImode and POImode partial > +;; The MMA patterns use the multi-register XOmode and OOmode partial > ;; integer modes to implement the target specific __vector_quad and XOmode and OOmode are not partial integer modes, so change to opaque mode. > +;; Return 1 if this operand is valid for an MMA disassemble insn. > +(define_predicate "mma_disassemble_output_operand" > + (match_code "reg,subreg,mem") > +{ > + if (REG_P (op) && !vsx_register_operand (op, mode)) > + return false; > + return true; > +}) Do we really want to accept subregs here? If so, why are they not also required to be vsx_register_operand()? > - if ((attr & RS6000_BTC_QUAD) == 0) > + if ( !( d->code == MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL > + || d->code == MMA_BUILTIN_DISASSEMBLE_PAIR_INTERNAL) > + && ((attr & RS6000_BTC_QUAD) == 0)) No white space after the '('. > - if (icode == CODE_FOR_nothing) > + /* This is a disassemble pair/acc function. */ > + if ( d->code == MMA_BUILTIN_DISASSEMBLE_ACC > + || d->code == MMA_BUILTIN_DISASSEMBLE_PAIR) Ditto. > + /* The __vector_pair and __vector_quad modes are multi-register > + modes, so if have to load or store the registers, we have to be > + careful to properly swap them if we're in little endian mode s/so if have to/so if we have to/ > - /* We are writing an accumulator register, so we have to > - prime it after we've written it. */ > - emit_insn (gen_mma_xxmtacc (dst, dst)); > + if ( GET_MODE (src) == XOmode ) White space again. > /* Move register range backwards, if we might have destructive > overlap. */ > int i; > - for (i = nregs - 1; i >= 0; i--) > - emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode, > - i * reg_mode_size), > - simplify_gen_subreg (reg_mode, src, mode, > - i * reg_mode_size))); > + /* XO/OO are opaque so cannot use subregs. */ > + if ( mode == OOmode || mode == XOmode ) Ditto. > + /* XO/OO are opaque so cannot use subregs. */ > + if ( mode == OOmode || mode == XOmode ) Ditto. Peter