From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id C74D33857C42; Wed, 9 Nov 2022 03:01:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C74D33857C42 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2A92jAW5025637; Wed, 9 Nov 2022 03:01:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : references : date : in-reply-to : message-id : content-type : mime-version; s=pp1; bh=UvEoE0XQoaZ5AyTyZ66cP7qC8RPcFa4ynLLs9ti6Row=; b=OYbQdgUefUX5ay5MGvJ4hD7z4sgtGT5EAeLbf3oIntP92mP/hLOs4YgMWvstE9rPgCCm h/QwHjKmm5yBvyBJWiIwIoSU1hW8SsOw5TzUzueNevhL3ZEXMLEkD5eNw/tT8o1VrlM5 dQB+r/BqHNQt48PtuKuDh4sE608W++TfMrj4kxg82dfqaMGNeOq9VEf/UVaGBeaQThEE UtEv2ckRvGAI5Kuo5qQsJ3+5hrGnx1wU+N+hWHw1mIXx9nPeZ+w02eBMBJKkI9cMNTzO oqbaZ7yhY+FAiNtMRBRxE2gbssAh+lq2HY3fTpD4FwrFaQDFAW70QpAqBPxRpdBpKj+R Rg== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3kr3pv0c89-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); 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Wed, 9 Nov 2022 03:01:46 GMT Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3A6AD58058; Wed, 9 Nov 2022 03:01:45 +0000 (GMT) Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C524C58066; Wed, 9 Nov 2022 03:01:44 +0000 (GMT) Received: from pike (unknown [9.5.12.127]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Wed, 9 Nov 2022 03:01:44 +0000 (GMT) From: Jiufu Guo To: Jiufu Guo via Gcc-patches Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org Subject: Ping^3: [PATCH V6] rs6000: Optimize cmp on rotated 16bits constant References: <20220829034216.94029-1-guojiufu@linux.ibm.com> <7e7d25t7iq.fsf@pike.rch.stglabs.ibm.com> <7eleply24g.fsf_-_@pike.rch.stglabs.ibm.com> Date: Wed, 09 Nov 2022 11:01:41 +0800 In-Reply-To: <7eleply24g.fsf_-_@pike.rch.stglabs.ibm.com> (Jiufu Guo via Gcc-patches's message of "Wed, 12 Oct 2022 14:42:07 +0800") Message-ID: <7eleokvnje.fsf_-_@pike.rch.stglabs.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: j4ZDPrLCnnT_-utsjdaKm0Ok6XYgCxyW X-Proofpoint-ORIG-GUID: m2fuCdwFQjqTPQuJ7MQOa81R0cVU5RBv X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-07_11,2022-11-08_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 impostorscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211090016 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600475.html BR, Jeff (Jiufu) Jiufu Guo via Gcc-patches writes: > Gentle ping: > https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600475.html > > BR, > Jeff (Jiufu) > > Jiufu Guo via Gcc-patches writes: > >> Ping: https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600475.html >> >> BR, >> Jeff(Jiufu) >> >> >> Jiufu Guo writes: >> >>> Hi, >>> >>> When checking eq/ne with a constant which has only 16bits, it can be >>> optimized to check the rotated data. By this, the constant building >>> is optimized. >>> >>> As the example in PR103743: >>> For "in == 0x8000000000000000LL", this patch generates: >>> rotldi %r3,%r3,16 >>> cmpldi %cr0,%r3,32768 >>> instead: >>> li %r9,-1 >>> rldicr %r9,%r9,0,0 >>> cmpd %cr0,%r3,%r9 >>> >>> Compare with previous patchs: >>> https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600385.html >>> https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600198.html >>> >>> This patch releases the condition on can_create_pseudo_p and adds >>> clobbers to allow the splitter can be run both before and after RA. >>> >>> This is updated patch based on previous patch and comments: >>> https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600315.html >>> >>> This patch pass bootstrap and regtest on ppc64 and ppc64le. >>> Is it ok for trunk? Thanks for comments! >>> >>> BR, >>> Jeff(Jiufu) >>> >>> >>> PR target/103743 >>> >>> gcc/ChangeLog: >>> >>> * config/rs6000/rs6000-protos.h (rotate_from_leading_zeros_const): New. >>> (compare_rotate_immediate_p): New. >>> * config/rs6000/rs6000.cc (rotate_from_leading_zeros_const): New >>> definition. >>> (compare_rotate_immediate_p): New definition. >>> * config/rs6000/rs6000.md (EQNE): New code_attr. >>> (*rotate_on_cmpdi): New define_insn_and_split. >>> >>> gcc/testsuite/ChangeLog: >>> >>> * gcc.target/powerpc/pr103743.c: New test. >>> * gcc.target/powerpc/pr103743_1.c: New test. >>> >>> --- >>> gcc/config/rs6000/rs6000-protos.h | 2 + >>> gcc/config/rs6000/rs6000.cc | 41 ++++++++ >>> gcc/config/rs6000/rs6000.md | 62 +++++++++++- >>> gcc/testsuite/gcc.target/powerpc/pr103743.c | 52 ++++++++++ >>> gcc/testsuite/gcc.target/powerpc/pr103743_1.c | 95 +++++++++++++++++++ >>> 5 files changed, 251 insertions(+), 1 deletion(-) >>> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103743.c >>> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103743_1.c >>> >>> diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h >>> index b3c16e7448d..78847e6b3db 100644 >>> --- a/gcc/config/rs6000/rs6000-protos.h >>> +++ b/gcc/config/rs6000/rs6000-protos.h >>> @@ -35,6 +35,8 @@ extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); >>> extern int vspltis_shifted (rtx); >>> extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); >>> extern bool macho_lo_sum_memory_operand (rtx, machine_mode); >>> +extern int rotate_from_leading_zeros_const (unsigned HOST_WIDE_INT, int); >>> +extern bool compare_rotate_immediate_p (unsigned HOST_WIDE_INT); >>> extern int num_insns_constant (rtx, machine_mode); >>> extern int small_data_operand (rtx, machine_mode); >>> extern bool mem_operand_gpr (rtx, machine_mode); >>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc >>> index df491bee2ea..a548db42660 100644 >>> --- a/gcc/config/rs6000/rs6000.cc >>> +++ b/gcc/config/rs6000/rs6000.cc >>> @@ -14797,6 +14797,47 @@ rs6000_reverse_condition (machine_mode mode, enum rtx_code code) >>> return reverse_condition (code); >>> } >>> >>> +/* Check if C can be rotated from an immediate which starts (as 64bit integer) >>> + with at least CLZ bits zero. >>> + >>> + Return the number by which C can be rotated from the immediate. >>> + Return -1 if C can not be rotated as from. */ >>> + >>> +int >>> +rotate_from_leading_zeros_const (unsigned HOST_WIDE_INT c, int clz) >>> +{ >>> + /* case a. 0..0xxx: already at least clz zeros. */ >>> + int lz = clz_hwi (c); >>> + if (lz >= clz) >>> + return 0; >>> + >>> + /* case b. 0..0xxx0..0: at least clz zeros. */ >>> + int tz = ctz_hwi (c); >>> + if (lz + tz >= clz) >>> + return tz; >>> + >>> + /* case c. xx10.....0xx: rotate 'clz + 1' bits firstly, then check case b. >>> + ^bit -> Vbit >>> + 00...00xxx100, 'clz + 1' >= bits of xxxx. */ >>> + const int rot_bits = HOST_BITS_PER_WIDE_INT - clz + 1; >>> + unsigned HOST_WIDE_INT rc = (c >> rot_bits) | (c << (clz - 1)); >>> + tz = ctz_hwi (rc); >>> + if (clz_hwi (rc) + tz >= clz) >>> + return tz + rot_bits; >>> + >>> + return -1; >>> +} >>> + >>> +/* Check if C can be rotated from an immediate operand of cmpdi or cmpldi. */ >>> + >>> +bool >>> +compare_rotate_immediate_p (unsigned HOST_WIDE_INT c) >>> +{ >>> + /* leading 48 zeros (cmpldi), or leading 49 ones (cmpdi). */ >>> + return rotate_from_leading_zeros_const (~c, 49) > 0 >>> + || rotate_from_leading_zeros_const (c, 48) > 0; >>> +} >>> + >>> /* Generate a compare for CODE. Return a brand-new rtx that >>> represents the result of the compare. */ >>> >>> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md >>> index e9e5cd1e54d..cad3cfc98cd 100644 >>> --- a/gcc/config/rs6000/rs6000.md >>> +++ b/gcc/config/rs6000/rs6000.md >>> @@ -7766,6 +7766,67 @@ (define_insn "*movsi_from_df" >>> "xscvdpsp %x0,%x1" >>> [(set_attr "type" "fp")]) >>> >>> + >>> +(define_code_iterator eqne [eq ne]) >>> +(define_code_attr EQNE [(eq "EQ") (ne "NE")]) >>> + >>> +;; "i == C" ==> "rotl(i,N) == rotl(C,N)" >>> +(define_insn_and_split "*rotate_on_cmpdi" >>> + [(set (pc) >>> + (if_then_else (eqne (match_operand:DI 1 "gpc_reg_operand" "r") >>> + (match_operand:DI 2 "const_int_operand" "n")) >>> + (label_ref (match_operand 0 "")) >>> + (pc))) >>> + (clobber (match_scratch:DI 3 "=r")) >>> + (clobber (match_scratch:CCUNS 4 "=y"))] >>> + "TARGET_POWERPC64 && num_insns_constant (operands[2], DImode) > 1 >>> + && compare_rotate_immediate_p (UINTVAL (operands[2]))" >>> + "#" >>> + "&& 1" >>> + [(pc)] >>> +{ >>> + rtx note = find_reg_note (curr_insn, REG_BR_PROB, 0); >>> + bool sgn = false; >>> + unsigned HOST_WIDE_INT C = INTVAL (operands[2]); >>> + int rot = rotate_from_leading_zeros_const (C, 48); >>> + if (rot < 0) >>> + { >>> + sgn = true; >>> + rot = rotate_from_leading_zeros_const (~C, 49); >>> + } >>> + rtx n = GEN_INT (HOST_BITS_PER_WIDE_INT - rot); >>> + >>> + /* i' = rotl (i, n) */ >>> + rtx op0 = can_create_pseudo_p () ? gen_reg_rtx (DImode) : operands[3]; >>> + emit_insn (gen_rtx_SET (op0, gen_rtx_ROTATE (DImode, operands[1], n))); >>> + >>> + /* C' = rotl (C, n) */ >>> + rtx op1 = GEN_INT ((C << INTVAL (n)) | (C >> rot)); >>> + >>> + /* i' == C' */ >>> + machine_mode comp_mode = sgn ? CCmode : CCUNSmode; >>> + rtx cc = can_create_pseudo_p () ? gen_reg_rtx (comp_mode) : operands[4]; >>> + PUT_MODE (cc, comp_mode); >>> + emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (comp_mode, op0, op1))); >>> + rtx cmp = gen_rtx_ (CCmode, cc, const0_rtx); >>> + rtx loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[0]); >>> + emit_jump_insn (gen_rtx_SET (pc_rtx, >>> + gen_rtx_IF_THEN_ELSE (VOIDmode, cmp, >>> + loc_ref, pc_rtx))); >>> + >>> + /* keep the probability info for the prediction of the branch insn. */ >>> + if (note) >>> + { >>> + profile_probability prob >>> + = profile_probability::from_reg_br_prob_note (XINT (note, 0)); >>> + >>> + add_reg_br_prob_note (get_last_insn (), prob); >>> + } >>> + >>> + DONE; >>> +} >>> +) >>> + >>> ;; Split a load of a large constant into the appropriate two-insn >>> ;; sequence. >>> >>> @@ -13472,7 +13533,6 @@ (define_expand "@ctr" >>> ;; rs6000_legitimate_combined_insn prevents combine creating any of >>> ;; the ctr insns. >>> >>> -(define_code_iterator eqne [eq ne]) >>> (define_code_attr bd [(eq "bdz") (ne "bdnz")]) >>> (define_code_attr bd_neg [(eq "bdnz") (ne "bdz")]) >>> >>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr103743.c b/gcc/testsuite/gcc.target/powerpc/pr103743.c >>> new file mode 100644 >>> index 00000000000..abb876ed79e >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/powerpc/pr103743.c >>> @@ -0,0 +1,52 @@ >>> +/* { dg-options "-O2" } */ >>> +/* { dg-do compile { target has_arch_ppc64 } } */ >>> + >>> +/* { dg-final { scan-assembler-times {\mcmpldi\M} 10 } } */ >>> +/* { dg-final { scan-assembler-times {\mcmpdi\M} 4 } } */ >>> +/* { dg-final { scan-assembler-times {\mrotldi\M} 14 } } */ >>> + >>> +int foo (int a); >>> + >>> +int __attribute__ ((noinline)) udi_fun (unsigned long long in) >>> +{ >>> + if (in == (0x8642000000000000ULL)) >>> + return foo (1); >>> + if (in == (0x7642000000000000ULL)) >>> + return foo (12); >>> + if (in == (0x8000000000000000ULL)) >>> + return foo (32); >>> + if (in == (0x8000000000000001ULL)) >>> + return foo (33); >>> + if (in == (0x8642FFFFFFFFFFFFULL)) >>> + return foo (46); >>> + if (in == (0x7642FFFFFFFFFFFFULL)) >>> + return foo (51); >>> + if (in == (0x7567000000ULL)) >>> + return foo (9); >>> + if (in == (0xFFF8567FFFFFFFFFULL)) >>> + return foo (19); >>> + >>> + return 0; >>> +} >>> + >>> +int __attribute__ ((noinline)) di_fun (long long in) >>> +{ >>> + if (in == (0x8642000000000000LL)) >>> + return foo (1); >>> + if (in == (0x7642000000000000LL)) >>> + return foo (12); >>> + if (in == (0x8000000000000000LL)) >>> + return foo (32); >>> + if (in == (0x8000000000000001LL)) >>> + return foo (33); >>> + if (in == (0x8642FFFFFFFFFFFFLL)) >>> + return foo (46); >>> + if (in == (0x7642FFFFFFFFFFFFLL)) >>> + return foo (51); >>> + if (in == (0x7567000000LL)) >>> + return foo (9); >>> + if (in == (0xFFF8567FFFFFFFFFLL)) >>> + return foo (19); >>> + >>> + return 0; >>> +} >>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr103743_1.c b/gcc/testsuite/gcc.target/powerpc/pr103743_1.c >>> new file mode 100644 >>> index 00000000000..2c08c56714a >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/powerpc/pr103743_1.c >>> @@ -0,0 +1,95 @@ >>> +/* { dg-do run } */ >>> +/* { dg-options "-O2 -std=c99" } */ >>> + >>> +int >>> +foo (int a) >>> +{ >>> + return a + 6; >>> +} >>> + >>> +int __attribute__ ((noinline)) udi_fun (unsigned long long in) >>> +{ >>> + if (in == (0x8642000000000000ULL)) >>> + return foo (1); >>> + if (in == (0x7642000000000000ULL)) >>> + return foo (12); >>> + if (in == (0x8000000000000000ULL)) >>> + return foo (32); >>> + if (in == (0x8000000000000001ULL)) >>> + return foo (33); >>> + if (in == (0x8642FFFFFFFFFFFFULL)) >>> + return foo (46); >>> + if (in == (0x7642FFFFFFFFFFFFULL)) >>> + return foo (51); >>> + if (in == (0x7567000000ULL)) >>> + return foo (9); >>> + if (in == (0xFFF8567FFFFFFFFFULL)) >>> + return foo (19); >>> + >>> + return 0; >>> +} >>> + >>> +int __attribute__ ((noinline)) di_fun (long long in) >>> +{ >>> + if (in == (0x8642000000000000LL)) >>> + return foo (1); >>> + if (in == (0x7642000000000000LL)) >>> + return foo (12); >>> + if (in == (0x8000000000000000LL)) >>> + return foo (32); >>> + if (in == (0x8000000000000001LL)) >>> + return foo (33); >>> + if (in == (0x8642FFFFFFFFFFFFLL)) >>> + return foo (46); >>> + if (in == (0x7642FFFFFFFFFFFFLL)) >>> + return foo (51); >>> + return 0; >>> +} >>> + >>> +int >>> +main () >>> +{ >>> + int e = 0; >>> + if (udi_fun (6) != 0) >>> + e++; >>> + if (udi_fun (0x8642000000000000ULL) != foo (1)) >>> + e++; >>> + if (udi_fun (0x7642000000000000ULL) != foo (12)) >>> + e++; >>> + if (udi_fun (0x8000000000000000ULL) != foo (32)) >>> + e++; >>> + if (udi_fun (0x8000000000000001ULL) != foo (33)) >>> + e++; >>> + if (udi_fun (0x8642FFFFFFFFFFFFULL) != foo (46)) >>> + e++; >>> + if (udi_fun (0x7642FFFFFFFFFFFFULL) != foo (51)) >>> + e++; >>> + if (udi_fun (0x7567000000ULL) != foo (9)) >>> + e++; >>> + if (udi_fun (0xFFF8567FFFFFFFFFULL) != foo (19)) >>> + e++; >>> + >>> + if (di_fun (6) != 0) >>> + e++; >>> + if (di_fun (0x8642000000000000LL) != foo (1)) >>> + e++; >>> + if (di_fun (0x7642000000000000LL) != foo (12)) >>> + e++; >>> + if (di_fun (0x8000000000000000LL) != foo (32)) >>> + e++; >>> + if (di_fun (0x8000000000000001LL) != foo (33)) >>> + e++; >>> + if (di_fun (0x8642FFFFFFFFFFFFLL) != foo (46)) >>> + e++; >>> + if (di_fun (0x7642FFFFFFFFFFFFLL) != foo (51)) >>> + e++; >>> + if (udi_fun (0x7567000000LL) != foo (9)) >>> + e++; >>> + if (udi_fun (0xFFF8567FFFFFFFFFLL) != foo (19)) >>> + e++; >>> + >>> + if (e) >>> + __builtin_abort (); >>> + return 0; >>> +} >>> +