From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 143C33855166; Fri, 25 Nov 2022 13:21:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 143C33855166 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2APCitsP029168; Fri, 25 Nov 2022 13:21:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : references : date : in-reply-to : message-id : mime-version : content-type; s=pp1; bh=HRWzgS+TokhgFGEYYCgw6wsBQBj+L7NAxpnLUb+D36U=; b=Zlpjpl1e70g9thS/e5a1WCI03xdMnOq8t9NSp3bBTeQjcX7xz9qdcBGtI+5l8rM7Obpg WyMXPjguc1kjHyAQTEglL7BLLP0bBmSkaKpckUBF9BNYYxKx4FV0J9Rn6QtSLa2mklC3 LRmBXiLxDoDXj3bSR1+/z0/t/VyCZmWGcCABjtbGlTohhQFxlflwbifK2C3L+s8pwEw+ N4YgGbA+RTFyqILsygBvcV2R6VkYs0Wpvx1aeCP6z8CmenOF9nBAuptg8KtBOHk1Txbe o7bc466Tb8QSGucZ7PKAOP5rzysp5p8kiBWS8nJhY0McIyZbXtHZNdX2PDqYiW5Klgvc bg== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3m2wyy8uj0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Nov 2022 13:21:28 +0000 Received: from m0187473.ppops.net (m0187473.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2APDELLT022260; Fri, 25 Nov 2022 13:21:28 GMT Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3m2wyy8uhp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Nov 2022 13:21:28 +0000 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 2APDLCTc010074; Fri, 25 Nov 2022 13:21:26 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma04wdc.us.ibm.com with ESMTP id 3kxps9yrxw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Nov 2022 13:21:26 +0000 Received: from smtpav05.dal12v.mail.ibm.com ([9.208.128.132]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2APDLRXO32571858 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 25 Nov 2022 13:21:28 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 95CED58052; Fri, 25 Nov 2022 13:21:25 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5121A5804C; Fri, 25 Nov 2022 13:21:25 +0000 (GMT) Received: from pike (unknown [9.5.12.127]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTPS; Fri, 25 Nov 2022 13:21:25 +0000 (GMT) From: Jiufu Guo To: "Kewen.Lin" Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, gcc-patches@gcc.gnu.org Subject: Re: [PATCH]rs6000: Load high and low part of 64bit constant independently References: <20220915083052.74903-1-guojiufu@linux.ibm.com> <7b482d49-3928-552c-ccf5-d391684b7f2b@linux.ibm.com> Date: Fri, 25 Nov 2022 21:21:21 +0800 In-Reply-To: <7b482d49-3928-552c-ccf5-d391684b7f2b@linux.ibm.com> (Kewen Lin's message of "Fri, 25 Nov 2022 17:15:17 +0800") Message-ID: <7ev8n3p3u6.fsf@pike.rch.stglabs.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: hWsOdT7WFVYtTXhGC6hsy3H3SgzDDEVS X-Proofpoint-ORIG-GUID: MNzub24BjUDJl1U1svX_JZATM-u_UwRk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-25_05,2022-11-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211250102 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Kewen, Thanks for your review on this patch! "Kewen.Lin" writes: > Hi Jeff, > > Sorry for the late review. > > on 2022/9/15 16:30, Jiufu Guo wrote: >> Hi, >> >> For a complicate 64bit constant, blow is one instruction-sequence to >> build: >> lis 9,0x800a >> ori 9,9,0xabcd >> sldi 9,9,32 >> oris 9,9,0xc167 >> ori 9,9,0xfa16 >> >> while we can also use below sequence to build: >> lis 9,0xc167 >> lis 10,0x800a >> ori 9,9,0xfa16 >> ori 10,10,0xabcd >> rldimi 9,10,32,0 >> This sequence is using 2 registers to build high and low part firstly, >> and then merge them. >> In parallel aspect, this sequence would be faster. (Ofcause, using 1 more >> register with potential register pressure). >> >> Bootstrap and regtest pass on ppc64le. >> Is this ok for trunk? >> >> >> BR, >> Jeff(Jiufu) >> >> >> gcc/ChangeLog: >> >> * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Update 64bit >> constant build. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/powerpc/parall_5insn_const.c: New test. >> >> --- >> gcc/config/rs6000/rs6000.cc | 45 +++++++++++-------- >> .../gcc.target/powerpc/parall_5insn_const.c | 27 +++++++++++ >> 2 files changed, 53 insertions(+), 19 deletions(-) >> create mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c >> >> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc >> index a656cb32a47..759c6309677 100644 >> --- a/gcc/config/rs6000/rs6000.cc >> +++ b/gcc/config/rs6000/rs6000.cc >> @@ -10180,26 +10180,33 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) >> } >> else >> { >> - temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); >> - >> - emit_move_insn (copy_rtx (temp), >> - GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000)); >> - if (ud3 != 0) >> - emit_move_insn (copy_rtx (temp), >> - gen_rtx_IOR (DImode, copy_rtx (temp), >> - GEN_INT (ud3))); >> + if (can_create_pseudo_p ()) >> + { >> + /* lis A,U4; ori A,U3; lis B,U2; ori B,U1; rldimi A,B,32,0. */ > > Nit: A, B are supposed to be H, L? Yes, thanks for this catch! It should be /* lis H,U4; ori H,U3; lis L,U2; ori L,U1; rldimi L,H,32,0. */ > >> + rtx H = gen_reg_rtx (DImode); >> + rtx L = gen_reg_rtx (DImode); >> + HOST_WIDE_INT num = (ud2 << 16) | ud1; >> + rs6000_emit_set_long_const (L, (num ^ 0x80000000) - 0x80000000); >> + num = (ud4 << 16) | ud3; >> + rs6000_emit_set_long_const (H, (num ^ 0x80000000) - 0x80000000); >> + emit_insn (gen_rotldi3_insert_3 (dest, H, GEN_INT (32), L, >> + GEN_INT (0xffffffff))); >> + } >> + else >> + { >> + /* lis A, U4; ori A,U3; rotl A,32; oris A,U2; ori A,U1. */ > ~~~ unexpected space? Thanks for the catch! > >> + emit_move_insn (dest, >> + GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000)); >> + if (ud3 != 0) >> + emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); >> >> - emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest, >> - gen_rtx_ASHIFT (DImode, copy_rtx (temp), >> - GEN_INT (32))); >> - if (ud2 != 0) >> - emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest, >> - gen_rtx_IOR (DImode, copy_rtx (temp), >> - GEN_INT (ud2 << 16))); >> - if (ud1 != 0) >> - emit_move_insn (dest, >> - gen_rtx_IOR (DImode, copy_rtx (temp), >> - GEN_INT (ud1))); >> + emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); >> + if (ud2 != 0) >> + emit_move_insn (dest, >> + gen_rtx_IOR (DImode, dest, GEN_INT (ud2 << 16))); >> + if (ud1 != 0) >> + emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); >> + } >> } >> } >> >> diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c >> new file mode 100644 >> index 00000000000..ed8ccc73378 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c >> @@ -0,0 +1,27 @@ >> +/* { dg-do run } */ >> +/* { dg-options "-O2 -mdejagnu-cpu=power7 -save-temps" } */ > > Why do we need power7 here? power8/9 are also ok for this case. Actually, O just want to avoid to use new p10 instruction, like "pli", and then selected an old arch option. > >> +/* { dg-require-effective-target has_arch_ppc64 } */ >> + >> +/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */ >> +/* { dg-final { scan-assembler-times {\mori\M} 4 } } */ >> +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ >> + >> +void __attribute__ ((noinline)) foo (unsigned long long *a) >> +{ >> + /* 2lis+2ori+1rldimi for each constant. */ > > Nit: seems better to read with "/* 2 lis + 2 ori + 1 rldimi for ..." Thanks for your sugguestion! BR, Jeff (Jiufu) I updated it as below: gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Update 64bit constant build. gcc/testsuite/ChangeLog: * gcc.target/powerpc/parall_5insn_const.c: New test. --- gcc/config/rs6000/rs6000.cc | 45 +++++++++++-------- .../gcc.target/powerpc/parall_5insn_const.c | 27 +++++++++++ 2 files changed, 53 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index a656cb32a47..759c6309677 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10180,26 +10180,33 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) } else { - temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); - - emit_move_insn (copy_rtx (temp), - GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000)); - if (ud3 != 0) - emit_move_insn (copy_rtx (temp), - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud3))); + if (can_create_pseudo_p ()) + { + /* lis H,U4; ori H,U3; lis L,U2; ori L,U1; rldimi L,H,32,0. */ + rtx H = gen_reg_rtx (DImode); + rtx L = gen_reg_rtx (DImode); + HOST_WIDE_INT num = (ud2 << 16) | ud1; + rs6000_emit_set_long_const (L, (num ^ 0x80000000) - 0x80000000); + num = (ud4 << 16) | ud3; + rs6000_emit_set_long_const (H, (num ^ 0x80000000) - 0x80000000); + emit_insn (gen_rotldi3_insert_3 (dest, H, GEN_INT (32), L, + GEN_INT (0xffffffff))); + } + else + { + /* lis A,U4; ori A,U3; rotl A,32; oris A,U2; ori A,U1. */ + emit_move_insn (dest, + GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000)); + if (ud3 != 0) + emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); - emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest, - gen_rtx_ASHIFT (DImode, copy_rtx (temp), - GEN_INT (32))); - if (ud2 != 0) - emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest, - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud2 << 16))); - if (ud1 != 0) - emit_move_insn (dest, - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud1))); + emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); + if (ud2 != 0) + emit_move_insn (dest, + gen_rtx_IOR (DImode, dest, GEN_INT (ud2 << 16))); + if (ud1 != 0) + emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); + } } } diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c new file mode 100644 index 00000000000..ed8ccc73378 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c @@ -0,1 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -save-temps" } */ +/* { dg-require-effective-target has_arch_ppc64 } */ + +/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mori\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ + +void __attribute__ ((noinline)) foo (unsigned long long *a) +{ + /* 2 lis + 2 ori + 1 rldimi for each constant. */ + *a++ = 0x800aabcdc167fa16ULL; + *a++ = 0x7543a876867f616ULL; +} + +long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL}; +int +main () +{ + long long res[2]; + + foo (res); + if (__builtin_memcmp (res, A, sizeof (res)) != 0) + __builtin_abort (); + + return 0; +} -- 2.17.1 > > BR, > Kewen