From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 3F8BD3858429; Thu, 11 Aug 2022 12:52:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3F8BD3858429 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27BCkTb7011251; Thu, 11 Aug 2022 12:52:54 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3hw22nr6bu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Aug 2022 12:52:54 +0000 Received: from m0187473.ppops.net (m0187473.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 27BCl1Pn012636; Thu, 11 Aug 2022 12:52:54 GMT Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3hw22nr6b2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Aug 2022 12:52:54 +0000 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 27BColkn007447; Thu, 11 Aug 2022 12:52:53 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma05wdc.us.ibm.com with ESMTP id 3hvcmrea1v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Aug 2022 12:52:52 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27BCqqeO66585044 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 11 Aug 2022 12:52:52 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8279E124053; Thu, 11 Aug 2022 12:52:52 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 458CF124052; Thu, 11 Aug 2022 12:52:52 +0000 (GMT) Received: from pike (unknown [9.5.12.127]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTPS; Thu, 11 Aug 2022 12:52:52 +0000 (GMT) From: Jiufu Guo To: Segher Boessenkool Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, linkw@gcc.gnu.org Subject: Re: [PATCH] rs6000: Enable generate const through pli+pli+rldimi References: <20220810071123.165157-1-guojiufu@linux.ibm.com> <20220810164306.GY25951@gate.crashing.org> Date: Thu, 11 Aug 2022 20:52:49 +0800 In-Reply-To: <20220810164306.GY25951@gate.crashing.org> (Segher Boessenkool's message of "Wed, 10 Aug 2022 11:43:06 -0500") Message-ID: <7ev8qzkkm6.fsf@pike.rch.stglabs.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: MVF6coCA_MNL31VA4hblNr-TjPcpleXz X-Proofpoint-GUID: pg_fs6fLTk2SFtmDg3NM9DVla_nxXyPr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-11_10,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 suspectscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208110039 X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Aug 2022 12:52:57 -0000 Hi, Segher Boessenkool writes: > Hi! > > On Wed, Aug 10, 2022 at 03:11:23PM +0800, Jiufu Guo wrote: >> As mentioned in PR106550, since pli could support 34bits immediate, we could >> use less instructions(3insn would be ok) to build 64bits constant with pli. >> >> For example, for constant 0x020805006106003, we could generate it with: >> asm code1: >> pli 9,101736451 (0x6106003) >> sldi 9,9,32 >> paddi 9,9, 2130000 (0x0208050) >> >> or asm code2: >> pli 10, 2130000 >> pli 9, 101736451 >> rldimi 9, 10, 32, 0 >> >> If there is only one register can be used, then the asm code1 is ok. Otherwise >> asm code2 may be better. > > It is significantly better yes. That code with sldi is perhaps what we > have to do after reload, but all those three insns are sequential, > expensive. > >> This patch re-enable the constant building(splitter) before RA by updating the >> constrains from int_reg_operand_not_pseudo to gpc_reg_operand. And then, we >> could use two different pseduo for two pli(s), and asm code2 can be generated. > >> This patch also could generate asm code1 if hard register is allocated for the >> constant. > >> + else if (TARGET_PREFIXED) >> + { >> + /* pli 9,high32 + pli 10,low32 + rldimi 9,10,32,0. */ >> + if (can_create_pseudo_p ()) >> + { >> + temp = gen_reg_rtx (DImode); >> + rtx temp1 = gen_reg_rtx (DImode); >> + emit_move_insn (copy_rtx (temp), GEN_INT ((ud4 << 16) | ud3)); >> + emit_move_insn (copy_rtx (temp1), GEN_INT ((ud2 << 16) | ud1)); >> + >> + rtx one = gen_rtx_AND (DImode, temp1, GEN_INT (0xffffffff)); > > Why do you meed to mask the value here? That is a nop, no? As you mentioned, this is not needed if using gen_rotldi3_insert_3. > >> + rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32)); >> + emit_move_insn (dest, gen_rtx_IOR (DImode, one, two)); > > But you can call gen_rotldi3_insert_3 explicitly, a better idea if this > code can run late (so we cannot rely on other optimisations to clean > things up). Thanks! Using gen_rotldi3_insert_3 would indicate the rotate behavior explicitly. emit_insn (gen_rotldi3_insert_3 (dest, temp, GEN_INT (32), temp1, GEN_INT (0xffffffff))); > >> --- a/gcc/config/rs6000/rs6000.md >> +++ b/gcc/config/rs6000/rs6000.md >> @@ -9659,7 +9659,7 @@ (define_split >> ;; When non-easy constants can go in the TOC, this should use >> ;; easy_fp_constant predicate. >> (define_split >> - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") >> + [(set (match_operand:DI 0 "gpc_reg_operand") >> (match_operand:DI 1 "const_int_operand"))] >> "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" >> [(set (match_dup 0) (match_dup 2)) > > This is a huge change. Do you have some indication that it helps / > hurts / is neutral? Some reasoning why it is a good idea? Thanks for this concern! I would do more check/test for this. The 'int_reg_operand_not_pseudo' cause this splitter only work after RA. Using 'int_reg_operand_not_pseudo', the code sequence "pli+sldi+paddi" can be used. > > I am not against it, but some more rationale would be good :-) > > Btw, this splitter uses operands[2] and [3] in the replacement, and > neither of those exists. The replacement never is used of course. > Instead, rs6000_emit_set_const is called always. It would be less > misleading if the replacement text was just "(pc)" or such. Right, "(pc)" would be better to avoid misleading. BR, Jeff(Jiufu) > > > Segher