From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 1B9EA3856278; Fri, 26 Aug 2022 09:28:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1B9EA3856278 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27Q9Qfft038998; Fri, 26 Aug 2022 09:28:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : references : date : in-reply-to : message-id : mime-version : content-type; s=pp1; bh=d3XY2f3i5Q1KGvqrnn0hXp43s7OHi6hvHVvY1GFUa9o=; b=DQvK8RuOD5gh+KHE1VSOAwhuxx2vVjxhbt3Z4HYDiE5EFOSWi7iZDMW79owyY01BwMl9 4lrouUBeaEcERSZdgy+51UpwSDND+/f/uf8sjmuCvr7AOiEgZZo59/jSbwrNGiOppKFA CrqVoFbdNSqgp5GdNs5r6/pjSeRxJ46/HbzrouUJ9N5LMxoUymHlkN0bRqX+Ti8C2ppr 6bDFJGpKzNCkrecVZe3CeErNDm5UZbrg7BvaJYecKWVnYyxGKp8WGFCmuAPY99ZYkC0x O9DkPQUAg7TCQPAtm2a4zgS0aAQ4hLU3J4a0DEvrOW3/61UgmE8GwIEQYErSv03c+27w uw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3j6uj2g104-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 Aug 2022 09:28:19 +0000 Received: from m0187473.ppops.net (m0187473.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 27Q9SCEc001115; Fri, 26 Aug 2022 09:28:19 GMT Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3j6uj2g0yq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 Aug 2022 09:28:19 +0000 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 27Q9K2fG017092; Fri, 26 Aug 2022 09:28:18 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma03dal.us.ibm.com with ESMTP id 3j2q8aedae-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 Aug 2022 09:28:18 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27Q9SHFj5571280 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 26 Aug 2022 09:28:17 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 38D9EBE054; Fri, 26 Aug 2022 09:30:06 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F2D96BE051; Fri, 26 Aug 2022 09:30:05 +0000 (GMT) Received: from pike (unknown [9.5.12.127]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS; Fri, 26 Aug 2022 09:30:05 +0000 (GMT) From: Jiufu Guo To: Segher Boessenkool Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, linkw@gcc.gnu.org Subject: Re: [PATCH V4] rs6000: Optimize cmp on rotated 16bits constant References: <20220725132922.45470-1-guojiufu@linux.ibm.com> <20220823221854.GX25951@gate.crashing.org> <7er116gjz2.fsf@pike.rch.stglabs.ibm.com> <20220824140722.GZ25951@gate.crashing.org> <7eedx4h6a4.fsf@pike.rch.stglabs.ibm.com> <20220825123444.GD25951@gate.crashing.org> Date: Fri, 26 Aug 2022 17:28:14 +0800 In-Reply-To: <20220825123444.GD25951@gate.crashing.org> (Segher Boessenkool's message of "Thu, 25 Aug 2022 07:34:44 -0500") Message-ID: <7ey1vbxsk1.fsf@pike.rch.stglabs.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: QHyeHGKbuCBKdY43SP2PnTfmC9dztBX9 X-Proofpoint-ORIG-GUID: z_Jkw0jGj1vkghtL5jkFUljpvmnwGxcT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-26_04,2022-08-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 malwarescore=0 mlxscore=0 mlxlogscore=299 phishscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208260035 X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, Segher Boessenkool writes: > Hi! > > On Thu, Aug 25, 2022 at 08:11:31PM +0800, Jiufu Guo wrote: >> Segher Boessenkool writes: >> > You usually can split fine if you cannot create new pseudos, by reusing >> > existing registers. >> > >> > FAIL will cause an ICE: the RTL instruction does match, but will fail >> > when trying to generate machine code for it. >> > >> Previous patch is using "gen_reg_rtx (DImode)" to generate a pseudo for >> the rotated result to prevent orignal one being changed accidently. >> So, an 'assert (can_create_pseudo_p ())' would catch it in after RA. > > It sounds like you want a define_split, not a define_insn_and_split. > That is much more stomachable anyway. > Thanks for pointing out this! As you mentioned, since it is only 'combine pass' that can match the patterns, it would be better to just a define_split. While I tried to use this way, like: (define_split [(set (pc) (if_then_else (eqne (match_operand:DI 1 "gpc_reg_operand") (match_operand:DI 2 "const_int_operand")) (label_ref (match_operand 0)) (pc)))] "TARGET_POWERPC64 && num_insns_constant (operands[2], DImode) > 1 && compare_rotate_immediate_p (UINTVAL (operands[2]))" [(pc)] But this does not work. With more debugging, it seems that, "combine_split_insns/split_insns" returns correctly with sequence of three insns. But after return, only less than two insns can be handled. Just as the code comment: If we were combining three insns and the result is a simple SET with no ASM_OPERANDS that wasn't recognized, try to split it into two insns. then, that 'define_split' fail to keep the result. In the patch, for 'define_insn_and_split', it is handled as the process: In 'combine' pass, the new defined insns "rotate_on_cmpdi" is combined from three instructions; And then, in the 'split1' pass, it was split into other three insns. > Anything that creates conditional branches together with compars insns > belongs before RA, before sched1 even. > For this patch, it would run in 'split1' mostly. The good thing is 'split1' is before sched1. :-) >> To enable this splitter works after RA, we may need to reserve one >> register (clobber would be ok). Such as below: >> >> [(set (pc) >> (if_then_else (eqne (match_operand:DI 1 "gpc_reg_operand" "r") >> (match_operand:DI 2 "const_int_operand" "n")) >> (label_ref (match_operand 0 "")) >> (pc))) >> (clobber (match_scratch:DI 3 "=r")) >> (clobber (match_scratch:CCUNS 4 "=y"))] > > Yes, that is one way to do it. Another way is to reuse operand 1. A > clobber is probably better in this case though :-) Yes, a clobber would be better -:) For example: If %3 is used later, it would be not safe to change: "%3:DI!=0x8642000000000000"==>"%3:DI=%3DI<-15, %3:DI!=0x4321" > > If this is only so combine can match things, you certainly want just a > define_split, and the compare+branch in one pattern is not as bad > then. As the above comments, since I failed to use 'define_split', so in patch, 'define_insn_and_split' is used. :( BR, Jeff(Jiufu) > > > Segher