From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id F09CF3857838 for ; Mon, 28 Aug 2023 09:20:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F09CF3857838 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37S8tf84030742; Mon, 28 Aug 2023 09:20:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=fQf6JzOaQyKZbx6jHHoimAjHgb1TtJJPS4xbwL7mNV8=; b=HS8luP7qJmqnhc/h/KOlEYQ1MD7/NT3jOVbjdwOkcH0/jxH37Y61i7tKxvX/NLfwoz06 7r/YjC2I0EKxmDWF9r56p66/OyoVi4kl31kcrwJko5mV7oUl6ocAzxxzHG/su3I2jJ95 xLzw9DEMC/u7+HfzgqYzaSLhCWeiDKywxVJ4y8T8Skucg+aab9mFKZOiLc2WiIYXed4K 60yvAszrO2fjZ0d/FFHLSGOlvdGKqizjDmrh89EpO/tS5vHZ5xsAk+dneZbYVyfoQH2S huLQg9Ovh0cM2K6uR+WZ4jyFLWrODCLbn6ahUDkU1YdIf6ZvLjw13TaodSQGXAKhCxdw Xw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3sr64rtbcc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Aug 2023 09:20:26 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37S9DwpK006186; Mon, 28 Aug 2023 09:20:26 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3sr64rtbbs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Aug 2023 09:20:26 +0000 Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 37S8ujvb019193; Mon, 28 Aug 2023 09:20:24 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 3sqxe18y8t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Aug 2023 09:20:24 +0000 Received: from smtpav07.fra02v.mail.ibm.com (smtpav07.fra02v.mail.ibm.com [10.20.54.106]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 37S9KMK149414508 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 28 Aug 2023 09:20:22 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1A69D20043; Mon, 28 Aug 2023 09:20:21 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F057220040; Mon, 28 Aug 2023 09:20:18 +0000 (GMT) Received: from [9.197.250.29] (unknown [9.197.250.29]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 28 Aug 2023 09:20:18 +0000 (GMT) Message-ID: <7fbc7b02-d0ee-d221-f4bb-bc1d3e05c44c@linux.ibm.com> Date: Mon, 28 Aug 2023 17:20:17 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH-2, rs6000] Implement 32bit inline lrint [PR88558] Content-Language: en-US To: HAO CHEN GUI Cc: Segher Boessenkool , David , Peter Bergner , gcc-patches References: From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: XtAe3R2sMFGkYtlVR-Yan1HSvXZiJP2J X-Proofpoint-ORIG-GUID: FNrfeTTvoHfqqwVZJGZREdvOowZdzwTB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-28_06,2023-08-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=872 impostorscore=0 mlxscore=0 adultscore=0 spamscore=0 suspectscore=0 clxscore=1015 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308280082 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Haochen, on 2023/8/25 14:44, HAO CHEN GUI wrote: > Hi, > This patch implements 32bit inline lrint by "fctiw". It depends on > the patch1 to do SImode move from FP register on P7. > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. > > Thanks > Gui Haochen > > ChangeLog > rs6000: support 32bit inline lrint > > gcc/ > PR target/88558 > * config/rs6000/rs6000.md (lrintdi2): Remove TARGET_FPRND > from insn condition. > (lrintsi2): New insn pattern for 32bit lrint. > > gcc/testsuite/ > PR target/106769 > * gcc.target/powerpc/pr88558.h: New. > * gcc.target/powerpc/pr88558-p7.c: New. > * gcc.target/powerpc/pr88558-p8v.c: New. > > patch.diff > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index fd263e8dfe3..b36304de8c6 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -6655,10 +6655,18 @@ (define_insn "lrintdi2" > [(set (match_operand:DI 0 "gpc_reg_operand" "=d") > (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "")] > UNSPEC_FCTID))] > - "TARGET_HARD_FLOAT && TARGET_FPRND" > + "TARGET_HARD_FLOAT" > "fctid %0,%1" > [(set_attr "type" "fp")]) > > +(define_insn "lrintsi2" > + [(set (match_operand:SI 0 "gpc_reg_operand" "=d") > + (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "")] > + UNSPEC_FCTIW))] It surprises me that we have UNSPEC_FCTIW but it's unused before. :) > + "TARGET_HARD_FLOAT && TARGET_POPCNTD" > + "fctiw %0,%1" > + [(set_attr "type" "fp")]) > + > (define_insn "btrunc2" > [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") > (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] > diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c > new file mode 100644 > index 00000000000..6437c55fa61 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c > @@ -0,0 +1,10 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power7" } */ Nit: Maybe add one comment for why -fno-math-errno is needed, such as: "-fno-math-errno is required to make {i,l,ll}rint inlined". > + > +#include "pr88558.h" > + > +/* { dg-final { scan-assembler-times {\mfctid\M} 2 { target lp64 } } } */ > +/* { dg-final { scan-assembler-times {\mfctid\M} 1 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\mfctiw\M} 1 { target lp64 } } } */ > +/* { dg-final { scan-assembler-times {\mfctiw\M} 2 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\mstfiwx\M} 1 } } */ Shouldn't we also expect different expected count for stfiwx for lp64 and ilp32? 1 for lp64 and 2 for ilp32? no? > diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p8v.c b/gcc/testsuite/gcc.target/powerpc/pr88558-p8v.c > new file mode 100644 > index 00000000000..fd22123ffb6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p8v.c Nit: Maybe just name this with "-p8.c" instead of "-p8v.c". > @@ -0,0 +1,24 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target powerpc_p8vector_ok } */ > +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power8" } */ > + > +long int foo (double a) > +{ > + return __builtin_lrint (a); > +} > + > +long long bar (double a) > +{ > + return __builtin_llrint (a); > +} > + > +int baz (double a) > +{ > + return __builtin_irint (a); > +} I think you want to use #include "pr88558.h" here, wrong revision? > + > +/* { dg-final { scan-assembler-times {\mfctid\M} 2 { target lp64 } } } */ > +/* { dg-final { scan-assembler-times {\mfctid\M} 1 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\mfctiw\M} 1 { target lp64 } } } */ > +/* { dg-final { scan-assembler-times {\mfctiw\M} 2 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 1 } } */ Similar question on mfvsrwz counts (to the above stfiwx). > diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558.h b/gcc/testsuite/gcc.target/powerpc/pr88558.h > new file mode 100644 > index 00000000000..0cc0c68dd4e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr88558.h > @@ -0,0 +1,14 @@ > +long int foo (double a) > +{ > + return __builtin_lrint (a); > +} > + > +long long bar (double a) > +{ > + return __builtin_llrint (a); > +} > + > +int baz (double a) > +{ > + return __builtin_irint (a); > +} > The PR also mentioned lrintf, I think we can also add some cases for the coverage? BR, Kewen