Re: [PATCH] s390: testsuite: Fix risbg-ll-2.c

[Andreas Krebbel <krebbel@linux.ibm.com>]

On 4/30/24 10:34, Stefan Schulze Frielinghaus wrote:
> Starting with r14-2047-gd0e891406b16dc we see through subregs which
> means for f10 in risbg-ll-2.c we do not end up with rosbg_si_noshift but
> rather rosbg_di_noshift which materializes in slightly different start
> index.  This saves us an extend.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/s390/risbg-ll-2.c: Fix start offset for rosbg of
> 	f10.

Ok. Thanks!

Andreas

> ---
>  Ok for mainline?
> 
>  gcc/testsuite/gcc.target/s390/risbg-ll-2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
> index 8bf1a0ff88b..ca80602a83f 100644
> --- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
> +++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
> @@ -113,7 +113,7 @@ i32 f9 (i64 v_x, i32 v_y)
>  // ands with incompatible masks.
>  i32 f10 (i64 v_x, i32 v_y)
>  {
> -  /* { dg-final { scan-assembler "f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,32,39,0" { target { lp64 } } } } */
> +  /* { dg-final { scan-assembler "f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,0,39,0" { target { lp64 } } } } */
>    /* { dg-final { scan-assembler "f10:\n\tnilf\t%r4,4278190080\n\trosbg\t%r4,%r2,48,63,48" { target { ! lp64 } } } } */
>    i64 v_shr6 = ((ui64)v_x) >> 48;
>    i32 v_conv = (ui32)v_shr6;