From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 0EF5B3858D1E; Fri, 2 Jun 2023 04:03:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0EF5B3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353724.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35243ET3023378; Fri, 2 Jun 2023 04:03:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : references : date : in-reply-to : message-id : content-type : content-transfer-encoding : mime-version; s=pp1; bh=IsV+bEXpH88WOYNfBcXhAMnz2VhNIDeGttXgd5eu1Ck=; b=tXgbVkGMgITqHw57UfQlKXRArWhCsOESxVLG6FeT6MLY+VwtGVd7kTmOSHH0DIEGL4kq kygvYarVtNP5RIaYmX/UPHTGq7QuiumLMMGT10a4Z2aYtEXJfHwe99NfMoo5J9H7e3zO VPA3e0vv5veQSSGQot9/X8FuZq32H+ADfdIsLBsQy78SmPqQ3y/VlK7sS7TVSa4Drj1I dxOH+yQP+kfK/PyGg7/6g17lAoyLvtedKyZ8bf1VSx1eBarFQlw+DovXf3+LegTYe0J6 wcKQiMgZR475LkP9FfSVfSfynw2iqdgTMV7Vj1WpBbfwUlyMd5yJFheg6VT21wGpn0OQ Gw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qy92ag0d3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 04:03:54 +0000 Received: from m0353724.ppops.net (m0353724.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 35243rlg024262; Fri, 2 Jun 2023 04:03:53 GMT Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qy92ag0cf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 04:03:53 +0000 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3521smGR008154; Fri, 2 Jun 2023 04:03:53 GMT Received: from smtprelay02.dal12v.mail.ibm.com ([9.208.130.97]) by ppma02wdc.us.ibm.com (PPS) with ESMTPS id 3qu9g8ngtu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 04:03:53 +0000 Received: from smtpav01.wdc07v.mail.ibm.com (smtpav01.wdc07v.mail.ibm.com [10.39.53.228]) by smtprelay02.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 35243qFh36569410 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 2 Jun 2023 04:03:52 GMT Received: from smtpav01.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DFB025804B; Fri, 2 Jun 2023 04:03:51 +0000 (GMT) Received: from smtpav01.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8E54558055; Fri, 2 Jun 2023 04:03:51 +0000 (GMT) Received: from ltcden2-lp1.aus.stglabs.ibm.com (unknown [9.3.90.43]) by smtpav01.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Fri, 2 Jun 2023 04:03:51 +0000 (GMT) From: Jiufu Guo To: David Edelsohn Cc: Jiufu Guo via Gcc-patches , segher@kernel.crashing.org, linkw@gcc.gnu.org Subject: Re: ping^^: [PATCH] rs6000: Enable const_anchor for 'addi' References: <20221014031748.55813-1-guojiufu@linux.ibm.com> <7npm7rkxrr.fsf@ltcden2-lp1.aus.stglabs.ibm.com> <7ncz2zpi81.fsf@ltcden2-lp1.aus.stglabs.ibm.com> <7npm6hxl1i.fsf_-_@ltcden2-lp1.aus.stglabs.ibm.com> Date: Fri, 02 Jun 2023 12:03:48 +0800 In-Reply-To: (David Edelsohn's message of "Wed, 31 May 2023 09:40:34 -0400") Message-ID: <7nmt1iik7v.fsf@ltcden2-lp1.aus.stglabs.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Content-Type: text/plain; charset=utf-8 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 05xSyqtVFO_uNmkTEmp5jAjQ3gcvy41x X-Proofpoint-GUID: vzJqrEorLIof7dVODSlag0WAEC04fOwu Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-02_01,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 suspectscore=0 phishscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306020024 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi David, Thanks! David Edelsohn writes: > This Message Is From an External Sender=20 > This message came from outside your organization.=20 >=20=20 > On Tue, May 30, 2023 at 11:00=E2=80=AFPM Jiufu Guo wrote: > > Gentle ping... > > Jiufu Guo via Gcc-patches writes: > > > Gentle ping... > > > > Jiufu Guo via Gcc-patches writes: > > > >> Hi, > >> > >> I'm thinking that we may enable this patch for stage1, so ping it. > >> https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603530.html > >> > >> BR, > >> Jeff (Jiufu) > >> > >> Jiufu Guo writes: > >> > >>> Hi, > >>> > >>> There is a functionality as const_anchor in cse.cc. This const_anch= or > >>> supports to generate new constants through adding small gap/offsets = to > >>> existing constant. For example: > >>> > >>> void __attribute__ ((noinline)) foo (long long *a) > >>> { > >>> *a++ =3D 0x2351847027482577LL; > >>> *a++ =3D 0x2351847027482578LL; > >>> } > >>> The second constant (0x2351847027482578LL) can be compated by adding= '1' > >>> to the first constant (0x2351847027482577LL). > >>> This is profitable if more than one instructions are need to build t= he > >>> second constant. > >>> > >>> * For rs6000, we can enable this functionality, as the instruction > >>> 'addi' is just for this when gap is smaller than 0x8000. > >>> > >>> * Besides enabling TARGET_CONST_ANCHOR on rs6000, this patch also fi= xed > >>> one issue. The issue is: > >>> "gcc_assert (SCALAR_INT_MODE_P (mode))" is an requirement for functi= on > >>> "try_const_anchors".=20 > >>> > >>> * One potential side effect of this patch: > >>> Comparing with > >>> "r101=3D0x2351847027482577LL > >>> ... > >>> r201=3D0x2351847027482578LL" > >>> The new r201 will be "r201=3Dr101+1", and then r101 will live longer, > >>> and would increase pressure when allocating registers. > >>> But I feel, this would be acceptable for this const_anchor feature. > >>> > >>> * With this patch, I checked the performance change on SPEC2017, whi= le, > >>> and the performance is not aggressive, since this functionality is n= ot > >>> hit on any hot path. There are runtime wavings/noise(e.g. on > >>> povray_r/xalancbmk_r/xz_r), that are not caused by the patch. > >>> > >>> With this patch, I also checked the changes in object files (from > >>> GCC bootstrap and SPEC), the significant changes are the improvement > >>> that: "addi" vs. "2 or more insns: lis+or.."; it also exposes some > >>> other optimizations opportunities: like combine/jump2. While the > >>> code to store/load one more register is also occurring in few cases, > >>> but it does not impact overall performance. > >>> > >>> * To refine this patch, some history discussions are referenced: > >>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D33699 > >>> https://gcc.gnu.org/pipermail/gcc-patches/2009-April/260421.html > >>> https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566744.html > >>> > >>> > >>> Bootstrap and regtest pass on ppc64 and ppc64le for this patch. > >>> Is this ok for trunk? > > Hi, Jiufu > > Thanks for developing this patch and your persistence. > > The rs6000.cc part of the patch (TARGET_CONST_ANCHOR) is okay for > Stage 1. This is approved.=20 > > I don't have the authority to approve the change to cse_insn. Is the > cse_insn change a prerequisite? Will the rs6000 change break or > produce wrong code=20 > without the cse change? The second part of the patch should be posted > separately to the mailing list, with a cc for appropriate maintainers, > because most maintainers will not be following this specific thread > to approve the other part of the patch. I would extract the cse part as a seperate patch. Yes, cse part is prerequest, the bug could be exposed by rs6000 part change. BR, Jeff (Jiufu Guo) > > Thanks, David >=20=20 > >>> > >>> > >>> BR, > >>> Jeff (Jiufu) > >>> > >>> gcc/ChangeLog: > >>> > >>> * config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define. > >>> * cse.cc (cse_insn): Add guard condition. > >>> > >>> gcc/testsuite/ChangeLog: > >>> > >>> * gcc.target/powerpc/const_anchors.c: New test. > >>> * gcc.target/powerpc/try_const_anchors_ice.c: New test. > >>> > >>> --- > >>> gcc/config/rs6000/rs6000.cc | 4 ++++ > >>> gcc/cse.cc | 3 ++- > >>> .../gcc.target/powerpc/const_anchors.c | 20 ++++++++++++++++= +++ > >>> .../powerpc/try_const_anchors_ice.c | 16 +++++++++++++++ > >>> 4 files changed, 42 insertions(+), 1 deletion(-) > >>> create mode 100644 gcc/testsuite/gcc.target/powerpc/const_anchors.c > >>> create mode 100644 gcc/testsuite/gcc.target/powerpc/try_const_ancho= rs_ice.c > >>> > >>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.= cc > >>> index d2743f7bce6..80cded6dec1 100644 > >>> --- a/gcc/config/rs6000/rs6000.cc > >>> +++ b/gcc/config/rs6000/rs6000.cc > >>> @@ -1760,6 +1760,10 @@ static const struct attribute_spec rs6000_att= ribute_table[] =3D > >>>=20=20 > >>> #undef TARGET_UPDATE_IPA_FN_TARGET_INFO > >>> #define TARGET_UPDATE_IPA_FN_TARGET_INFO rs6000_update_ipa_fn_targe= t_info > >>> + > >>> +#undef TARGET_CONST_ANCHOR > >>> +#define TARGET_CONST_ANCHOR 0x8000 > >>> + > >>>=20=20 > >>>=20=20 > >>> /* Processor table. */ > >>> diff --git a/gcc/cse.cc b/gcc/cse.cc > >>> index b13afd4ba72..56542b91c1e 100644 > >>> --- a/gcc/cse.cc > >>> +++ b/gcc/cse.cc > >>> @@ -5005,7 +5005,8 @@ cse_insn (rtx_insn *insn) > >>> if (targetm.const_anchor > >>> && !src_related > >>> && src_const > >>> - && GET_CODE (src_const) =3D=3D CONST_INT) > >>> + && GET_CODE (src_const) =3D=3D CONST_INT > >>> + && SCALAR_INT_MODE_P (mode)) > >>> { > >>> src_related =3D try_const_anchors (src_const, mode); > >>> src_related_is_const_anchor =3D src_related !=3D NULL_RTX; > >>> diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/= testsuite/gcc.target/powerpc/const_anchors.c > >>> new file mode 100644 > >>> index 00000000000..39958ff9765 > >>> --- /dev/null > >>> +++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c > >>> @@ -0,0 +1,20 @@ > >>> +/* { dg-do compile { target has_arch_ppc64 } } */ > >>> +/* { dg-options "-O2" } */ > >>> + > >>> +#define C1 0x2351847027482577ULL > >>> +#define C2 0x2351847027482578ULL > >>> + > >>> +void __attribute__ ((noinline)) foo (long long *a) > >>> +{ > >>> + *a++ =3D C1; > >>> + *a++ =3D C2; > >>> +} > >>> + > >>> +void __attribute__ ((noinline)) foo1 (long long *a, long long b) > >>> +{ > >>> + *a++ =3D C1; > >>> + if (b) > >>> + *a++ =3D C2; > >>> +} > >>> + > >>> +/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */ > >>> diff --git a/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.= c b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c > >>> new file mode 100644 > >>> index 00000000000..4c8a892e803 > >>> --- /dev/null > >>> +++ b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c > >>> @@ -0,0 +1,16 @@ > >>> +/* { dg-do compile } */ > >>> +/* { dg-options "-O2" } */ > >>> + > >>> +/* __builtin_stack_restore could generates {[%1:DI]=3D0;} in BLK mo= de, > >>> + it could case ICE in try_const_anchors which only supports SCALA= R_INT. */ > >>> + > >>> +long > >>> +foo (const int val) > >>> +{ > >>> + if (val =3D=3D (0)) > >>> + return 0; > >>> + void *p =3D __builtin_stack_save (); > >>> + char c =3D val; > >>> + __builtin_stack_restore (p); > >>> + return c; > >>> +}