From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 653893858D20; Wed, 31 May 2023 03:00:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 653893858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34V1xjTt023804; Wed, 31 May 2023 03:00:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : references : date : in-reply-to : message-id : content-type : mime-version; s=pp1; bh=zDrIAzLJPhQ2dLOgGHp0QFRG3GkOZOGDBLSHlIxC5pw=; b=pzo7ssdQHmoab2kytGiTAkA72tR5TuBHXPKNle2tDS5L3OaP/6uycPKOYUCAmsewENqs Tbd38w6skLc1rwTYcB+C1VUOz/4Gimf5Ug92yykvzNFBkgXfLOEkGq6W9EpAza7N5d1C Bv+MgnkiooizKwgt2pwFIzQWmGlHMib2DFR05R7xAQslQTn6ZTd/lOWsvmrhe121l2Sc /9gO0TFwYpcQOi4YYvdzN6ZSzXt9Z+iY3EuVVPqVt666HT2GxZ5FPfPoX8HozMRhmAcL pGWmOn7Y7jMZjONUY51ZOumbZ6htALHBQXUTSv1nVz49CJR5HZabCY7Pcvrim0l3wfRb 5g== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qwjvfgtas-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 May 2023 03:00:17 +0000 Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34V2k2Dn031378; Wed, 31 May 2023 03:00:16 GMT Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qwjvfgt98-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 May 2023 03:00:16 +0000 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 34UFMc7r017380; Wed, 31 May 2023 03:00:14 GMT Received: from smtprelay07.wdc07v.mail.ibm.com ([9.208.129.116]) by ppma03dal.us.ibm.com (PPS) with ESMTPS id 3qu9g5652v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 May 2023 03:00:13 +0000 Received: from smtpav01.wdc07v.mail.ibm.com (smtpav01.wdc07v.mail.ibm.com [10.39.53.228]) by smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 34V30Clh48955760 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 31 May 2023 03:00:12 GMT Received: from smtpav01.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8AE585804B; Wed, 31 May 2023 03:00:12 +0000 (GMT) Received: from smtpav01.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 43D6C5806E; Wed, 31 May 2023 03:00:12 +0000 (GMT) Received: from ltcden2-lp1.aus.stglabs.ibm.com (unknown [9.3.90.43]) by smtpav01.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Wed, 31 May 2023 03:00:12 +0000 (GMT) From: Jiufu Guo To: Jiufu Guo via Gcc-patches Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org Subject: ping^^: [PATCH] rs6000: Enable const_anchor for 'addi' References: <20221014031748.55813-1-guojiufu@linux.ibm.com> <7npm7rkxrr.fsf@ltcden2-lp1.aus.stglabs.ibm.com> <7ncz2zpi81.fsf@ltcden2-lp1.aus.stglabs.ibm.com> Date: Wed, 31 May 2023 11:00:09 +0800 In-Reply-To: <7ncz2zpi81.fsf@ltcden2-lp1.aus.stglabs.ibm.com> (Jiufu Guo via Gcc-patches's message of "Wed, 17 May 2023 14:47:26 +0800") Message-ID: <7npm6hxl1i.fsf_-_@ltcden2-lp1.aus.stglabs.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: FioTdJCecmzCR2ilLRGQptDe7_eRLQlc X-Proofpoint-GUID: DC64fCWCjsZ1b_5nUP-QvFpSeFZjq5xG X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_18,2023-05-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 phishscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305310019 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Gentle ping... Jiufu Guo via Gcc-patches writes: > Gentle ping... > > Jiufu Guo via Gcc-patches writes: > >> Hi, >> >> I'm thinking that we may enable this patch for stage1, so ping it. >> https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603530.html >> >> BR, >> Jeff (Jiufu) >> >> Jiufu Guo writes: >> >>> Hi, >>> >>> There is a functionality as const_anchor in cse.cc. This const_anchor >>> supports to generate new constants through adding small gap/offsets to >>> existing constant. For example: >>> >>> void __attribute__ ((noinline)) foo (long long *a) >>> { >>> *a++ = 0x2351847027482577LL; >>> *a++ = 0x2351847027482578LL; >>> } >>> The second constant (0x2351847027482578LL) can be compated by adding '1' >>> to the first constant (0x2351847027482577LL). >>> This is profitable if more than one instructions are need to build the >>> second constant. >>> >>> * For rs6000, we can enable this functionality, as the instruction >>> 'addi' is just for this when gap is smaller than 0x8000. >>> >>> * Besides enabling TARGET_CONST_ANCHOR on rs6000, this patch also fixed >>> one issue. The issue is: >>> "gcc_assert (SCALAR_INT_MODE_P (mode))" is an requirement for function >>> "try_const_anchors". >>> >>> * One potential side effect of this patch: >>> Comparing with >>> "r101=0x2351847027482577LL >>> ... >>> r201=0x2351847027482578LL" >>> The new r201 will be "r201=r101+1", and then r101 will live longer, >>> and would increase pressure when allocating registers. >>> But I feel, this would be acceptable for this const_anchor feature. >>> >>> * With this patch, I checked the performance change on SPEC2017, while, >>> and the performance is not aggressive, since this functionality is not >>> hit on any hot path. There are runtime wavings/noise(e.g. on >>> povray_r/xalancbmk_r/xz_r), that are not caused by the patch. >>> >>> With this patch, I also checked the changes in object files (from >>> GCC bootstrap and SPEC), the significant changes are the improvement >>> that: "addi" vs. "2 or more insns: lis+or.."; it also exposes some >>> other optimizations opportunities: like combine/jump2. While the >>> code to store/load one more register is also occurring in few cases, >>> but it does not impact overall performance. >>> >>> * To refine this patch, some history discussions are referenced: >>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=33699 >>> https://gcc.gnu.org/pipermail/gcc-patches/2009-April/260421.html >>> https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566744.html >>> >>> >>> Bootstrap and regtest pass on ppc64 and ppc64le for this patch. >>> Is this ok for trunk? >>> >>> >>> BR, >>> Jeff (Jiufu) >>> >>> gcc/ChangeLog: >>> >>> * config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define. >>> * cse.cc (cse_insn): Add guard condition. >>> >>> gcc/testsuite/ChangeLog: >>> >>> * gcc.target/powerpc/const_anchors.c: New test. >>> * gcc.target/powerpc/try_const_anchors_ice.c: New test. >>> >>> --- >>> gcc/config/rs6000/rs6000.cc | 4 ++++ >>> gcc/cse.cc | 3 ++- >>> .../gcc.target/powerpc/const_anchors.c | 20 +++++++++++++++++++ >>> .../powerpc/try_const_anchors_ice.c | 16 +++++++++++++++ >>> 4 files changed, 42 insertions(+), 1 deletion(-) >>> create mode 100644 gcc/testsuite/gcc.target/powerpc/const_anchors.c >>> create mode 100644 gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c >>> >>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc >>> index d2743f7bce6..80cded6dec1 100644 >>> --- a/gcc/config/rs6000/rs6000.cc >>> +++ b/gcc/config/rs6000/rs6000.cc >>> @@ -1760,6 +1760,10 @@ static const struct attribute_spec rs6000_attribute_table[] = >>> >>> #undef TARGET_UPDATE_IPA_FN_TARGET_INFO >>> #define TARGET_UPDATE_IPA_FN_TARGET_INFO rs6000_update_ipa_fn_target_info >>> + >>> +#undef TARGET_CONST_ANCHOR >>> +#define TARGET_CONST_ANCHOR 0x8000 >>> + >>> >>> >>> /* Processor table. */ >>> diff --git a/gcc/cse.cc b/gcc/cse.cc >>> index b13afd4ba72..56542b91c1e 100644 >>> --- a/gcc/cse.cc >>> +++ b/gcc/cse.cc >>> @@ -5005,7 +5005,8 @@ cse_insn (rtx_insn *insn) >>> if (targetm.const_anchor >>> && !src_related >>> && src_const >>> - && GET_CODE (src_const) == CONST_INT) >>> + && GET_CODE (src_const) == CONST_INT >>> + && SCALAR_INT_MODE_P (mode)) >>> { >>> src_related = try_const_anchors (src_const, mode); >>> src_related_is_const_anchor = src_related != NULL_RTX; >>> diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/testsuite/gcc.target/powerpc/const_anchors.c >>> new file mode 100644 >>> index 00000000000..39958ff9765 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c >>> @@ -0,0 +1,20 @@ >>> +/* { dg-do compile { target has_arch_ppc64 } } */ >>> +/* { dg-options "-O2" } */ >>> + >>> +#define C1 0x2351847027482577ULL >>> +#define C2 0x2351847027482578ULL >>> + >>> +void __attribute__ ((noinline)) foo (long long *a) >>> +{ >>> + *a++ = C1; >>> + *a++ = C2; >>> +} >>> + >>> +void __attribute__ ((noinline)) foo1 (long long *a, long long b) >>> +{ >>> + *a++ = C1; >>> + if (b) >>> + *a++ = C2; >>> +} >>> + >>> +/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */ >>> diff --git a/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c >>> new file mode 100644 >>> index 00000000000..4c8a892e803 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c >>> @@ -0,0 +1,16 @@ >>> +/* { dg-do compile } */ >>> +/* { dg-options "-O2" } */ >>> + >>> +/* __builtin_stack_restore could generates {[%1:DI]=0;} in BLK mode, >>> + it could case ICE in try_const_anchors which only supports SCALAR_INT. */ >>> + >>> +long >>> +foo (const int val) >>> +{ >>> + if (val == (0)) >>> + return 0; >>> + void *p = __builtin_stack_save (); >>> + char c = val; >>> + __builtin_stack_restore (p); >>> + return c; >>> +}