From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 98A573858C2C; Tue, 4 Jul 2023 02:56:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 98A573858C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3642lUsK016700; Tue, 4 Jul 2023 02:56:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : references : date : in-reply-to : message-id : content-type : mime-version; s=pp1; bh=lLVpHkh08fbE+b2aKYH/npNWK8+Nh1nHUG0NxefmoEo=; b=qJ45l8OE5KBLaIdJMlDo3g2u/Mx2w2BLzLzWebCTsl0kizySBUihxJzLZlV8JCwbC5ft xrkirjPGN938D2dCztOp7KObkksA2qttu64fPI5hAbYCvtH0aMaY1plnYFIyiuD0MJSS 5DSTb6ofXk5NUr7dMVNPaD5vRK/csm3vPLUPXamJliBDuHBWBxabv6jzn+opHq2KVSMO exIEB+AnnAEGDPW3EGcoa7Gmo3eV0Rx/0cZEa2Gf674WoMNR/mOajv3CzGCyTAFis7jU FdHwar31X5ACLExwOWD7wr5g/uGOSBGg9PZZ9aPRbDgeXJj1ZsB4mz6R6Mi1y7USvtr7 7Q== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rmaxvr42r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Jul 2023 02:56:47 +0000 Received: from m0360083.ppops.net (m0360083.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3642m27K018344; Tue, 4 Jul 2023 02:56:46 GMT Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rmaxvr42h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Jul 2023 02:56:46 +0000 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3641fpM2029960; Tue, 4 Jul 2023 02:56:45 GMT Received: from smtprelay04.dal12v.mail.ibm.com ([9.208.130.102]) by ppma04dal.us.ibm.com (PPS) with ESMTPS id 3rjbs5mga4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Jul 2023 02:56:45 +0000 Received: from smtpav04.wdc07v.mail.ibm.com (smtpav04.wdc07v.mail.ibm.com [10.39.53.231]) by smtprelay04.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3642ui4x59834736 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Jul 2023 02:56:44 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6C3C058050; Tue, 4 Jul 2023 02:56:44 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1948258045; Tue, 4 Jul 2023 02:56:44 +0000 (GMT) Received: from ltcden2-lp1.aus.stglabs.ibm.com (unknown [9.3.90.43]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Tue, 4 Jul 2023 02:56:43 +0000 (GMT) From: Jiufu Guo To: Jiufu Guo via Gcc-patches Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org Subject: ping^^^^: [PATCH V2] rs6000: Enhance lowpart/highpart DI->SF by mtvsrws/mtvsrd References: <20230213051843.2615021-1-guojiufu@linux.ibm.com> <7n5y9jmjr6.fsf@ltcden2-lp1.aus.stglabs.ibm.com> <7nmt23pief.fsf_-_@ltcden2-lp1.aus.stglabs.ibm.com> <7n1qixyzx3.fsf_-_@ltcden2-lp1.aus.stglabs.ibm.com> Date: Tue, 04 Jul 2023 10:56:41 +0800 In-Reply-To: <7n1qixyzx3.fsf_-_@ltcden2-lp1.aus.stglabs.ibm.com> (Jiufu Guo via Gcc-patches's message of "Wed, 31 May 2023 10:53:28 +0800") Message-ID: <7nwmzgidue.fsf_-_@ltcden2-lp1.aus.stglabs.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: nI2AvGlwE3NIR8gZI9U4gHUWR1b8wawu X-Proofpoint-GUID: HXpYfizxIFfsKKXZS7nGdxlhft6rqfUA X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-03_17,2023-06-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 adultscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307040020 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, Gentle ping ... Jiufu Guo via Gcc-patches writes: > Gentle ping... > > Jiufu Guo via Gcc-patches writes: > >> Gentle ping... >> >> Jiufu Guo via Gcc-patches writes: >> >>> Hi >>> >>> I would like to ping this patch for stage1: >>> https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612168.html >>> >>> BR, >>> Jeff (Jiufu) >>> >>> Jiufu Guo writes: >>> >>>> Hi, >>>> >>>> Compare with previous version: >>>> https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609654.html >>>> This patch does not use UNSPEC for insn mtvsrws anymore. And to handle >>>> the subreg better on BE and LE, predicate "lowpart_subreg_operator" >>>> is introducted. To help combine pass to match the pattern on high32 >>>> bit of DI, shiftrt is still used. >>>> >>>> As mentioned in PR108338, on p9, we could use mtvsrws to implement >>>> the conversion from SI#0 to SF (or lowpart DI to SF). >>>> >>>> For examples: >>>> *(long long*)buff = di; >>>> float f = *(float*)(buff); >>>> We generate "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1" instead of >>>> "mtvsrws 1,3 ; xscvspdpn 1,1". >>>> >>>> This patch update this, and also enhance the bitcast from highpart >>>> DI to SF. >>>> >>>> Bootstrap and regtests pass on ppc64{,le}. >>>> Is this ok for trunk? >>>> >>>> BR, >>>> Jeff (Jiufu) >>>> >>>> PR target/108338 >>>> >>>> gcc/ChangeLog: >>>> >>>> * config/rs6000/predicates.md (lowpart_subreg_operator): New >>>> define_predicate. >>>> * config/rs6000/rs6000.md (any_rshift): New code_iterator. >>>> (movsf_from_si2): Rename to... >>>> (movsf_from_si2_): ... this. >>>> (si2sf_mtvsrws): New define_insn. >>>> >>>> gcc/testsuite/ChangeLog: >>>> >>>> * gcc.target/powerpc/pr108338.c: New test. >>>> >>>> --- >>>> gcc/config/rs6000/predicates.md | 5 +++ >>>> gcc/config/rs6000/rs6000.md | 35 ++++++++++++----- >>>> gcc/testsuite/gcc.target/powerpc/pr108338.c | 42 +++++++++++++++++++++ >>>> 3 files changed, 73 insertions(+), 9 deletions(-) >>>> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108338.c >>>> >>>> diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md >>>> index 52c65534e51..e57c9d99c6b 100644 >>>> --- a/gcc/config/rs6000/predicates.md >>>> +++ b/gcc/config/rs6000/predicates.md >>>> @@ -2064,3 +2064,8 @@ (define_predicate "macho_pic_address" >>>> else >>>> return false; >>>> }) >>>> + >>>> +(define_predicate "lowpart_subreg_operator" >>>> + (and (match_code "subreg") >>>> + (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG (op))) >>>> + == SUBREG_BYTE (op)"))) >>>> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md >>>> index 4a7812fa592..5b4a7f8d801 100644 >>>> --- a/gcc/config/rs6000/rs6000.md >>>> +++ b/gcc/config/rs6000/rs6000.md >>>> @@ -7539,6 +7539,14 @@ (define_split >>>> UNSPEC_MOVSI_GOT))] >>>> "") >>>> >>>> +(define_insn "si2sf_mtvsrws" >>>> + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") >>>> + (subreg:SF (match_operand:SI 1 "gpc_reg_operand" "r") 0))] >>>> + "TARGET_P9_VECTOR && TARGET_XSCVSPDPN" >>>> + "mtvsrws %x0,%1\n\txscvspdpn %x0,%x0" >>>> + [(set_attr "type" "mfvsr") >>>> + (set_attr "length" "8")]) >>>> + >>>> ;; MR LA >>>> ;; LWZ LFIWZX LXSIWZX >>>> ;; STW STFIWX STXSIWX >>>> @@ -8203,10 +8211,18 @@ (define_insn_and_split "movsf_from_si" >>>> rtx op2 = operands[2]; >>>> rtx op1_di = gen_rtx_REG (DImode, REGNO (op1)); >>>> >>>> - /* Move SF value to upper 32-bits for xscvspdpn. */ >>>> - emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); >>>> - emit_insn (gen_p8_mtvsrd_sf (op0, op2)); >>>> - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); >>>> + if (TARGET_P9_VECTOR) >>>> + { >>>> + emit_insn (gen_si2sf_mtvsrws (op0, gen_lowpart (SImode, op1_di))); >>>> + } >>>> + else >>>> + { >>>> + /* Move SF value to upper 32-bits for xscvspdpn. */ >>>> + emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); >>>> + emit_insn (gen_p8_mtvsrd_sf (op0, op2)); >>>> + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); >>>> + } >>>> + >>>> DONE; >>>> } >>>> [(set_attr "length" >>>> @@ -8219,18 +8235,19 @@ (define_insn_and_split "movsf_from_si" >>>> "*, *, p9v, p8v, *, *, >>>> p8v, p8v, p8v, *")]) >>>> >>>> +(define_code_iterator any_rshift [ashiftrt lshiftrt]) >>>> + >>>> ;; For extracting high part element from DImode register like: >>>> ;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} >>>> ;; split it before reload with "and mask" to avoid generating shift right >>>> ;; 32 bit then shift left 32 bit. >>>> -(define_insn_and_split "movsf_from_si2" >>>> +(define_insn_and_split "movsf_from_si2_" >>>> [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") >>>> (unspec:SF >>>> - [(subreg:SI >>>> - (ashiftrt:DI >>>> + [(match_operator:SI 3 "lowpart_subreg_operator" >>>> + [(any_rshift:DI >>>> (match_operand:DI 1 "input_operand" "r") >>>> - (const_int 32)) >>>> - 0)] >>>> + (const_int 32))])] >>>> UNSPEC_SF_FROM_SI)) >>>> (clobber (match_scratch:DI 2 "=r"))] >>>> "TARGET_NO_SF_SUBREG" >>>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c >>>> new file mode 100644 >>>> index 00000000000..2438dc13f41 >>>> --- /dev/null >>>> +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c >>>> @@ -0,0 +1,42 @@ >>>> +// { dg-do run } >>>> +// { dg-options "-O2 -save-temps" } >>>> + >>>> +float __attribute__ ((noipa)) sf_from_di_off0 (long long l) >>>> +{ >>>> + char buff[16]; >>>> + *(long long*)buff = l; >>>> + float f = *(float*)(buff); >>>> + return f; >>>> +} >>>> + >>>> +float __attribute__ ((noipa)) sf_from_di_off4 (long long l) >>>> +{ >>>> + char buff[16]; >>>> + *(long long*)buff = l; >>>> + float f = *(float*)(buff + 4); >>>> + return f; >>>> +} >>>> + >>>> +/* Under lp64, 'l' is in one DI reg, then check sub DI to SF. */ >>>> +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */ >>>> +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 2 { target { lp64 && has_arch_pwr8 } } } } */ >>>> + >>>> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 2 { target { lp64 && { has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */ >>>> +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr9 } } } } */ >>>> +/* { dg-final { scan-assembler-times {\mmtvsrws\M} 1 { target { lp64 && has_arch_pwr9 } } } } */ >>>> + >>>> +union di_sf_sf >>>> +{ >>>> + struct {float f1; float f2;}; >>>> + long long l; >>>> +}; >>>> + >>>> +int main() >>>> +{ >>>> + union di_sf_sf v; >>>> + v.f1 = 1.0f; >>>> + v.f2 = 2.0f; >>>> + if (sf_from_di_off0 (v.l) != 1.0f || sf_from_di_off4 (v.l) != 2.0f ) >>>> + __builtin_abort (); >>>> + return 0; >>>> +}