From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 7C9A43858C83 for ; Tue, 8 Mar 2022 11:25:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7C9A43858C83 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 2289tKkK013797; Tue, 8 Mar 2022 11:25:32 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3enxs00u7e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Mar 2022 11:25:31 +0000 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 228BNcIh026774; Tue, 8 Mar 2022 11:25:31 GMT Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 3enxs00u72-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Mar 2022 11:25:31 +0000 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 228BCVks022065; Tue, 8 Mar 2022 11:25:29 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma02wdc.us.ibm.com with ESMTP id 3ekyg9cf84-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Mar 2022 11:25:29 +0000 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 228BPTGJ14680476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 8 Mar 2022 11:25:29 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3FD58112064; Tue, 8 Mar 2022 11:25:29 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C9CCA112061; Tue, 8 Mar 2022 11:25:28 +0000 (GMT) Received: from perkins (unknown [9.3.90.38]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTPS; Tue, 8 Mar 2022 11:25:28 +0000 (GMT) From: Jiufu Guo To: Segher Boessenkool Cc: Richard Biener , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, jlaw@tachyum.com, wschmidt@linux.ibm.com Subject: Re: [PATCH] Check if loading const from mem is faster References: <20220222065313.2040127-1-guojiufu@linux.ibm.com> <70r5oq10-988r-3rns-356-o3s79o292nn0@fhfr.qr> <1d471fba-a966-3e90-92ce-ae4707fe53b6@linux.ibm.com> <20220223212749.GI614@gate.crashing.org> <20220228164511.GB614@gate.crashing.org> <7p35k1u4pi.fsf@linux.ibm.com> <20220302202416.GG614@gate.crashing.org> <7pilsvqref.fsf@linux.ibm.com> Date: Tue, 08 Mar 2022 19:25:26 +0800 In-Reply-To: <7pilsvqref.fsf@linux.ibm.com> (Jiufu Guo's message of "Thu, 03 Mar 2022 18:09:12 +0800") Message-ID: <7pcziwy9cp.fsf@linux.ibm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: EQbgMpW27QqaKzqJiHqo6M3EaTaLIEbb X-Proofpoint-ORIG-GUID: LotMIQooFy7fTJXfYP_FHPpnsoWi8Np8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-08_03,2022-03-04_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 bulkscore=0 mlxlogscore=982 clxscore=1015 adultscore=0 spamscore=0 suspectscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203080059 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Mar 2022 11:25:35 -0000 Jiufu Guo writes: Hi! > Hi Sehger, > > Segher Boessenkool writes: > >> On Tue, Mar 01, 2022 at 10:28:57PM +0800, Jiufu Guo wrote: >>> Segher Boessenkool writes: >>> > No. insn_cost is only for correct, existing instructions, not for >>> > made-up nonsense. I created insn_cost precisely to get away from that >>> > aspect of rtx_cost (and some other issues, like, it is incredibly hard >>> > and cumbersome to write a correct rtx_cost). >>> >>> Thanks! The implementations of hook insn_cost are align with this >>> design, they are checking insn's attributes and COSTS_N_INSNS. >>> >>> One question on the speciall case: >>> For instruction: "r119:DI=0x100803004101001" >>> Would we treat it as valid instruction? >> >> Currently we do, alternative 6 in *movdi_internal64: we allow any r<-n. >> This is costed as 5 insns (cost=20). >> >> It generally is better to split things into patterns close to the >> eventual machine isntructions as early as possible: all the more generic >> optimisations can take advantage of that then. > Get it! >> >>> A patch, which is attached the end of this mail, accepts >>> "r119:DI=0x100803004101001" as input of insn_cost. >>> In this patch, >>> - A tmp instruction is generated via make_insn_raw. >>> - A few calls to rtx_cost (in cse_insn) is replaced by insn_cost. >>> - In hook of insn_cost, checking the special 'constant' instruction. >>> Are these make sense? >> >> I'll review that patch inline. I drafted a new patch that replace rtx_cost with insn_cost for cse.cc. Different from the previous partial patch, this patch replaces all usage of rtx_cost. It may be better/aggressive than previous one. With this patch, bootstrap pass. >From regtest, only output of fusion-p10-ldcmpi.c is changed, and the change seems as expected. BR, Jiufu diff --git a/gcc/cse.cc b/gcc/cse.cc index a18b599d324..e623ad298db 100644 --- a/gcc/cse.cc +++ b/gcc/cse.cc @@ -262,6 +262,9 @@ static struct qty_table_elem *qty_table; static rtx_insn *this_insn; static bool optimize_this_for_speed_p; +/* Used for insn_cost. */ +static rtx_insn *estimate_insn; + /* Index by register number, gives the number of the next (or previous) register in the chain of registers sharing the same value. @@ -445,7 +448,7 @@ struct table_elt /* Compute cost of X, as stored in the `cost' field of a table_elt. Fixed hard registers and pointers into the frame are the cheapest with a cost of 0. Next come pseudos with a cost of one and other hard registers with - a cost of 2. Aside from these special cases, call `rtx_cost'. */ + a cost of 2. Aside from these special cases, call `insn_cost'. */ #define CHEAP_REGNO(N) \ (REGNO_PTR_FRAME_P (N) \ @@ -698,18 +701,33 @@ preferable (int cost_a, int regcost_a, int cost_b, int regcost_b) from COST macro to keep it simple. */ static int -notreg_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno) +notreg_cost (rtx x, machine_mode mode, enum rtx_code /*outer*/, int /*opno*/) { scalar_int_mode int_mode, inner_mode; - return ((GET_CODE (x) == SUBREG - && REG_P (SUBREG_REG (x)) - && is_int_mode (mode, &int_mode) - && is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode) - && GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode) - && subreg_lowpart_p (x) - && TRULY_NOOP_TRUNCATION_MODES_P (int_mode, inner_mode)) - ? 0 - : rtx_cost (x, mode, outer, opno, optimize_this_for_speed_p) * 2); + if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) + && is_int_mode (mode, &int_mode) + && is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode) + && GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode) + && subreg_lowpart_p (x) + && TRULY_NOOP_TRUNCATION_MODES_P (int_mode, inner_mode)) + return 0; + + if (estimate_insn == NULL) + { + estimate_insn = make_insn_raw ( + gen_rtx_SET (gen_rtx_REG (mode, LAST_VIRTUAL_REGISTER + 1), x)); + SET_PREV_INSN (estimate_insn) = NULL_RTX; + SET_NEXT_INSN (estimate_insn) = NULL_RTX; + INSN_LOCATION (estimate_insn) = 0; + } + else + { + /* Update for new context. */ + INSN_CODE (estimate_insn) = -1; + PUT_MODE (SET_DEST (PATTERN (estimate_insn)), mode); + SET_SRC (PATTERN (estimate_insn)) = x; + } + return insn_cost (estimate_insn, optimize_this_for_speed_p); } @@ -6667,6 +6685,7 @@ cse_main (rtx_insn *f ATTRIBUTE_UNUSED, int nregs) init_recog (); init_alias_analysis (); + estimate_insn = NULL; reg_eqv_table = XNEWVEC (struct reg_eqv_elem, nregs);