From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19891 invoked by alias); 20 Sep 2018 14:55:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 19877 invoked by uid 89); 20 Sep 2018 14:55:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1527, H*u:6.1, H*UA:6.1 X-HELO: huawei.com Received: from szxga05-in.huawei.com (HELO huawei.com) (45.249.212.191) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 20 Sep 2018 14:55:13 +0000 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 2C9AC89D6DE63; Thu, 20 Sep 2018 22:55:06 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.399.0; Thu, 20 Sep 2018 22:54:58 +0800 Subject: Re: [PATCH v4] [aarch64] Add HiSilicon tsv110 CPU support To: James Greenhalgh References: <1537350832-11076-1-git-send-email-zhangshaokun@hisilicon.com> <20180920142235.GA31720@arm.com> CC: "gcc-patches@gcc.gnu.org" , "kyrylo.tkachov@foss.arm.com" , Marcus Shawcroft , Richard Earnshaw , "zbo.zhou@hisilicon.com" , From: Zhangshaokun Message-ID: <80f8c297-5e5e-c760-90e7-5ea2ec84634f@hisilicon.com> Date: Thu, 20 Sep 2018 15:13:00 -0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <20180920142235.GA31720@arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2018-09/txt/msg01158.txt.bz2 Hi James, On 2018/9/20 22:22, James Greenhalgh wrote: > On Wed, Sep 19, 2018 at 04:53:52AM -0500, Shaokun Zhang wrote: >> This patch adds HiSilicon's an mcpu: tsv110, which supports v8_4A. >> It has been tested on aarch64 and no regressions from this patch. > > This patch is OK for Trunk. > > Do you need someone to commit it on your behalf? > Sure, it is great. Thanks in advance, Shaokun > Thanks, > James > >> >> --- >> gcc/ChangeLog | 9 +++ >> gcc/config/aarch64/aarch64-cores.def | 3 + >> gcc/config/aarch64/aarch64-cost-tables.h | 104 +++++++++++++++++++++++++++++++ >> gcc/config/aarch64/aarch64-tune.md | 2 +- >> gcc/config/aarch64/aarch64.c | 82 ++++++++++++++++++++++++ >> gcc/doc/invoke.texi | 2 +- >> 6 files changed, 200 insertions(+), 2 deletions(-) >> >> diff --git a/gcc/ChangeLog b/gcc/ChangeLog >> index 69e2e14..a040daa 100644 >> --- a/gcc/ChangeLog >> +++ b/gcc/ChangeLog >> @@ -1,3 +1,12 @@ >> +2018-09-19 Shaokun Zhang >> + Bo Zhou >> + >> + * config/aarch64/aarch64-cores.def (tsv110): New CPU. >> + * config/aarch64/aarch64-tune.md: Regenerated. >> + * doc/invoke.texi (AArch64 Options/-mtune): Add "tsv110". >> + * config/aarch64/aarch64.c (tsv110_tunings): New tuning table. >> + * config/aarch64/aarch64-cost-tables.h: Add "tsv110" extra costs. >> + >> 2018-09-18 Marek Polacek >> >> P1064R0 - Allowing Virtual Function Calls in Constant Expressions > > > . >