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Subject: Re: [pushed] [PATCH v4 1/2] LoongArch: Define ISA versions
From: Xi Ruoyao <xry111@xry111.site>
To: Lulu Cheng <chenglulu@loongson.cn>, Yang Yujie <yangyujie@loongson.cn>, 
	gcc-patches@gcc.gnu.org
Cc: xuchenghua@loongson.cn
Date: Tue, 07 May 2024 17:07:01 +0800
In-Reply-To: <88e6a608-3581-81da-cf72-95f57ebe224d@loongson.cn>
References: <20240423024248.243759-1-yangyujie@loongson.cn>
	 <88e6a608-3581-81da-cf72-95f57ebe224d@loongson.cn>
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Hmm, after this change the default (-march=3Dla64v1.0) is enabling LSX:

$ echo "int dummy;" | cc -c -v |& tail -n1
COLLECT_GCC_OPTIONS=3D'-c' '-v' '-mabi=3Dlp64d' '-march=3Dla64v1.0' '-mfpu=
=3D64'
'-msimd=3Dlsx' '-mcmodel=3Dnormal' '-mtune=3Dgeneric'

Is this expected or there's something wrong?

On Tue, 2024-04-23 at 11:31 +0800, Lulu Cheng wrote:
> Pushed to r14-10083.
>=20
> =E5=9C=A8 2024/4/23 =E4=B8=8A=E5=8D=8810:42, Yang Yujie =E5=86=99=E9=81=
=93:
> > These ISA versions are defined as -march=3D parameters and
> > are recommended for building binaries for distribution.
> >=20
> > Detailed description of these definitions can be found at
> > https://github.com/loongson/la-toolchain-conventions, which
> > the LoongArch GCC port aims to conform to.
> >=20
> > gcc/ChangeLog:
> >=20
> > 	* config.gcc: Make la64v1.0 the default ISA preset of the
> > lp64d ABI.
> > 	* config/loongarch/genopts/loongarch-strings: Define
> > la64v1.0, la64v1.1.
> > 	* config/loongarch/genopts/loongarch.opt.in: Likewise.
> > 	* config/loongarch/loongarch-c.cc
> > (LARCH_CPP_SET_PROCESSOR): Likewise.
> > 	(loongarch_cpu_cpp_builtins): Likewise.
> > 	* config/loongarch/loongarch-cpu.cc (get_native_prid):
> > Likewise.
> > 	(fill_native_cpu_config): Likewise.
> > 	* config/loongarch/loongarch-def.cc (array_tune): Likewise.
> > 	* config/loongarch/loongarch-def.h: Likewise.
> > 	* config/loongarch/loongarch-driver.cc (driver_set_m_parm):
> > Likewise.
> > 	(driver_get_normalized_m_opts): Likewise.
> > 	* config/loongarch/loongarch-opts.cc
> > (default_tune_for_arch): Likewise.
> > 	(TUNE_FOR_ARCH): Likewise.
> > 	(arch_str): Likewise.
> > 	(loongarch_target_option_override): Likewise.
> > 	* config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464):
> > Likewise.
> > 	(TARGET_uARCH_LA664): Likewise.
> > 	* config/loongarch/loongarch-str.h (STR_CPU_ABI_DEFAULT):
> > Likewise.
> > 	(STR_ARCH_ABI_DEFAULT): Likewise.
> > 	(STR_TUNE_GENERIC): Likewise.
> > 	(STR_ARCH_LA64V1_0): Likewise.
> > 	(STR_ARCH_LA64V1_1): Likewise.
> > 	* config/loongarch/loongarch.cc
> > (loongarch_cpu_sched_reassociation_width): Likewise.
> > 	(loongarch_asm_code_end): Likewise.
> > 	* config/loongarch/loongarch.opt: Likewise.
> > 	* doc/invoke.texi: Likewise.
> > ---
> > =C2=A0 gcc/config.gcc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 34 ++++--=
--
> > =C2=A0 .../loongarch/genopts/loongarch-strings=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 |=C2=A0 5 +-
> > =C2=A0 gcc/config/loongarch/genopts/loongarch.opt.in | 43 ++++++++--
> > =C2=A0 gcc/config/loongarch/loongarch-c.cc=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 37 +++------
> > =C2=A0 gcc/config/loongarch/loongarch-cpu.cc=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 | 35 ++++----
> > =C2=A0 gcc/config/loongarch/loongarch-def.cc=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 | 83 +++++++++++++--
> > ----
> > =C2=A0 gcc/config/loongarch/loongarch-def.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 37 ++++++---
> > =C2=A0 gcc/config/loongarch/loongarch-driver.cc=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 |=C2=A0 8 +-
> > =C2=A0 gcc/config/loongarch/loongarch-opts.cc=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 | 66 +++++++++++----
> > =C2=A0 gcc/config/loongarch/loongarch-opts.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 4 +-
> > =C2=A0 gcc/config/loongarch/loongarch-str.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 5 +-
> > =C2=A0 gcc/config/loongarch/loongarch.cc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 11 +--
> > =C2=A0 gcc/config/loongarch/loongarch.opt=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 43 ++++++++--
> > =C2=A0 gcc/doc/invoke.texi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 57 ++++++++-----
> > =C2=A0 14 files changed, 300 insertions(+), 168 deletions(-)
> >=20
> > diff --git a/gcc/config.gcc b/gcc/config.gcc
> > index 5df3c52f8e9..929695c25ab 100644
> > --- a/gcc/config.gcc
> > +++ b/gcc/config.gcc
> > @@ -5072,7 +5072,7 @@ case "${target}" in
> > =C2=A0=20
> > =C2=A0=C2=A0		# Perform initial sanity checks on --with-*
> > options.
> > =C2=A0=C2=A0		case ${with_arch} in
> > -		"" | abi-default | loongarch64 | la[46]64) ;; # OK,
> > append here.
> > +		"" | la64v1.[01] | abi-default | loongarch64 |
> > la[46]64) ;; # OK, append here.
> > =C2=A0=C2=A0		native)
> > =C2=A0=C2=A0			if test x${host} !=3D x${target}; then
> > =C2=A0=C2=A0				echo "--with-arch=3Dnative is illegal
> > for cross-compiler." 1>&2
> > @@ -5119,10 +5119,18 @@ case "${target}" in
> > =C2=A0=20
> > =C2=A0=C2=A0		# Infer ISA-related default options from the ABI:
> > pass 1
> > =C2=A0=C2=A0		case ${abi_base}/${abi_ext} in
> > -		lp64*/base)
> > +		lp64d/base)
> > =C2=A0=C2=A0			# architectures that support lp64* ABI
> > -			arch_pattern=3D"native|abi-
> > default|loongarch64|la[46]64"
> > -			# default architecture for lp64* ABI
> > +			arch_pattern=3D"native|abi-
> > default|la64v1.[01]|loongarch64|la[46]64"
> > +
> > +			# default architecture for lp64d ABI
> > +			arch_default=3D"la64v1.0"
> > +			;;
> > +		lp64[fs]/base)
> > +			# architectures that support lp64* ABI
> > +			arch_pattern=3D"native|abi-
> > default|la64v1.[01]|loongarch64|la[46]64"
> > +
> > +			# default architecture for lp64[fs] ABI
> > =C2=A0=C2=A0			arch_default=3D"abi-default"
> > =C2=A0=C2=A0			;;
> > =C2=A0=C2=A0		*)
> > @@ -5194,15 +5202,7 @@ case "${target}" in
> > =C2=A0=20
> > =C2=A0=20
> > =C2=A0=C2=A0		# Check default with_tune configuration using
> > with_arch.
> > -		case ${with_arch} in
> > -		loongarch64)
> > -			tune_pattern=3D"native|abi-
> > default|loongarch64|la[46]64"
> > -			;;
> > -		*)
> > -			# By default, $with_tune =3D=3D $with_arch
> > -			tune_pattern=3D"*"
> > -			;;
> > -		esac
> > +		tune_pattern=3D"native|generic|loongarch64|la[46]64"
> > =C2=A0=20
> > =C2=A0=C2=A0		case ${with_tune} in
> > =C2=A0=C2=A0		"") ;; # OK
> > @@ -5252,7 +5252,7 @@ case "${target}" in
> > =C2=A0=C2=A0					# Fixed: use the default
> > gcc configuration for all multilib
> > =C2=A0=C2=A0					# builds by default.
> > =C2=A0=C2=A0					with_multilib_default=3D"" ;;
> > -
> > 				arch,native|arch,loongarch64|arch,la[46]64) # OK, append here.
> > +				arch,native|arch,la64v1.[01]|arch,l
> > oongarch64|arch,la[46]64) # OK, append here.
> > =C2=A0=C2=A0					with_multilib_default=3D"/mar
> > ch=3D${component}" ;;
> > =C2=A0=C2=A0				arch,*)
> > =C2=A0=C2=A0					with_multilib_default=3D"/mar
> > ch=3Dabi-default"
> > @@ -5352,7 +5352,7 @@ case "${target}" in
> > =C2=A0=C2=A0				if test x${parse_state} =3D x"arch";
> > then
> > =C2=A0=C2=A0					# -march option
> > =C2=A0=C2=A0					case ${component} in
> > -					native | abi-default |
> > loongarch64 | la[46]64) # OK, append here.
> > +					native | abi-default |
> > la64v1.[01] | loongarch64 | la[46]64) # OK, append here.
> > =C2=A0=C2=A0						# Append -march
> > spec for each multilib variant.
> > =C2=A0=C2=A0						loongarch_multilib_
> > list_make=3D"${loongarch_multilib_list_make}/march=3D${component}"
> > =C2=A0=C2=A0						parse_state=3D"opts"
> > @@ -5925,7 +5925,7 @@ case ${target} in
> > =C2=A0=C2=A0		# See macro definitions from loongarch-opts.h and
> > loongarch-cpu.h.
> > =C2=A0=20
> > =C2=A0=C2=A0		# Architecture
> > -		tm_defines=3D"${tm_defines}
> > DEFAULT_CPU_ARCH=3DCPU_$(echo ${with_arch} | tr a-z- A-Z_)"
> > +		tm_defines=3D"${tm_defines}
> > DEFAULT_CPU_ARCH=3DARCH_$(echo ${with_arch} | tr a-z.- A-Z__)"
> > =C2=A0=20
> > =C2=A0=C2=A0		# Base ABI type
> > =C2=A0=C2=A0		tm_defines=3D"${tm_defines}
> > DEFAULT_ABI_BASE=3DABI_BASE_$(echo ${abi_base} | tr a-z- A-Z_)"
> > @@ -5937,7 +5937,7 @@ case ${target} in
> > =C2=A0=20
> > =C2=A0=C2=A0		# Microarchitecture
> > =C2=A0=C2=A0		if test x${with_tune} !=3D x; then
> > -		=C2=A0 tm_defines=3D"${tm_defines}
> > DEFAULT_CPU_TUNE=3DCPU_$(echo ${with_tune} | tr a-z- A-Z_)"
> > +		=C2=A0 tm_defines=3D"${tm_defines}
> > DEFAULT_CPU_TUNE=3DTUNE_$(echo ${with_tune} | tr a-z.- A-Z__)"
> > =C2=A0=C2=A0		fi
> > =C2=A0=20
> > =C2=A0=C2=A0		# FPU adjustment
> > diff --git a/gcc/config/loongarch/genopts/loongarch-strings
> > b/gcc/config/loongarch/genopts/loongarch-strings
> > index e434a89c9ee..e9ebd254bfa 100644
> > --- a/gcc/config/loongarch/genopts/loongarch-strings
> > +++ b/gcc/config/loongarch/genopts/loongarch-strings
> > @@ -23,10 +23,13 @@ OPTSTR_ARCH	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 arch
> > =C2=A0 OPTSTR_TUNE	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tune
> > =C2=A0=20
> > =C2=A0 STR_CPU_NATIVE	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 native
> > -STR_CPU_ABI_DEFAULT=C2=A0=C2=A0 abi-default
> > +STR_ARCH_ABI_DEFAULT=C2=A0 abi-default
> > +STR_TUNE_GENERIC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 generic
> > =C2=A0 STR_CPU_LOONGARCH64=C2=A0=C2=A0 loongarch64
> > =C2=A0 STR_CPU_LA464	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 la464
> > =C2=A0 STR_CPU_LA664	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 la664
> > +STR_ARCH_LA64V1_0=C2=A0=C2=A0=C2=A0=C2=A0 la64v1.0
> > +STR_ARCH_LA64V1_1=C2=A0=C2=A0=C2=A0=C2=A0 la64v1.1
> > =C2=A0=20
> > =C2=A0 # Base architecture
> > =C2=A0 STR_ISA_BASE_LA64 la64
> > diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in
> > b/gcc/config/loongarch/genopts/loongarch.opt.in
> > index 50ea47a161f..d00950cb4f4 100644
> > --- a/gcc/config/loongarch/genopts/loongarch.opt.in
> > +++ b/gcc/config/loongarch/genopts/loongarch.opt.in
> > @@ -95,30 +95,55 @@ Enable LoongArch Advanced SIMD Extension (LASX,
> > 256-bit).
> > =C2=A0=20
> > =C2=A0 ;; Base target models (implies ISA & tune parameters)
> > =C2=A0 Enum
> > -Name(cpu_type) Type(int)
> > -LoongArch CPU types:
> > +Name(arch_type) Type(int)
> > +LoongArch ARCH presets:
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(@@STR_CPU_NATIVE@@) Value(CPU_NATIVE)
> > +Enum(arch_type) String(@@STR_CPU_NATIVE@@) Value(ARCH_NATIVE)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(@@STR_CPU_ABI_DEFAULT@@)
> > Value(CPU_ABI_DEFAULT)
> > +Enum(arch_type) String(@@STR_ARCH_ABI_DEFAULT@@)
> > Value(ARCH_ABI_DEFAULT)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@)
> > Value(CPU_LOONGARCH64)
> > +Enum(arch_type) String(@@STR_CPU_LOONGARCH64@@)
> > Value(ARCH_LOONGARCH64)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
> > +Enum(arch_type) String(@@STR_CPU_LA464@@) Value(ARCH_LA464)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(@@STR_CPU_LA664@@) Value(CPU_LA664)
> > +Enum(arch_type) String(@@STR_CPU_LA664@@) Value(ARCH_LA664)
> > +
> > +EnumValue
> > +Enum(arch_type) String(@@STR_ARCH_LA64V1_0@@) Value(ARCH_LA64V1_0)
> > +
> > +EnumValue
> > +Enum(arch_type) String(@@STR_ARCH_LA64V1_1@@) Value(ARCH_LA64V1_1)
> > =C2=A0=20
> > =C2=A0 m@@OPTSTR_ARCH@@=3D
> > -Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch)
> > Init(M_OPT_UNSET) Save
> > +Target RejectNegative Joined Enum(arch_type) Var(la_opt_cpu_arch)
> > Init(M_OPT_UNSET) Save
> > =C2=A0 -m@@OPTSTR_ARCH@@=3DPROCESSOR	Generate code for the given
> > PROCESSOR ISA.
> > =C2=A0=20
> > +Enum
> > +Name(tune_type) Type(int)
> > +LoongArch TUNE presets:
> > +
> > +EnumValue
> > +Enum(tune_type) String(@@STR_CPU_NATIVE@@) Value(TUNE_NATIVE)
> > +
> > +EnumValue
> > +Enum(tune_type) String(@@STR_TUNE_GENERIC@@) Value(TUNE_GENERIC)
> > +
> > +EnumValue
> > +Enum(tune_type) String(@@STR_CPU_LOONGARCH64@@)
> > Value(TUNE_LOONGARCH64)
> > +
> > +EnumValue
> > +Enum(tune_type) String(@@STR_CPU_LA464@@) Value(TUNE_LA464)
> > +
> > +EnumValue
> > +Enum(tune_type) String(@@STR_CPU_LA664@@) Value(TUNE_LA664)
> > +
> > =C2=A0 m@@OPTSTR_TUNE@@=3D
> > -Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune)
> > Init(M_OPT_UNSET) Save
> > +Target RejectNegative Joined Enum(tune_type) Var(la_opt_cpu_tune)
> > Init(M_OPT_UNSET) Save
> > =C2=A0 -m@@OPTSTR_TUNE@@=3DPROCESSOR	Generate optimized code for
> > PROCESSOR.
> > =C2=A0=20
> > =C2=A0=20
> > diff --git a/gcc/config/loongarch/loongarch-c.cc
> > b/gcc/config/loongarch/loongarch-c.cc
> > index 4d88c1729ff..c1eab28db4b 100644
> > --- a/gcc/config/loongarch/loongarch-c.cc
> > +++ b/gcc/config/loongarch/loongarch-c.cc
> > @@ -31,29 +31,6 @@ along with GCC; see the file COPYING3.=C2=A0 If not
> > see
> > =C2=A0 #define builtin_define(TXT) cpp_define (pfile, TXT)
> > =C2=A0 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
> > =C2=A0=20
> > -/* Define preprocessor macros for the -march and -mtune options.
> > -=C2=A0=C2=A0 PREFIX is either _LOONGARCH_ARCH or _LOONGARCH_TUNE, INFO=
 is
> > -=C2=A0=C2=A0 the selected processor.=C2=A0 If INFO's canonical name is=
 "foo",
> > -=C2=A0=C2=A0 define PREFIX to be "foo", and define an additional macro
> > -=C2=A0=C2=A0 PREFIX_FOO.=C2=A0 */
> > -#define LARCH_CPP_SET_PROCESSOR(PREFIX,
> > CPU_TYPE)			\
> > -=C2=A0
> > do									\
> > -=C2=A0=C2=A0=C2=A0
> > {									\
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 char *macro,
> > *p;							\
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int cpu_type =3D
> > (CPU_TYPE);					\
> > -
> > 									\
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 macro =3D concat ((PREFIX),
> > "_",					\
> > -		=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 loongarch_cpu_strings[cpu_type],
> > NULL);		\
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for (p =3D macro; *p !=3D 0;
> > p++)					\
> > -	*p =3D TOUPPER
> > (*p);						\
> > -
> > 									\
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 builtin_define
> > (macro);						\
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 builtin_define_with_value
> > ((PREFIX),				\
> > -				 loongarch_cpu_strings[cpu_type],
> > 1);	\
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 free
> > (macro);							\
> > -=C2=A0=C2=A0=C2=A0
> > }									\
> > -=C2=A0 while (0)
> > -
> > =C2=A0 void
> > =C2=A0 loongarch_cpu_cpp_builtins (cpp_reader *pfile)
> > =C2=A0 {
> > @@ -61,11 +38,17 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
> > =C2=A0=C2=A0=C2=A0 builtin_assert ("cpu=3Dloongarch");
> > =C2=A0=C2=A0=C2=A0 builtin_define ("__loongarch__");
> > =C2=A0=20
> > -=C2=A0 LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_ARCH", la_target.cpu_arch)=
;
> > -=C2=A0 LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_TUNE", la_target.cpu_tune)=
;
> > +=C2=A0 builtin_define_with_value ("__loongarch_arch",
> > +			=C2=A0=C2=A0=C2=A0=C2=A0
> > loongarch_arch_strings[la_target.cpu_arch], 1);
> > +
> > +=C2=A0 builtin_define_with_value ("__loongarch_tune",
> > +			=C2=A0=C2=A0=C2=A0=C2=A0
> > loongarch_tune_strings[la_target.cpu_tune], 1);
> > +
> > +=C2=A0 builtin_define_with_value ("_LOONGARCH_ARCH",
> > +			=C2=A0=C2=A0=C2=A0=C2=A0
> > loongarch_arch_strings[la_target.cpu_arch], 1);
> > =C2=A0=20
> > -=C2=A0 LARCH_CPP_SET_PROCESSOR ("__loongarch_arch", la_target.cpu_arch=
);
> > -=C2=A0 LARCH_CPP_SET_PROCESSOR ("__loongarch_tune", la_target.cpu_tune=
);
> > +=C2=A0 builtin_define_with_value ("_LOONGARCH_TUNE",
> > +			=C2=A0=C2=A0=C2=A0=C2=A0
> > loongarch_tune_strings[la_target.cpu_tune], 1);
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 /* Base architecture / ABI.=C2=A0 */
> > =C2=A0=C2=A0=C2=A0 if (TARGET_64BIT)
> > diff --git a/gcc/config/loongarch/loongarch-cpu.cc
> > b/gcc/config/loongarch/loongarch-cpu.cc
> > index 97ac5fed9d8..80e4494ba19 100644
> > --- a/gcc/config/loongarch/loongarch-cpu.cc
> > +++ b/gcc/config/loongarch/loongarch-cpu.cc
> > @@ -62,7 +62,7 @@ cache_cpucfg (void)
> > =C2=A0 uint32_t
> > =C2=A0 get_native_prid (void)
> > =C2=A0 {
> > -=C2=A0 /* Fill loongarch_cpu_default_config[CPU_NATIVE] with cpucfg
> > data,
> > +=C2=A0 /* Fill loongarch_cpu_default_config[ARCH_NATIVE] with cpucfg
> > data,
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 see "Loongson Architecture Referen=
ce Manual"
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (Volume 1, Section 2.2.10.5) */
> > =C2=A0=C2=A0=C2=A0 return cpucfg_cache[0];
> > @@ -76,13 +76,14 @@ get_native_prid_str (void)
> > =C2=A0=C2=A0=C2=A0 return (const char*) prid_str;
> > =C2=A0 }
> > =C2=A0=20
> > -/* Fill property tables for CPU_NATIVE.=C2=A0 */
> > +/* Fill property tables for ARCH_NATIVE / TUNE_NATIVE.=C2=A0 */
> > =C2=A0 void
> > =C2=A0 fill_native_cpu_config (struct loongarch_target *tgt)
> > =C2=A0 {
> > -=C2=A0 int arch_native_p =3D tgt->cpu_arch =3D=3D CPU_NATIVE;
> > -=C2=A0 int tune_native_p =3D tgt->cpu_tune =3D=3D CPU_NATIVE;
> > -=C2=A0 int native_cpu_type =3D CPU_NATIVE;
> > +=C2=A0 int arch_native_p =3D tgt->cpu_arch =3D=3D ARCH_NATIVE;
> > +=C2=A0 int tune_native_p =3D tgt->cpu_tune =3D=3D TUNE_NATIVE;
> > +=C2=A0 int native_cpu_arch =3D ARCH_NATIVE;
> > +=C2=A0 int native_cpu_tune =3D TUNE_NATIVE;
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 /* Nothing needs to be done unless "-march/tune=3Dna=
tive"
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 is given or implied.=C2=A0 */
> > @@ -99,11 +100,13 @@ fill_native_cpu_config (struct loongarch_target
> > *tgt)
> > =C2=A0=C2=A0=C2=A0 switch (cpucfg_cache[0] & 0x00ffff00)
> > =C2=A0=C2=A0=C2=A0 {
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 0x0014c000:=C2=A0=C2=A0 /* LA464 */
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 native_cpu_type =3D CPU_LA464;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 native_cpu_arch =3D ARCH_LA464;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 native_cpu_tune =3D TUNE_LA464;
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case 0x0014d000:=C2=A0=C2=A0 /* LA664 */
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 native_cpu_type =3D CPU_LA664;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 native_cpu_arch =3D ARCH_LA664;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 native_cpu_tune =3D TUNE_LA664;
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 default:
> > @@ -119,7 +122,7 @@ fill_native_cpu_config (struct loongarch_target
> > *tgt)
> > =C2=A0=C2=A0=C2=A0 if (arch_native_p)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int tmp;
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tgt->cpu_arch =3D native_cpu_type;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tgt->cpu_arch =3D native_cpu_arch;
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 auto &preset =3D loongarch_c=
pu_default_isa[tgt->cpu_arch];
> > =C2=A0=20
> > @@ -127,8 +130,8 @@ fill_native_cpu_config (struct loongarch_target
> > *tgt)
> > =C2=A0=C2=A0	 With: base architecture (ARCH)
> > =C2=A0=C2=A0	 At:=C2=A0=C2=A0 cpucfg_words[1][1:0] */
> > =C2=A0=20
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_type !=3D CPU_NATIVE)
> > -	tmp =3D loongarch_cpu_default_isa[native_cpu_type].base;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_arch !=3D ARCH_NATIVE)
> > +	tmp =3D loongarch_cpu_default_isa[native_cpu_arch].base;
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 else
> > =C2=A0=C2=A0	switch (cpucfg_cache[1] & 0x3)
> > =C2=A0=C2=A0	=C2=A0 {
> > @@ -173,7 +176,7 @@ fill_native_cpu_config (struct loongarch_target
> > *tgt)
> > =C2=A0=C2=A0	}
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Check consistency with PR=
ID presets.=C2=A0 */
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_type !=3D CPU_NATIVE && =
tmp !=3D preset.fpu)
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_arch !=3D ARCH_NATIVE &&=
 tmp !=3D preset.fpu)
> > =C2=A0=C2=A0	warning (0, "floating-point unit %qs differs from PRID
> > preset %qs",
> > =C2=A0=C2=A0		 loongarch_isa_ext_strings[tmp],
> > =C2=A0=C2=A0		 loongarch_isa_ext_strings[preset.fpu]);
> > @@ -182,7 +185,7 @@ fill_native_cpu_config (struct loongarch_target
> > *tgt)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 preset.fpu =3D tmp;
> > =C2=A0=20
> > =C2=A0=20
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Fill: loongarch_cpu_default_isa[CPU_=
NATIVE].simd
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Fill: loongarch_cpu_default_isa[ARCH=
_NATIVE].simd
> > =C2=A0=C2=A0	 With: SIMD extension type (LSX, LASX)
> > =C2=A0=C2=A0	 At:=C2=A0=C2=A0 cpucfg_words[2][7:6] */
> > =C2=A0=20
> > @@ -212,7 +215,7 @@ fill_native_cpu_config (struct loongarch_target
> > *tgt)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Check consistency with PR=
ID presets.=C2=A0 */
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /*
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_type !=3D CPU_NATIVE && =
tmp !=3D preset.simd)
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_arch !=3D ARCH_NATIVE &&=
 tmp !=3D preset.simd)
> > =C2=A0=C2=A0	warning (0, "SIMD extension %qs differs from PRID preset
> > %qs",
> > =C2=A0=C2=A0		 loongarch_isa_ext_strings[tmp],
> > =C2=A0=C2=A0		 loongarch_isa_ext_strings[preset.simd]);
> > @@ -229,10 +232,10 @@ fill_native_cpu_config (struct
> > loongarch_target *tgt)
> > =C2=A0=C2=A0	if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
> > =C2=A0=C2=A0	=C2=A0 hw_isa_evolution |=3D entry.isa_evolution_bit;
> > =C2=A0=20
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_type !=3D CPU_NATIVE)
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (native_cpu_arch !=3D ARCH_NATIVE)
> > =C2=A0=C2=A0	{
> > =C2=A0=C2=A0	=C2=A0 /* Check if the local CPU really supports the featu=
res of
> > the base
> > -	=C2=A0=C2=A0=C2=A0=C2=A0 ISA of probed native_cpu_type.=C2=A0 If any =
feature is not
> > detected,
> > +	=C2=A0=C2=A0=C2=A0=C2=A0 ISA of probed native_cpu_arch.=C2=A0 If any =
feature is not
> > detected,
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0=C2=A0 either GCC or the hardware is bug=
gy.=C2=A0 */
> > =C2=A0=C2=A0	=C2=A0 if ((preset.evolution & hw_isa_evolution) !=3D
> > hw_isa_evolution)
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 warning (0,
> > @@ -247,7 +250,7 @@ fill_native_cpu_config (struct loongarch_target
> > *tgt)
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 if (tune_native_p)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tgt->cpu_tune =3D native_cpu_type;
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tgt->cpu_tune =3D native_cpu_tune;
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Fill: loongarch_cpu_cache=
[tgt->cpu_tune]
> > =C2=A0=C2=A0	 With: cache size info
> > diff --git a/gcc/config/loongarch/loongarch-def.cc
> > b/gcc/config/loongarch/loongarch-def.cc
> > index 63a8f108f4e..d19628f3454 100644
> > --- a/gcc/config/loongarch/loongarch-def.cc
> > +++ b/gcc/config/loongarch/loongarch-def.cc
> > @@ -31,39 +31,64 @@ template <class T, int N>
> > =C2=A0 using array =3D loongarch_def_array<T, N>;
> > =C2=A0=20
> > =C2=A0 template <class T>
> > -using array_tune =3D array<T, N_TUNE_TYPES>;
> > +using array_arch =3D array<T, N_ARCH_TYPES>;
> > =C2=A0=20
> > =C2=A0 template <class T>
> > -using array_arch =3D array<T, N_ARCH_TYPES>;
> > +using array_tune =3D array<T, N_TUNE_TYPES>;
> > =C2=A0=20
> > -/* CPU property tables.=C2=A0 */
> > -array_tune<const char *> loongarch_cpu_strings =3D array_tune<const
> > char *> ()
> > -=C2=A0 .set (CPU_NATIVE, STR_CPU_NATIVE)
> > -=C2=A0 .set (CPU_ABI_DEFAULT, STR_CPU_ABI_DEFAULT)
> > -=C2=A0 .set (CPU_LOONGARCH64, STR_CPU_LOONGARCH64)
> > -=C2=A0 .set (CPU_LA464, STR_CPU_LA464)
> > -=C2=A0 .set (CPU_LA664, STR_CPU_LA664);
> > +array_arch<const char *> loongarch_arch_strings =3D array_arch<const
> > char *> ()
> > +=C2=A0 .set (ARCH_NATIVE, STR_CPU_NATIVE)
> > +=C2=A0 .set (ARCH_ABI_DEFAULT, STR_ARCH_ABI_DEFAULT)
> > +=C2=A0 .set (ARCH_LOONGARCH64, STR_CPU_LOONGARCH64)
> > +=C2=A0 .set (ARCH_LA464, STR_CPU_LA464)
> > +=C2=A0 .set (ARCH_LA664, STR_CPU_LA664)
> > +=C2=A0 .set (ARCH_LA64V1_0, STR_ARCH_LA64V1_0)
> > +=C2=A0 .set (ARCH_LA64V1_1, STR_ARCH_LA64V1_1);
> > +
> > +array_tune<const char *> loongarch_tune_strings =3D array_tune<const
> > char *> ()
> > +=C2=A0 .set (TUNE_NATIVE, STR_CPU_NATIVE)
> > +=C2=A0 .set (TUNE_GENERIC, STR_TUNE_GENERIC)
> > +=C2=A0 .set (TUNE_LOONGARCH64, STR_CPU_LOONGARCH64)
> > +=C2=A0 .set (TUNE_LA464, STR_CPU_LA464)
> > +=C2=A0 .set (TUNE_LA664, STR_CPU_LA664);
> > =C2=A0=20
> > =C2=A0 array_arch<loongarch_isa> loongarch_cpu_default_isa =3D
> > =C2=A0=C2=A0=C2=A0 array_arch<loongarch_isa> ()
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LOONGARCH64,
> > +=C2=A0=C2=A0=C2=A0 .set (ARCH_LOONGARCH64,
> > =C2=A0=C2=A0	=C2=A0 loongarch_isa ()
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .base_ (ISA_BASE_LA64)
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .fpu_ (ISA_EXT_FPU64))
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LA464,
> > +
> > +=C2=A0=C2=A0=C2=A0 .set (ARCH_LA464,
> > =C2=A0=C2=A0	=C2=A0 loongarch_isa ()
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .base_ (ISA_BASE_LA64)
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .fpu_ (ISA_EXT_FPU64)
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .simd_ (ISA_EXT_SIMD_LASX))
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LA664,
> > +
> > +=C2=A0=C2=A0=C2=A0 .set (ARCH_LA664,
> > =C2=A0=C2=A0	=C2=A0 loongarch_isa ()
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .base_ (ISA_BASE_LA64)
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .fpu_ (ISA_EXT_FPU64)
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .simd_ (ISA_EXT_SIMD_LASX)
> > +	=C2=A0=C2=A0=C2=A0 .evolution_ (OPTION_MASK_ISA_DIV32 |
> > OPTION_MASK_ISA_LD_SEQ_SA
> > +			 | OPTION_MASK_ISA_LAM_BH |
> > OPTION_MASK_ISA_LAMCAS
> > +			 | OPTION_MASK_ISA_FRECIPE))
> > +=C2=A0=C2=A0=C2=A0 .set (ARCH_LA64V1_0,
> > +	=C2=A0 loongarch_isa ()
> > +	=C2=A0=C2=A0=C2=A0 .base_ (ISA_BASE_LA64)
> > +	=C2=A0=C2=A0=C2=A0 .fpu_ (ISA_EXT_FPU64)
> > +	=C2=A0=C2=A0=C2=A0 .simd_ (ISA_EXT_SIMD_LSX))
> > +
> > +=C2=A0=C2=A0=C2=A0 .set (ARCH_LA64V1_1,
> > +	=C2=A0 loongarch_isa ()
> > +	=C2=A0=C2=A0=C2=A0 .base_ (ISA_BASE_LA64)
> > +	=C2=A0=C2=A0=C2=A0 .fpu_ (ISA_EXT_FPU64)
> > +	=C2=A0=C2=A0=C2=A0 .simd_ (ISA_EXT_SIMD_LSX)
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .evolution_ (OPTION_MASK_ISA_DIV32 |
> > OPTION_MASK_ISA_LD_SEQ_SA
> > =C2=A0=C2=A0			 | OPTION_MASK_ISA_LAM_BH |
> > OPTION_MASK_ISA_LAMCAS
> > =C2=A0=C2=A0			 | OPTION_MASK_ISA_FRECIPE));
> > =C2=A0=20
> > +
> > =C2=A0 static inline loongarch_cache la464_cache ()
> > =C2=A0 {
> > =C2=A0=C2=A0=C2=A0 return loongarch_cache ()
> > @@ -75,9 +100,10 @@ static inline loongarch_cache la464_cache ()
> > =C2=A0=20
> > =C2=A0 array_tune<loongarch_cache> loongarch_cpu_cache =3D
> > =C2=A0=C2=A0=C2=A0 array_tune<loongarch_cache> ()
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LOONGARCH64, la464_cache ())
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LA464, la464_cache ())
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LA664, la464_cache ());
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_GENERIC, la464_cache ())
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_LOONGARCH64, la464_cache ())
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_LA464, la464_cache ())
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_LA664, la464_cache ());
> > =C2=A0=20
> > =C2=A0 static inline loongarch_align la464_align ()
> > =C2=A0 {
> > @@ -91,9 +117,10 @@ static inline loongarch_align la664_align ()
> > =C2=A0=20
> > =C2=A0 array_tune<loongarch_align> loongarch_cpu_align =3D
> > =C2=A0=C2=A0=C2=A0 array_tune<loongarch_align> ()
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LOONGARCH64, la664_align ())
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LA464, la464_align ())
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LA664, la664_align ());
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_GENERIC, la664_align ())
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_LOONGARCH64, la664_align ())
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_LA464, la464_align ())
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_LA664, la664_align ());
> > =C2=A0=20
> > =C2=A0 /* Default RTX cost initializer.=C2=A0 */
> > =C2=A0 loongarch_rtx_cost_data::loongarch_rtx_cost_data ()
> > @@ -117,7 +144,7 @@ loongarch_rtx_cost_data::loongarch_rtx_cost_data
> > ()
> > =C2=A0=C2=A0 any known "-mtune" type).=C2=A0 */
> > =C2=A0 array_tune<loongarch_rtx_cost_data> loongarch_cpu_rtx_cost_data =
=3D
> > =C2=A0=C2=A0=C2=A0 array_tune<loongarch_rtx_cost_data> ()
> > -=C2=A0=C2=A0=C2=A0 .set (CPU_LA664,
> > +=C2=A0=C2=A0=C2=A0 .set (TUNE_LA664,
> > =C2=A0=C2=A0	=C2=A0 loongarch_rtx_cost_data ()
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .movcf2gr_ (COSTS_N_INSNS (1))
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0 .movgr2cf_ (COSTS_N_INSNS (1)));
> > @@ -140,16 +167,18 @@ const loongarch_rtx_cost_data
> > loongarch_rtx_cost_optimize_size =3D
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .movcf2gr_ (COST_COMPLEX_INSN);
> > =C2=A0=20
> > =C2=A0 array_tune<int> loongarch_cpu_issue_rate =3D array_tune<int> ()
> > -=C2=A0 .set (CPU_NATIVE, 4)
> > -=C2=A0 .set (CPU_LOONGARCH64, 4)
> > -=C2=A0 .set (CPU_LA464, 4)
> > -=C2=A0 .set (CPU_LA664, 6);
> > +=C2=A0 .set (TUNE_NATIVE, 4)
> > +=C2=A0 .set (TUNE_GENERIC, 4)
> > +=C2=A0 .set (TUNE_LOONGARCH64, 4)
> > +=C2=A0 .set (TUNE_LA464, 4)
> > +=C2=A0 .set (TUNE_LA664, 6);
> > =C2=A0=20
> > =C2=A0 array_tune<int> loongarch_cpu_multipass_dfa_lookahead =3D
> > array_tune<int> ()
> > -=C2=A0 .set (CPU_NATIVE, 4)
> > -=C2=A0 .set (CPU_LOONGARCH64, 4)
> > -=C2=A0 .set (CPU_LA464, 4)
> > -=C2=A0 .set (CPU_LA664, 6);
> > +=C2=A0 .set (TUNE_NATIVE, 4)
> > +=C2=A0 .set (TUNE_GENERIC, 4)
> > +=C2=A0 .set (TUNE_LOONGARCH64, 4)
> > +=C2=A0 .set (TUNE_LA464, 4)
> > +=C2=A0 .set (TUNE_LA664, 6);
> > =C2=A0=20
> > =C2=A0 /* Wiring string definitions from loongarch-str.h to global arra=
ys
> > =C2=A0=C2=A0=C2=A0=C2=A0 with standard index values from loongarch-opts=
.h, so we can
> > diff --git a/gcc/config/loongarch/loongarch-def.h
> > b/gcc/config/loongarch/loongarch-def.h
> > index 60ce3e230f1..ef7d183df50 100644
> > --- a/gcc/config/loongarch/loongarch-def.h
> > +++ b/gcc/config/loongarch/loongarch-def.h
> > @@ -177,21 +177,32 @@ struct loongarch_target
> > =C2=A0 {
> > =C2=A0=C2=A0=C2=A0 struct loongarch_isa isa;
> > =C2=A0=C2=A0=C2=A0 struct loongarch_abi abi;
> > -=C2=A0 int cpu_arch;	=C2=A0=C2=A0=C2=A0 /* CPU_ */
> > -=C2=A0 int cpu_tune;	=C2=A0=C2=A0=C2=A0 /* same */
> > +=C2=A0 int cpu_arch;	=C2=A0=C2=A0=C2=A0 /* ARCH_ */
> > +=C2=A0 int cpu_tune;	=C2=A0=C2=A0=C2=A0 /* TUNE_ */
> > =C2=A0=C2=A0=C2=A0 int cmodel;	=C2=A0=C2=A0=C2=A0 /* CMODEL_ */
> > =C2=A0=C2=A0=C2=A0 int tls_dialect;=C2=A0 /* TLS_ */
> > =C2=A0 };
> > =C2=A0=20
> > -/* CPU model */
> > +/* ISA target presets (-march=3D*) */
> > =C2=A0 enum {
> > -=C2=A0 CPU_NATIVE	=C2=A0=C2=A0=C2=A0 =3D 0,
> > -=C2=A0 CPU_ABI_DEFAULT=C2=A0=C2=A0 =3D 1,
> > -=C2=A0 CPU_LOONGARCH64=C2=A0=C2=A0 =3D 2,
> > -=C2=A0 CPU_LA464	=C2=A0=C2=A0=C2=A0 =3D 3,
> > -=C2=A0 CPU_LA664	=C2=A0=C2=A0=C2=A0 =3D 4,
> > -=C2=A0 N_ARCH_TYPES	=C2=A0=C2=A0=C2=A0 =3D 5,
> > -=C2=A0 N_TUNE_TYPES	=C2=A0=C2=A0=C2=A0 =3D 5
> > +=C2=A0 ARCH_NATIVE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D 0,
> > +=C2=A0 ARCH_ABI_DEFAULT=C2=A0 =3D 1,
> > +=C2=A0 ARCH_LOONGARCH64=C2=A0 =3D 2,
> > +=C2=A0 ARCH_LA464	=C2=A0=C2=A0=C2=A0 =3D 3,
> > +=C2=A0 ARCH_LA664	=C2=A0=C2=A0=C2=A0 =3D 4,
> > +=C2=A0 ARCH_LA64V1_0=C2=A0=C2=A0=C2=A0=C2=A0 =3D 5,
> > +=C2=A0 ARCH_LA64V1_1=C2=A0=C2=A0=C2=A0=C2=A0 =3D 6,
> > +=C2=A0 N_ARCH_TYPES=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D 7,
> > +};
> > +
> > +/* Tune target presets (-mtune=3D*) */
> > +enum {
> > +=C2=A0 TUNE_NATIVE=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D 0,
> > +=C2=A0 TUNE_GENERIC=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D 1,
> > +=C2=A0 TUNE_LOONGARCH64=C2=A0 =3D 2,
> > +=C2=A0 TUNE_LA464	=C2=A0=C2=A0=C2=A0 =3D 3,
> > +=C2=A0 TUNE_LA664	=C2=A0=C2=A0=C2=A0 =3D 4,
> > +=C2=A0 N_TUNE_TYPES=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D 5,
> > =C2=A0 };
> > =C2=A0=20
> > =C2=A0 /* TLS types.=C2=A0 */
> > @@ -200,9 +211,11 @@ enum {
> > =C2=A0=C2=A0=C2=A0 TLS_DESCRIPTORS =3D 1
> > =C2=A0 };
> > =C2=A0=20
> > -/* CPU model properties */
> > +/* Target preset properties */
> > =C2=A0 extern loongarch_def_array<const char *, N_ARCH_TYPES>
> > -=C2=A0 loongarch_cpu_strings;
> > +=C2=A0 loongarch_arch_strings;
> > +extern loongarch_def_array<const char *, N_TUNE_TYPES>
> > +=C2=A0 loongarch_tune_strings;
> > =C2=A0 extern loongarch_def_array<loongarch_isa, N_ARCH_TYPES>
> > =C2=A0=C2=A0=C2=A0 loongarch_cpu_default_isa;
> > =C2=A0 extern loongarch_def_array<int, N_TUNE_TYPES>
> > diff --git a/gcc/config/loongarch/loongarch-driver.cc
> > b/gcc/config/loongarch/loongarch-driver.cc
> > index 8c4ed34698b..628dcdc3b77 100644
> > --- a/gcc/config/loongarch/loongarch-driver.cc
> > +++ b/gcc/config/loongarch/loongarch-driver.cc
> > @@ -85,10 +85,10 @@ driver_set_m_parm (int argc, const char **argv)
> > =C2=A0=C2=A0			=C2=A0=C2=A0 loongarch_isa_ext_strings, 0,
> > N_ISA_EXT_TYPES)
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 LARCH_DRIVER_PARSE_PARM (la_target.cpu_arch, ARCH, \
> > -			=C2=A0=C2=A0 loongarch_cpu_strings, 0, N_ARCH_TYPES)
> > +			=C2=A0=C2=A0 loongarch_arch_strings, 0, N_ARCH_TYPES)
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 LARCH_DRIVER_PARSE_PARM (la_target.cpu_tune, TUNE, \
> > -			=C2=A0=C2=A0 loongarch_cpu_strings, 0, N_TUNE_TYPES)
> > +			=C2=A0=C2=A0 loongarch_tune_strings, 0, N_TUNE_TYPES)
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 LARCH_DRIVER_PARSE_PARM (la_target.cmodel, CMODEL, \
> > =C2=A0=C2=A0			=C2=A0=C2=A0 loongarch_cmodel_strings, 0,
> > N_CMODEL_TYPES)
> > @@ -190,7 +190,7 @@ driver_get_normalized_m_opts (int argc, const
> > char **argv ATTRIBUTE_UNUSED)
> > =C2=A0=C2=A0=C2=A0 APPEND_VAL (loongarch_abi_base_strings[la_target.abi=
.base]);
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 APPEND_OPT (ARCH);
> > -=C2=A0 APPEND_VAL (loongarch_cpu_strings[la_target.cpu_arch]);
> > +=C2=A0 APPEND_VAL (loongarch_arch_strings[la_target.cpu_arch]);
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 APPEND_OPT (ISA_EXT_FPU);
> > =C2=A0=C2=A0=C2=A0 APPEND_VAL (loongarch_isa_ext_strings[la_target.isa.=
fpu]);
> > @@ -202,7 +202,7 @@ driver_get_normalized_m_opts (int argc, const
> > char **argv ATTRIBUTE_UNUSED)
> > =C2=A0=C2=A0=C2=A0 APPEND_VAL (loongarch_cmodel_strings[la_target.cmode=
l]);
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 APPEND_OPT (TUNE);
> > -=C2=A0 APPEND_VAL (loongarch_cpu_strings[la_target.cpu_tune]);
> > +=C2=A0 APPEND_VAL (loongarch_tune_strings[la_target.cpu_tune]);
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 obstack_1grow (&opts_obstack, '\0');
> > =C2=A0=20
> > diff --git a/gcc/config/loongarch/loongarch-opts.cc
> > b/gcc/config/loongarch/loongarch-opts.cc
> > index 7b21cc311a8..8408a70e5ca 100644
> > --- a/gcc/config/loongarch/loongarch-opts.cc
> > +++ b/gcc/config/loongarch/loongarch-opts.cc
> > @@ -101,6 +101,7 @@ static int abi_compat_p (const struct
> > loongarch_isa *isa,
> > =C2=A0=C2=A0			 struct loongarch_abi abi);
> > =C2=A0 static int abi_default_cpu_arch (struct loongarch_abi abi,
> > =C2=A0=C2=A0				 struct loongarch_isa *isa);
> > +static int default_tune_for_arch (int arch, int fallback);
> > =C2=A0=20
> > =C2=A0 /* Mandatory configure-time defaults.=C2=A0 */
> > =C2=A0 #ifndef DEFAULT_ABI_BASE
> > @@ -259,35 +260,35 @@ loongarch_config_target (struct
> > loongarch_target *target,
> > =C2=A0=C2=A0=C2=A0 /* If cpu_tune is not set using neither -mtune nor -=
-with-tune,
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 the current cpu_arch is used as it=
s default.=C2=A0 */
> > =C2=A0=C2=A0=C2=A0 t.cpu_tune =3D constrained.tune ? target->cpu_tune
> > -=C2=A0=C2=A0=C2=A0 : (constrained.arch ? target->cpu_arch :
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (with_default_tune ? DEFAULT_CPU_=
TUNE : DEFAULT_CPU_ARCH));
> > +=C2=A0=C2=A0=C2=A0 : (constrained.arch
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ? default_tune_for_arch (target->=
cpu_arch, with_default_tune
> > +				? DEFAULT_CPU_TUNE : TUNE_GENERIC)
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : (with_default_tune ? DEFAULT_CP=
U_TUNE
> > +	=C2=A0 : default_tune_for_arch (DEFAULT_CPU_ARCH,
> > TUNE_GENERIC)));
> > =C2=A0=20
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 /* Handle -march/tune=3Dnative */
> > =C2=A0 #ifdef __loongarch__
> > =C2=A0=C2=A0=C2=A0 /* For native compilers, gather local CPU informatio=
n
> > -=C2=A0=C2=A0=C2=A0=C2=A0 and fill the "CPU_NATIVE" index of arrays def=
ined in
> > -=C2=A0=C2=A0=C2=A0=C2=A0 loongarch-cpu.c.=C2=A0 */
> > +=C2=A0=C2=A0=C2=A0=C2=A0 and fill the "ARCH_NATIVE/TUNE_NATIVE" index =
of arrays
> > +=C2=A0=C2=A0=C2=A0=C2=A0 defined in loongarch-cpu.c.=C2=A0 */
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 fill_native_cpu_config (&t);
> > =C2=A0=20
> > =C2=A0 #else
> > -=C2=A0 if (t.cpu_arch =3D=3D CPU_NATIVE)
> > +=C2=A0 if (t.cpu_arch =3D=3D ARCH_NATIVE)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fatal_error (UNKNOWN_LOCATION,
> > =C2=A0=C2=A0		 "%qs does not work on a cross compiler",
> > =C2=A0=C2=A0		 "-m" OPTSTR_ARCH "=3D" STR_CPU_NATIVE);
> > =C2=A0=20
> > -=C2=A0 else if (t.cpu_tune =3D=3D CPU_NATIVE)
> > +=C2=A0 else if (t.cpu_tune =3D=3D TUNE_NATIVE)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fatal_error (UNKNOWN_LOCATION,
> > =C2=A0=C2=A0		 "%qs does not work on a cross compiler",
> > =C2=A0=C2=A0		 "-m" OPTSTR_TUNE "=3D" STR_CPU_NATIVE);
> > =C2=A0 #endif
> > =C2=A0=20
> > -=C2=A0 /* Handle -march/tune=3Dabi-default */
> > -=C2=A0 if (t.cpu_tune =3D=3D CPU_ABI_DEFAULT)
> > -=C2=A0=C2=A0=C2=A0 t.cpu_tune =3D abi_default_cpu_arch (t.abi, NULL);
> > -
> > -=C2=A0 if (t.cpu_arch =3D=3D CPU_ABI_DEFAULT)
> > +=C2=A0 /* Handle -march=3Dabi-default */
> > +=C2=A0 if (t.cpu_arch =3D=3D ARCH_ABI_DEFAULT)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 t.cpu_arch =3D abi_default_c=
pu_arch (t.abi, &(t.isa));
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 loongarch_cpu_default_isa[t.=
cpu_arch] =3D t.isa;
> > @@ -438,16 +439,16 @@ config_target_isa:
> > =C2=A0=C2=A0	 so we adjust that first if it is not constrained.=C2=A0 *=
/
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int fallback_arch =3D abi_de=
fault_cpu_arch (t.abi, NULL);
> > =C2=A0=20
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (t.cpu_arch =3D=3D CPU_NATIVE)
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (t.cpu_arch =3D=3D ARCH_NATIVE)
> > =C2=A0=C2=A0	warning (0, "your native CPU architecture (%qs) "
> > =C2=A0=C2=A0		 "does not support %qs ABI, falling back to %<-
> > m%s=3D%s%>",
> > =C2=A0=C2=A0		 arch_str (&t), abi_str (t.abi), OPTSTR_ARCH,
> > -		 loongarch_cpu_strings[fallback_arch]);
> > +		 loongarch_arch_strings[fallback_arch]);
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 else
> > =C2=A0=C2=A0	warning (0, "default CPU architecture (%qs) "
> > =C2=A0=C2=A0		 "does not support %qs ABI, falling back to %<-
> > m%s=3D%s%>",
> > =C2=A0=C2=A0		 arch_str (&t), abi_str (t.abi), OPTSTR_ARCH,
> > -		 loongarch_cpu_strings[fallback_arch]);
> > +		 loongarch_arch_strings[fallback_arch]);
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 t.cpu_arch =3D fallback_arch=
;
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 constrained.arch =3D 1;
> > @@ -664,11 +665,40 @@ abi_default_cpu_arch (struct loongarch_abi
> > abi,
> > =C2=A0=C2=A0	case ABI_BASE_LP64F:
> > =C2=A0=C2=A0	case ABI_BASE_LP64S:
> > =C2=A0=C2=A0	=C2=A0 *isa =3D isa_required (abi);
> > -	=C2=A0 return CPU_LOONGARCH64;
> > +	=C2=A0 return ARCH_LOONGARCH64;
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }
> > =C2=A0=C2=A0=C2=A0 gcc_unreachable ();
> > =C2=A0 }
> > =C2=A0=20
> > +static inline int
> > +default_tune_for_arch (int arch, int fallback)
> > +{
> > +=C2=A0 int ret;
> > +=C2=A0 switch (arch)
> > +=C2=A0=C2=A0=C2=A0 {
> > +
> > +#define TUNE_FOR_ARCH(NAME) \
> > +=C2=A0=C2=A0=C2=A0 case ARCH_##NAME: \
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D TUNE_##NAME; \
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
> > +
> > +=C2=A0=C2=A0=C2=A0 TUNE_FOR_ARCH(NATIVE)
> > +=C2=A0=C2=A0=C2=A0 TUNE_FOR_ARCH(LOONGARCH64)
> > +=C2=A0=C2=A0=C2=A0 TUNE_FOR_ARCH(LA464)
> > +=C2=A0=C2=A0=C2=A0 TUNE_FOR_ARCH(LA664)
> > +
> > +#undef TUNE_FOR_ARCH
> > +
> > +=C2=A0=C2=A0=C2=A0 case ARCH_ABI_DEFAULT:
> > +=C2=A0=C2=A0=C2=A0 case ARCH_LA64V1_0:
> > +=C2=A0=C2=A0=C2=A0 case ARCH_LA64V1_1:
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D fallback;
> > +=C2=A0=C2=A0=C2=A0 }
> > +
> > +=C2=A0 gcc_assert (0 <=3D ret && ret < N_TUNE_TYPES);
> > +=C2=A0 return ret;
> > +}
> > +
> > =C2=A0 static const char*
> > =C2=A0 abi_str (struct loongarch_abi abi)
> > =C2=A0 {
> > @@ -731,7 +761,7 @@ isa_str (const struct loongarch_isa *isa, char
> > separator)
> > =C2=A0 static const char*
> > =C2=A0 arch_str (const struct loongarch_target *target)
> > =C2=A0 {
> > -=C2=A0 if (target->cpu_arch =3D=3D CPU_NATIVE)
> > +=C2=A0 if (target->cpu_arch =3D=3D ARCH_NATIVE)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Describe a native CPU wit=
h unknown PRID.=C2=A0 */
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 const char* isa_string =3D i=
sa_str (&target->isa, ',');
> > @@ -741,7 +771,7 @@ arch_str (const struct loongarch_target *target)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 APPEND_STRING (isa_string)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }
> > =C2=A0=C2=A0=C2=A0 else
> > -=C2=A0=C2=A0=C2=A0 APPEND_STRING (loongarch_cpu_strings[target->cpu_ar=
ch]);
> > +=C2=A0=C2=A0=C2=A0 APPEND_STRING (loongarch_arch_strings[target->cpu_a=
rch]);
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 APPEND1 ('\0')
> > =C2=A0=C2=A0=C2=A0 return XOBFINISH (&msg_obstack, const char *);
> > @@ -956,7 +986,7 @@ loongarch_target_option_override (struct
> > loongarch_target *target,
> > =C2=A0=C2=A0=C2=A0 /* Other arch-specific overrides.=C2=A0 */
> > =C2=A0=C2=A0=C2=A0 switch (target->cpu_arch)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {
> > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case CPU_LA664:
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case ARCH_LA664:
> > =C2=A0=C2=A0	/* Enable -mrecipe=3Dall for LA664 by default.=C2=A0 */
> > =C2=A0=C2=A0	if (!opts_set->x_recip_mask)
> > =C2=A0=C2=A0	=C2=A0 {
> > diff --git a/gcc/config/loongarch/loongarch-opts.h
> > b/gcc/config/loongarch/loongarch-opts.h
> > index 9844b27ed27..f80482357ac 100644
> > --- a/gcc/config/loongarch/loongarch-opts.h
> > +++ b/gcc/config/loongarch/loongarch-opts.h
> > @@ -127,8 +127,8 @@ struct loongarch_flags {
> > =C2=A0=C2=A0=C2=A0 (la_target.isa.evolution & OPTION_MASK_ISA_LD_SEQ_SA=
)
> > =C2=A0=20
> > =C2=A0 /* TARGET_ macros for use in *.md template conditionals */
> > -#define TARGET_uARCH_LA464	=C2=A0 (la_target.cpu_tune =3D=3D CPU_LA464=
)
> > -#define TARGET_uARCH_LA664	=C2=A0 (la_target.cpu_tune =3D=3D CPU_LA664=
)
> > +#define TARGET_uARCH_LA464	=C2=A0 (la_target.cpu_tune =3D=3D
> > TUNE_LA464)
> > +#define TARGET_uARCH_LA664	=C2=A0 (la_target.cpu_tune =3D=3D
> > TUNE_LA664)
> > =C2=A0=20
> > =C2=A0 /* Note: optimize_size may vary across functions,
> > =C2=A0=C2=A0=C2=A0=C2=A0 while -m[no]-memcpy imposes a global constrain=
t.=C2=A0 */
> > diff --git a/gcc/config/loongarch/loongarch-str.h
> > b/gcc/config/loongarch/loongarch-str.h
> > index 20da2b169ed..47f761babb2 100644
> > --- a/gcc/config/loongarch/loongarch-str.h
> > +++ b/gcc/config/loongarch/loongarch-str.h
> > @@ -27,10 +27,13 @@ along with GCC; see the file COPYING3.=C2=A0 If not
> > see
> > =C2=A0 #define OPTSTR_TUNE "tune"
> > =C2=A0=20
> > =C2=A0 #define STR_CPU_NATIVE "native"
> > -#define STR_CPU_ABI_DEFAULT "abi-default"
> > +#define STR_ARCH_ABI_DEFAULT "abi-default"
> > +#define STR_TUNE_GENERIC "generic"
> > =C2=A0 #define STR_CPU_LOONGARCH64 "loongarch64"
> > =C2=A0 #define STR_CPU_LA464 "la464"
> > =C2=A0 #define STR_CPU_LA664 "la664"
> > +#define STR_ARCH_LA64V1_0 "la64v1.0"
> > +#define STR_ARCH_LA64V1_1 "la64v1.1"
> > =C2=A0=20
> > =C2=A0 #define STR_ISA_BASE_LA64 "la64"
> > =C2=A0=20
> > diff --git a/gcc/config/loongarch/loongarch.cc
> > b/gcc/config/loongarch/loongarch.cc
> > index 6b92e7034c5..e7835ae34ae 100644
> > --- a/gcc/config/loongarch/loongarch.cc
> > +++ b/gcc/config/loongarch/loongarch.cc
> > @@ -9609,9 +9609,10 @@ loongarch_cpu_sched_reassociation_width
> > (struct loongarch_target *target,
> > =C2=A0=20
> > =C2=A0=C2=A0=C2=A0 switch (target->cpu_tune)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {
> > -=C2=A0=C2=A0=C2=A0 case CPU_LOONGARCH64:
> > -=C2=A0=C2=A0=C2=A0 case CPU_LA464:
> > -=C2=A0=C2=A0=C2=A0 case CPU_LA664:
> > +=C2=A0=C2=A0=C2=A0 case TUNE_GENERIC:
> > +=C2=A0=C2=A0=C2=A0 case TUNE_LOONGARCH64:
> > +=C2=A0=C2=A0=C2=A0 case TUNE_LA464:
> > +=C2=A0=C2=A0=C2=A0 case TUNE_LA664:
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Vector part.=C2=A0 */
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (LSX_SUPPORTED_MODE_P (mo=
de) || LASX_SUPPORTED_MODE_P
> > (mode))
> > =C2=A0=C2=A0	{
> > @@ -10980,9 +10981,9 @@ loongarch_asm_code_end (void)
> > =C2=A0=C2=A0=C2=A0 if (flag_verbose_asm)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fprintf (asm_out_file, "\n%s=
 CPU: %s\n", ASM_COMMENT_START,
> > -	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 loongarch_cpu_strings [la_target=
.cpu_arch]);
> > +	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 loongarch_arch_strings[la_target=
.cpu_arch]);
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fprintf (asm_out_file, "%s T=
une: %s\n", ASM_COMMENT_START,
> > -	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 loongarch_cpu_strings [la_target=
.cpu_tune]);
> > +	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 loongarch_tune_strings[la_target=
.cpu_tune]);
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fprintf (asm_out_file, "%s B=
ase ISA: %s\n",
> > ASM_COMMENT_START,
> > =C2=A0=C2=A0	=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 loongarch_isa_base_st=
rings [la_target.isa.base]);
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 DUMP_FEATURE (ISA_HAS_FRECIP=
E);
> > diff --git a/gcc/config/loongarch/loongarch.opt
> > b/gcc/config/loongarch/loongarch.opt
> > index 773747f2add..91cb5236ad8 100644
> > --- a/gcc/config/loongarch/loongarch.opt
> > +++ b/gcc/config/loongarch/loongarch.opt
> > @@ -103,30 +103,55 @@ Enable LoongArch Advanced SIMD Extension
> > (LASX, 256-bit).
> > =C2=A0=20
> > =C2=A0 ;; Base target models (implies ISA & tune parameters)
> > =C2=A0 Enum
> > -Name(cpu_type) Type(int)
> > -LoongArch CPU types:
> > +Name(arch_type) Type(int)
> > +LoongArch ARCH presets:
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(native) Value(CPU_NATIVE)
> > +Enum(arch_type) String(native) Value(ARCH_NATIVE)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(abi-default) Value(CPU_ABI_DEFAULT)
> > +Enum(arch_type) String(abi-default) Value(ARCH_ABI_DEFAULT)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
> > +Enum(arch_type) String(loongarch64) Value(ARCH_LOONGARCH64)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(la464) Value(CPU_LA464)
> > +Enum(arch_type) String(la464) Value(ARCH_LA464)
> > =C2=A0=20
> > =C2=A0 EnumValue
> > -Enum(cpu_type) String(la664) Value(CPU_LA664)
> > +Enum(arch_type) String(la664) Value(ARCH_LA664)
> > +
> > +EnumValue
> > +Enum(arch_type) String(la64v1.0) Value(ARCH_LA64V1_0)
> > +
> > +EnumValue
> > +Enum(arch_type) String(la64v1.1) Value(ARCH_LA64V1_1)
> > =C2=A0=20
> > =C2=A0 march=3D
> > -Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch)
> > Init(M_OPT_UNSET) Save
> > +Target RejectNegative Joined Enum(arch_type) Var(la_opt_cpu_arch)
> > Init(M_OPT_UNSET) Save
> > =C2=A0 -march=3DPROCESSOR	Generate code for the given PROCESSOR ISA.
> > =C2=A0=20
> > +Enum
> > +Name(tune_type) Type(int)
> > +LoongArch TUNE presets:
> > +
> > +EnumValue
> > +Enum(tune_type) String(native) Value(TUNE_NATIVE)
> > +
> > +EnumValue
> > +Enum(tune_type) String(generic) Value(TUNE_GENERIC)
> > +
> > +EnumValue
> > +Enum(tune_type) String(loongarch64) Value(TUNE_LOONGARCH64)
> > +
> > +EnumValue
> > +Enum(tune_type) String(la464) Value(TUNE_LA464)
> > +
> > +EnumValue
> > +Enum(tune_type) String(la664) Value(TUNE_LA664)
> > +
> > =C2=A0 mtune=3D
> > -Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune)
> > Init(M_OPT_UNSET) Save
> > +Target RejectNegative Joined Enum(tune_type) Var(la_opt_cpu_tune)
> > Init(M_OPT_UNSET) Save
> > =C2=A0 -mtune=3DPROCESSOR	Generate optimized code for PROCESSOR.
> > =C2=A0=20
> > =C2=A0=20
> > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> > index 5d5e70c3033..6cfb77a0f8a 100644
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -1049,7 +1049,7 @@ Objective-C and Objective-C++ Dialects}.
> > =C2=A0 -msign-extend-enabled=C2=A0 -muser-enabled}
> > =C2=A0=20
> > =C2=A0 @emph{LoongArch Options}
> > -@gccoptlist{-march=3D@var{cpu-type}=C2=A0 -mtune=3D@var{cpu-type}
> > -mabi=3D@var{base-abi-type}
> > +@gccoptlist{-march=3D@var{arch-type}=C2=A0 -mtune=3D@var{tune-type}
> > -mabi=3D@var{base-abi-type}
> > =C2=A0 -mfpu=3D@var{fpu-type} -msimd=3D@var{simd-type}
> > =C2=A0 -msoft-float -msingle-float -mdouble-float -mlsx -mno-lsx -mlasx=
 -
> > mno-lasx
> > =C2=A0 -mbranch-cost=3D@var{n}=C2=A0 -mcheck-zero-division -mno-check-z=
ero-
> > division
> > @@ -26839,34 +26839,51 @@ These command-line options are defined for
> > LoongArch targets:
> > =C2=A0=20
> > =C2=A0 @table @gcctabopt
> > =C2=A0 @opindex march
> > -@item -march=3D@var{cpu-type}
> > -Generate instructions for the machine type @var{cpu-type}.=C2=A0 In
> > contrast to
> > -@option{-mtune=3D@var{cpu-type}}, which merely tunes the generated
> > code
> > -for the specified @var{cpu-type}, @option{-march=3D@var{cpu-type}}
> > allows GCC
> > -to generate code that may not run at all on processors other than
> > the one
> > -indicated.=C2=A0 Specifying @option{-march=3D@var{cpu-type}} implies
> > -@option{-mtune=3D@var{cpu-type}}, except where noted otherwise.
> > +@item -march=3D@var{arch-type}
> > +Generate instructions for the machine type @var{arch-type}.
> > +@option{-march=3D@var{arch-type}} allows GCC to generate code that
> > +may not run at all on processors other than the one indicated.
> > =C2=A0=20
> > -The choices for @var{cpu-type} are:
> > +The choices for @var{arch-type} are:
> > =C2=A0=20
> > =C2=A0 @table @samp
> > =C2=A0 @item native
> > -This selects the CPU to generate code for at compilation time by
> > determining
> > -the processor type of the compiling machine.=C2=A0 Using @option{-
> > march=3Dnative}
> > -enables all instruction subsets supported by the local machine
> > (hence
> > -the result might not run on different machines).=C2=A0 Using @option{-
> > mtune=3Dnative}
> > -produces code optimized for the local machine under the constraints
> > -of the selected instruction set.
> > +Local processor type detected by the native compiler.
> > =C2=A0 @item loongarch64
> > -A generic CPU with 64-bit extensions.
> > +Generic LoongArch 64-bit processor.
> > =C2=A0 @item la464
> > -LoongArch LA464 CPU with LBT, LSX, LASX, LVZ.
> > +LoongArch LA464-based processor with LSX, LASX.
> > +@item la664
> > +LoongArch LA664-based processor with LSX, LASX
> > +and all LoongArch v1.1 instructions.
> > +@item la64v1.0
> > +LoongArch64 ISA version 1.0.
> > +@item la64v1.1
> > +LoongArch64 ISA version 1.1.
> > =C2=A0 @end table
> > =C2=A0=20
> > +More information about LoongArch ISA versions can be found at
> > +@uref{https://github.com/loongson/la-toolchain-conventions}.
> > +
> > =C2=A0 @opindex mtune
> > -@item -mtune=3D@var{cpu-type}
> > -Optimize the output for the given processor, specified by
> > microarchitecture
> > -name.
> > +@item -mtune=3D@var{tune-type}
> > +Optimize the generated code for the given processor target.
> > +
> > +The choices for @var{tune-type} are:
> > +
> > +@table @samp
> > +@item native
> > +Local processor type detected by the native compiler.
> > +@item generic
> > +Generic LoongArch processor.
> > +@item loongarch64
> > +Generic LoongArch 64-bit processor.
> > +@item la464
> > +LoongArch LA464 core.
> > +@item la664
> > +LoongArch LA664 core.
> > +@end table
> > +
> > =C2=A0=20
> > =C2=A0 @opindex mabi
> > =C2=A0 @item -mabi=3D@var{base-abi-type}
>=20

--=20
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University