* [PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal.
@ 2024-05-24 11:48 Jiawei
2024-05-24 12:33 ` Richard Biener
0 siblings, 1 reply; 3+ messages in thread
From: Jiawei @ 2024-05-24 11:48 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, jlaw, Jiawei
An ICE bug reported in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
https://godbolt.org/z/WE9aGYvoo
Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.
gcc/ChangeLog:
* tree-ssa-pre.cc (find_or_generate_expression): Remove assert.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr1071140.c: New test.
---
.../gcc.target/riscv/rvv/vsetvl/pr1071140.c | 52 +++++++++++++++++++
gcc/tree-ssa-pre.cc | 4 +-
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
new file mode 100644
index 00000000000..4f0815e099f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w" } */
+
+#include <riscv_vector.h>
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+ vint32m1_t __trans_tmp_9;
+ {
+ int __trans_tmp_0 = nlane;
+ {
+ vint64m1_t __trans_tmp_1;
+ vint64m1_t __trans_tmp_2;
+ vint64m1_t __trans_tmp_3;
+ vint64m1_t __trans_tmp_4;
+ if (__trans_tmp_0 == 1) {
+ {
+ __trans_tmp_3 =
+ __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+ }
+ __trans_tmp_4 = __trans_tmp_2;
+ }
+ __trans_tmp_4 = __trans_tmp_3;
+ __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+ }
+ }
+ return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+ char *b_src0 = &CFLOAT_add_args[0], *b_src1 = &CFLOAT_add_args[1],
+ *b_dst = &CFLOAT_add_args[2];
+ const float *src1 = (float *)b_src1;
+ float *dst = (float *)b_dst;
+ const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+ const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+ const int hstep = 4 / 2;
+ vfloat32m1x2_t a;
+ int len = 255;
+ for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+ int b = vload_tillz_f32(len);
+ int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type '__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+ }
+ for (; len > 0; --len, b_src0 += CFLOAT_steps,
+ b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+ ;
+}
+
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..e3d9c47f96b 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2777,7 +2777,9 @@ find_or_generate_expression (basic_block block, tree op, gimple_seq *stmts)
if (is_gimple_min_invariant (op))
return op;
- gcc_assert (TREE_CODE (op) == SSA_NAME);
+ if (TREE_CODE (op) != SSA_NAME)
+ return NULL_TREE;
+
vn_ssa_aux_t info = VN_INFO (op);
unsigned int lookfor = info->value_id;
if (value_id_constant_p (lookfor))
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal.
2024-05-24 11:48 [PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal Jiawei
@ 2024-05-24 12:33 ` Richard Biener
2024-05-24 13:18 ` Jiawei
0 siblings, 1 reply; 3+ messages in thread
From: Richard Biener @ 2024-05-24 12:33 UTC (permalink / raw)
To: Jiawei, Richard Sandiford; +Cc: gcc-patches, kito.cheng, jlaw
On Fri, May 24, 2024 at 1:49 PM Jiawei <jiawei@iscas.ac.cn> wrote:
>
> An ICE bug reported in
> https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
> https://godbolt.org/z/WE9aGYvoo
>
> Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.
The assert is on purpose. Can you open a GCC bug for this please? It looks
like we have unfolded POLY_INT_CST [16, 16] /[ex] 16 here.
It seems that
/* We can't always put a size in units of the element alignment
here as the element alignment may be not visible. See
PR43783. Simply drop the element size for constant
sizes. */
if (TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
(wi::to_offset (genop3)
* vn_ref_op_align_unit (currop))))
genop3 = NULL_TREE;
fails to match the POLY_INT case - the unit alignment is 16 here. One
possibility would be to match the EXACT_DIV_EXPR case and the
INTEGER_CST divisor to vn_ref_op_align_unit and the other half
separately. But maybe this can be written in a "proper" way?
The EXACT_DIV_EXPR is built by copy_reference_ops_from_ref,
I suppose SVE could be similarly affected.
Richard.
> gcc/ChangeLog:
>
> * tree-ssa-pre.cc (find_or_generate_expression): Remove assert.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr1071140.c: New test.
>
> ---
> .../gcc.target/riscv/rvv/vsetvl/pr1071140.c | 52 +++++++++++++++++++
> gcc/tree-ssa-pre.cc | 4 +-
> 2 files changed, 55 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
> new file mode 100644
> index 00000000000..4f0815e099f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
> @@ -0,0 +1,52 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w" } */
> +
> +#include <riscv_vector.h>
> +
> +static inline __attribute__(()) int vaddq_f32();
> +static inline __attribute__(()) int vload_tillz_f32(int nlane) {
> + vint32m1_t __trans_tmp_9;
> + {
> + int __trans_tmp_0 = nlane;
> + {
> + vint64m1_t __trans_tmp_1;
> + vint64m1_t __trans_tmp_2;
> + vint64m1_t __trans_tmp_3;
> + vint64m1_t __trans_tmp_4;
> + if (__trans_tmp_0 == 1) {
> + {
> + __trans_tmp_3 =
> + __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
> + }
> + __trans_tmp_4 = __trans_tmp_2;
> + }
> + __trans_tmp_4 = __trans_tmp_3;
> + __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
> + }
> + }
> + return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot be passed to an unprototyped function} } */
> +}
> +
> +char CFLOAT_add_args[3];
> +const int *CFLOAT_add_steps;
> +const int CFLOAT_steps;
> +
> +__attribute__(()) void CFLOAT_add() {
> + char *b_src0 = &CFLOAT_add_args[0], *b_src1 = &CFLOAT_add_args[1],
> + *b_dst = &CFLOAT_add_args[2];
> + const float *src1 = (float *)b_src1;
> + float *dst = (float *)b_dst;
> + const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
> + const int sdst = CFLOAT_add_steps[2] / sizeof(float);
> + const int hstep = 4 / 2;
> + vfloat32m1x2_t a;
> + int len = 255;
> + for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
> + int b = vload_tillz_f32(len);
> + int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type '__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
> + }
> + for (; len > 0; --len, b_src0 += CFLOAT_steps,
> + b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
> + ;
> +}
> +
> diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
> index 75217f5cde1..e3d9c47f96b 100644
> --- a/gcc/tree-ssa-pre.cc
> +++ b/gcc/tree-ssa-pre.cc
> @@ -2777,7 +2777,9 @@ find_or_generate_expression (basic_block block, tree op, gimple_seq *stmts)
> if (is_gimple_min_invariant (op))
> return op;
>
> - gcc_assert (TREE_CODE (op) == SSA_NAME);
> + if (TREE_CODE (op) != SSA_NAME)
> + return NULL_TREE;
> +
> vn_ssa_aux_t info = VN_INFO (op);
> unsigned int lookfor = info->value_id;
> if (value_id_constant_p (lookfor))
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal.
2024-05-24 12:33 ` Richard Biener
@ 2024-05-24 13:18 ` Jiawei
0 siblings, 0 replies; 3+ messages in thread
From: Jiawei @ 2024-05-24 13:18 UTC (permalink / raw)
To: Richard Biener, Richard Sandiford; +Cc: gcc-patches, kito.cheng, jlaw
On 2024/5/24 20:33, Richard Biener wrote:
> On Fri, May 24, 2024 at 1:49 PM Jiawei <jiawei@iscas.ac.cn> wrote:
>> An ICE bug reported in
>> https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
>> https://godbolt.org/z/WE9aGYvoo
>>
>> Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.
> The assert is on purpose. Can you open a GCC bug for this please? It looks
> like we have unfolded POLY_INT_CST [16, 16] /[ex] 16 here.
>
> It seems that
>
> /* We can't always put a size in units of the element alignment
> here as the element alignment may be not visible. See
> PR43783. Simply drop the element size for constant
> sizes. */
> if (TREE_CODE (genop3) == INTEGER_CST
> && TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
> && wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
> (wi::to_offset (genop3)
> * vn_ref_op_align_unit (currop))))
> genop3 = NULL_TREE;
>
> fails to match the POLY_INT case - the unit alignment is 16 here. One
> possibility would be to match the EXACT_DIV_EXPR case and the
> INTEGER_CST divisor to vn_ref_op_align_unit and the other half
> separately. But maybe this can be written in a "proper" way?
>
> The EXACT_DIV_EXPR is built by copy_reference_ops_from_ref,
> I suppose SVE could be similarly affected.
>
> Richard.
Thanks for your quick reply, reported it on bugzilla——
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115214
BR,
Jiawei
>> gcc/ChangeLog:
>>
>> * tree-ssa-pre.cc (find_or_generate_expression): Remove assert.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/rvv/vsetvl/pr1071140.c: New test.
>>
>> ---
>> .../gcc.target/riscv/rvv/vsetvl/pr1071140.c | 52 +++++++++++++++++++
>> gcc/tree-ssa-pre.cc | 4 +-
>> 2 files changed, 55 insertions(+), 1 deletion(-)
>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
>>
>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
>> new file mode 100644
>> index 00000000000..4f0815e099f
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
>> @@ -0,0 +1,52 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w" } */
>> +
>> +#include <riscv_vector.h>
>> +
>> +static inline __attribute__(()) int vaddq_f32();
>> +static inline __attribute__(()) int vload_tillz_f32(int nlane) {
>> + vint32m1_t __trans_tmp_9;
>> + {
>> + int __trans_tmp_0 = nlane;
>> + {
>> + vint64m1_t __trans_tmp_1;
>> + vint64m1_t __trans_tmp_2;
>> + vint64m1_t __trans_tmp_3;
>> + vint64m1_t __trans_tmp_4;
>> + if (__trans_tmp_0 == 1) {
>> + {
>> + __trans_tmp_3 =
>> + __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
>> + }
>> + __trans_tmp_4 = __trans_tmp_2;
>> + }
>> + __trans_tmp_4 = __trans_tmp_3;
>> + __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
>> + }
>> + }
>> + return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot be passed to an unprototyped function} } */
>> +}
>> +
>> +char CFLOAT_add_args[3];
>> +const int *CFLOAT_add_steps;
>> +const int CFLOAT_steps;
>> +
>> +__attribute__(()) void CFLOAT_add() {
>> + char *b_src0 = &CFLOAT_add_args[0], *b_src1 = &CFLOAT_add_args[1],
>> + *b_dst = &CFLOAT_add_args[2];
>> + const float *src1 = (float *)b_src1;
>> + float *dst = (float *)b_dst;
>> + const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
>> + const int sdst = CFLOAT_add_steps[2] / sizeof(float);
>> + const int hstep = 4 / 2;
>> + vfloat32m1x2_t a;
>> + int len = 255;
>> + for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
>> + int b = vload_tillz_f32(len);
>> + int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type '__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
>> + }
>> + for (; len > 0; --len, b_src0 += CFLOAT_steps,
>> + b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
>> + ;
>> +}
>> +
>> diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
>> index 75217f5cde1..e3d9c47f96b 100644
>> --- a/gcc/tree-ssa-pre.cc
>> +++ b/gcc/tree-ssa-pre.cc
>> @@ -2777,7 +2777,9 @@ find_or_generate_expression (basic_block block, tree op, gimple_seq *stmts)
>> if (is_gimple_min_invariant (op))
>> return op;
>>
>> - gcc_assert (TREE_CODE (op) == SSA_NAME);
>> + if (TREE_CODE (op) != SSA_NAME)
>> + return NULL_TREE;
>> +
>> vn_ssa_aux_t info = VN_INFO (op);
>> unsigned int lookfor = info->value_id;
>> if (value_id_constant_p (lookfor))
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-05-24 11:48 [PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal Jiawei
2024-05-24 12:33 ` Richard Biener
2024-05-24 13:18 ` Jiawei
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