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Wed, 25 Nov 2020 02:17:27 +0000 (GMT) Received: from [9.65.207.150] (unknown [9.65.207.150]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTPS; Wed, 25 Nov 2020 02:17:27 +0000 (GMT) Subject: Re: [PATCH v2] rs6000, vector integer multiply/divide/modulo instructions To: Carl Love , Segher Boessenkool Cc: GCC Patches , David Edelsohn References: <0801554741c7f11d26ded3a2243462cb2790c215.camel@us.ibm.com> <20201119232651.GA2672@gate.crashing.org> <5d20abfbfd6e1edd7712305449e6053df8ca3043.camel@us.ibm.com> From: Pat Haugen Message-ID: <81d86281-30d4-4d5a-b5d1-e961aa3c6573@linux.ibm.com> Date: Tue, 24 Nov 2020 20:17:26 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.4.3 MIME-Version: 1.0 In-Reply-To: <5d20abfbfd6e1edd7712305449e6053df8ca3043.camel@us.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-24_11:2020-11-24, 2020-11-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 mlxscore=0 spamscore=0 malwarescore=0 bulkscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011250011 X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Nov 2020 02:17:35 -0000 On 11/24/20 12:59 PM, Carl Love via Gcc-patches wrote: > + > +(define_insn "dives_" > + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") > + (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v") > + (match_operand:VIlong 2 "vsx_register_operand" "v")] > + UNSPEC_VDIVES))] > + "TARGET_POWER10" > + "vdives %0,%1,%2" > + [(set_attr "type" "vecdiv") > + (set_attr "size" "128")]) > + > +(define_insn "diveu_" > + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") > + (unspec: VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v") > + (match_operand:VIlong 2 "vsx_register_operand" "v")] > + UNSPEC_VDIVEU))] > + "TARGET_POWER10" > + "vdiveu %0,%1,%2" > + [(set_attr "type" "vecdiv") > + (set_attr "size" "128")]) > + > +(define_insn "div3" > + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") > + (div:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") > + (match_operand:VIlong 2 "vsx_register_operand" "v")))] > + "TARGET_POWER10" > + "vdivs %0,%1,%2" > + [(set_attr "type" "vecdiv") > + (set_attr "size" "128")]) > + > +(define_insn "udiv3" > + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") > + (udiv:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") > + (match_operand:VIlong 2 "vsx_register_operand" "v")))] > + "TARGET_POWER10" > + "vdivu %0,%1,%2" > + [(set_attr "type" "vecdiv") > + (set_attr "size" "128")]) > + > +(define_insn "mods_" > + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") > + (mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") > + (match_operand:VIlong 2 "vsx_register_operand" "v")))] > + "TARGET_POWER10" > + "vmods %0,%1,%2" > + [(set_attr "type" "vecdiv") > + (set_attr "size" "128")]) > + > +(define_insn "modu_" > + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") > + (umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") > + (match_operand:VIlong 2 "vsx_register_operand" "v")))] > + "TARGET_POWER10" > + "vmodu %0,%1,%2" > + [(set_attr "type" "vecdiv") > + (set_attr "size" "128")]) We should only be setting "size" "128" for instructions that operate on scalar 128-bit data items (i.e. 'vdivesq' etc). Since the above insns are either V2DI/V4SI (ala VIlong mode_iterator), they shouldn't be marked as size 128. If you want to set the size based on mode, (set_attr "size" "") should do the trick I believe. -Pat