* [PATCH 1/2] rs6000: Use brace blocks in define_insn
@ 2018-02-22 1:09 Segher Boessenkool
2018-02-22 1:09 ` [PATCH 2/2] rs6000: Delete meaningless arguments to define_{expand,split,peephole2} Segher Boessenkool
0 siblings, 1 reply; 2+ messages in thread
From: Segher Boessenkool @ 2018-02-22 1:09 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This patch changes the remaining cases in our machine description files
to use brace blocks instead of double-quoted strings as the output
control string. This increases readability by making the blocks look
more like normal C code, mostly because backslash quoting is no longer
needed. It also removes such quoting where it was still there (usually
harmless but always confusing). and it writes "\n\t" as "\;" in one
place where we didn't already.
Tested on powerpc64-linux {-m64,-m32}. Committing to trunk.
Segher
2018-02-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Write output control strings as braced
blocks instead of double-quoted strings.
* config/rs6000/darwin.md: Ditto.
* config/rs6000/rs6000.md: Ditto.
* config/rs6000/vector.md: Ditto.
* config/rs6000/vsx.md: Ditto.
gcc/config/rs6000/altivec.md | 159 ++++++++------------
gcc/config/rs6000/darwin.md | 32 ++--
gcc/config/rs6000/rs6000.md | 346 +++++++++++++++++--------------------------
gcc/config/rs6000/vector.md | 69 +++------
gcc/config/rs6000/vsx.md | 31 +---
5 files changed, 249 insertions(+), 388 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index a01a3c6..55a9f53 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1680,13 +1680,12 @@ (define_insn "altivec_vpkpx"
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VPKPX))]
"TARGET_ALTIVEC"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpkpx %0,%1,%2\";
- else
- return \"vpkpx %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpkpx %0,%1,%2";
+ else
+ return "vpkpx %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>ss"
@@ -1695,13 +1694,12 @@ (define_insn "altivec_vpks<VI_char>ss"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_SIGN_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpks<VI_char>ss %0,%1,%2\";
- else
- return \"vpks<VI_char>ss %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpks<VI_char>ss %0,%1,%2";
+ else
+ return "vpks<VI_char>ss %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>us"
@@ -1710,13 +1708,12 @@ (define_insn "altivec_vpks<VI_char>us"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_UNS_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpks<VI_char>us %0,%1,%2\";
- else
- return \"vpks<VI_char>us %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpks<VI_char>us %0,%1,%2";
+ else
+ return "vpks<VI_char>us %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>us"
@@ -1725,13 +1722,12 @@ (define_insn "altivec_vpku<VI_char>us"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpku<VI_char>us %0,%1,%2\";
- else
- return \"vpku<VI_char>us %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpku<VI_char>us %0,%1,%2";
+ else
+ return "vpku<VI_char>us %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um"
@@ -1740,13 +1736,12 @@ (define_insn "altivec_vpku<VI_char>um"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpku<VI_char>um %0,%1,%2\";
- else
- return \"vpku<VI_char>um %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpku<VI_char>um %0,%1,%2";
+ else
+ return "vpku<VI_char>um %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um_direct"
@@ -1755,13 +1750,12 @@ (define_insn "altivec_vpku<VI_char>um_direct"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))]
"<VI_unit>"
- "*
- {
- if (BYTES_BIG_ENDIAN)
- return \"vpku<VI_char>um %0,%1,%2\";
- else
- return \"vpku<VI_char>um %0,%2,%1\";
- }"
+{
+ if (BYTES_BIG_ENDIAN)
+ return "vpku<VI_char>um %0,%1,%2";
+ else
+ return "vpku<VI_char>um %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "*altivec_vrl<VI_char>"
@@ -2348,7 +2342,6 @@ (define_expand "altivec_copysign_v4sf3"
(use (match_operand:V4SF 1 "register_operand" ""))
(use (match_operand:V4SF 2 "register_operand" ""))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
- "
{
rtx mask = gen_reg_rtx (V4SImode);
rtvec v = rtvec_alloc (4);
@@ -2363,7 +2356,7 @@ (define_expand "altivec_copysign_v4sf3"
emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],
gen_lowpart (V4SFmode, mask)));
DONE;
-}")
+})
(define_insn "altivec_vsldoi_<mode>"
[(set (match_operand:VM 0 "register_operand" "=v")
@@ -2670,8 +2663,7 @@ (define_expand "build_vector_mask_for_load"
[(set (match_operand:V16QI 0 "register_operand" "")
(unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
"TARGET_ALTIVEC"
- "
-{
+{
rtx addr;
rtx temp;
@@ -2683,7 +2675,7 @@ (define_expand "build_vector_mask_for_load"
emit_insn (gen_altivec_lvsr (operands[0],
replace_equiv_address (operands[1], temp)));
DONE;
-}")
+})
;; Parallel some of the LVE* and STV*'s with unspecs because some have
;; identical rtl but different instructions-- and gcc gets confused.
@@ -3361,12 +3353,11 @@ (define_expand "udot_prod<mode>"
(match_operand:VIshort 2 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
- "
-{
+{
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
DONE;
-}")
-
+})
+
(define_expand "sdot_prodv8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
@@ -3374,11 +3365,10 @@ (define_expand "sdot_prodv8hi"
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
- "
{
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
DONE;
-}")
+})
(define_expand "widen_usum<mode>3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3386,14 +3376,13 @@ (define_expand "widen_usum<mode>3"
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "widen_ssumv16qi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3401,14 +3390,13 @@ (define_expand "widen_ssumv16qi3"
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VMSUMM)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (V16QImode);
emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "widen_ssumv8hi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3416,14 +3404,13 @@ (define_expand "widen_ssumv8hi3"
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vspltish (vones, const1_rtx));
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "vec_unpacks_hi_<VP_small_lc>"
[(set (match_operand:VP 0 "register_operand" "=v")
@@ -3471,7 +3458,6 @@ (define_expand "vec_unpacku_hi_v16qi"
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKHUB))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3500,14 +3486,13 @@ (define_expand "vec_unpacku_hi_v16qi"
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKHUH))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3536,14 +3521,13 @@ (define_expand "vec_unpacku_hi_v8hi"
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKLUB))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3572,14 +3556,13 @@ (define_expand "vec_unpacku_lo_v16qi"
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKLUH))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3608,7 +3591,7 @@ (define_expand "vec_unpacku_lo_v8hi"
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_widen_umult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3616,7 +3599,6 @@ (define_expand "vec_widen_umult_hi_v16qi"
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHUB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3634,7 +3616,7 @@ (define_expand "vec_widen_umult_hi_v16qi"
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3642,7 +3624,6 @@ (define_expand "vec_widen_umult_lo_v16qi"
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLUB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3660,7 +3641,7 @@ (define_expand "vec_widen_umult_lo_v16qi"
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3668,7 +3649,6 @@ (define_expand "vec_widen_smult_hi_v16qi"
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHSB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3686,7 +3666,7 @@ (define_expand "vec_widen_smult_hi_v16qi"
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3694,7 +3674,6 @@ (define_expand "vec_widen_smult_lo_v16qi"
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLSB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3712,7 +3691,7 @@ (define_expand "vec_widen_smult_lo_v16qi"
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3720,7 +3699,6 @@ (define_expand "vec_widen_umult_hi_v8hi"
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHUH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3738,7 +3716,7 @@ (define_expand "vec_widen_umult_hi_v8hi"
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3746,7 +3724,6 @@ (define_expand "vec_widen_umult_lo_v8hi"
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLUH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3764,7 +3741,7 @@ (define_expand "vec_widen_umult_lo_v8hi"
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3772,7 +3749,6 @@ (define_expand "vec_widen_smult_hi_v8hi"
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHSH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3790,7 +3766,7 @@ (define_expand "vec_widen_smult_hi_v8hi"
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3798,7 +3774,6 @@ (define_expand "vec_widen_smult_lo_v8hi"
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLSH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3816,7 +3791,7 @@ (define_expand "vec_widen_smult_lo_v8hi"
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_pack_trunc_<mode>"
[(set (match_operand:<VP_small> 0 "register_operand" "=v")
@@ -3831,7 +3806,6 @@ (define_expand "mulv16qi3"
(mult:V16QI (match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
- "
{
rtx even = gen_reg_rtx (V8HImode);
rtx odd = gen_reg_rtx (V8HImode);
@@ -3851,13 +3825,12 @@ (define_expand "mulv16qi3"
emit_insn (gen_altivec_vmulosb (odd, operands[1], operands[2]));
emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], even, odd, mask));
DONE;
-}")
+})
(define_expand "altivec_negv4sf2"
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))]
"TARGET_ALTIVEC"
- "
{
rtx neg0;
@@ -3871,7 +3844,7 @@ (define_expand "altivec_negv4sf2"
gen_lowpart (V4SFmode, neg0), operands[1]));
DONE;
-}")
+})
;; Vector reverse elements
(define_expand "altivec_vreve<mode>2"
@@ -3973,56 +3946,52 @@ (define_expand "vec_unpacks_float_hi_v8hi"
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacks_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacku_float_hi_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacku_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
\f
;; Power8/power9 vector instructions encoded as Altivec instructions
diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md
index 066518d..780ad17 100644
--- a/gcc/config/rs6000/darwin.md
+++ b/gcc/config/rs6000/darwin.md
@@ -31,28 +31,27 @@ (define_insn "movdf_low_si"
(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
- "*
{
switch (which_alternative)
{
case 0:
- return \"lfd %0,lo16(%2)(%1)\";
+ return "lfd %0,lo16(%2)(%1)";
case 1:
{
if (TARGET_POWERPC64 && TARGET_32BIT)
/* Note, old assemblers didn't support relocation here. */
- return \"ld %0,lo16(%2)(%1)\";
+ return "ld %0,lo16(%2)(%1)";
else
{
- output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
- output_asm_insn (\"lwz %L0,4(%0)\", operands);
- return (\"lwz %0,0(%0)\");
+ output_asm_insn ("la %0,lo16(%2)(%1)", operands);
+ output_asm_insn ("lwz %L0,4(%0)", operands);
+ return ("lwz %0,0(%0)");
}
}
default:
gcc_unreachable ();
}
-}"
+}
[(set_attr "type" "load")
(set_attr "length" "4,12")])
@@ -62,18 +61,17 @@ (define_insn "movdf_low_di"
(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
- "*
{
switch (which_alternative)
{
case 0:
- return \"lfd %0,lo16(%2)(%1)\";
+ return "lfd %0,lo16(%2)(%1)";
case 1:
- return \"ld %0,lo16(%2)(%1)\";
+ return "ld %0,lo16(%2)(%1)";
default:
gcc_unreachable ();
}
-}"
+}
[(set_attr "type" "load")
(set_attr "length" "4,4")])
@@ -262,7 +260,7 @@ (define_insn "load_macho_picbase_si"
#else
gcc_unreachable ();
#endif
- return "bcl 20,31,%0\\n%0:";
+ return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
@@ -279,7 +277,7 @@ (define_insn "load_macho_picbase_di"
#else
gcc_unreachable ();
#endif
- return "bcl 20,31,%0\\n%0:";
+ return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
@@ -408,14 +406,14 @@ (define_insn "reload_macho_picbase_si"
{
static char tmp[64];
const char *cnam = machopic_get_function_picbase ();
- snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
+ snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
return tmp;
}
else
#else
gcc_unreachable ();
#endif
- return "bcl 20,31,%0\\n%0:";
+ return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
@@ -432,14 +430,14 @@ (define_insn "reload_macho_picbase_di"
{
static char tmp[64];
const char *cnam = machopic_get_function_picbase ();
- snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
+ snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam);
return tmp;
}
else
#else
gcc_unreachable ();
#endif
- return "bcl 20,31,%0\\n%0:";
+ return "bcl 20,31,%0\n%0:";
}
[(set_attr "type" "branch")
(set_attr "cannot_copy" "yes")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5f44d80..999aa37 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2595,7 +2595,6 @@ (define_split
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -2650,7 +2649,7 @@ (define_split
emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32)));
emit_insn (gen_iordi3 (dest, dest, op3));
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
@@ -2659,7 +2658,6 @@ (define_split
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -2713,7 +2711,7 @@ (define_split
emit_insn (gen_bswapsi2 (word1, op3_si));
}
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -2722,7 +2720,6 @@ (define_split
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -2740,7 +2737,7 @@ (define_split
emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
emit_insn (gen_iordi3 (dest, dest, op3));
DONE;
-}")
+})
(define_insn "bswapdi2_32bit"
[(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,?&r")
@@ -2756,7 +2753,6 @@ (define_split
(clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -2801,7 +2797,7 @@ (define_split
thus allowing us to omit an early clobber on the output. */
emit_insn (gen_bswapsi2 (dest1, word2));
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
@@ -2809,7 +2805,6 @@ (define_split
(clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -2850,7 +2845,7 @@ (define_split
emit_insn (gen_bswapsi2 (word2, src1));
emit_insn (gen_bswapsi2 (word1, src2));
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
@@ -2858,7 +2853,6 @@ (define_split
(clobber (match_operand:SI 2 "" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -2870,7 +2864,7 @@ (define_split
emit_insn (gen_bswapsi2 (dest1, src2));
emit_insn (gen_bswapsi2 (dest2, src1));
DONE;
-}")
+})
(define_insn "mul<mode>3"
@@ -4972,13 +4966,12 @@ (define_expand "mov<mode>cc"
(match_operand:GPR 2 "gpc_reg_operand" "")
(match_operand:GPR 3 "gpc_reg_operand" "")))]
"TARGET_ISEL"
- "
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
;; We use the BASE_REGS for the isel input operands because, if rA is
;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
@@ -5053,13 +5046,12 @@ (define_expand "mov<mode>cc"
(match_operand:SFDF 2 "gpc_reg_operand" "")
(match_operand:SFDF 3 "gpc_reg_operand" "")))]
"TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
- "
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
(define_insn "*fsel<SFDF:mode><SFDF2:mode>4"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=&<SFDF:rreg2>")
@@ -5193,7 +5185,6 @@ (define_insn_and_split "floatsi<mode>2_lfiwax"
"#"
""
[(pc)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -5221,7 +5212,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax"
}
emit_insn (gen_floatdi<mode>2 (dest, tmp));
DONE;
-}"
+}
[(set_attr "length" "12")
(set_attr "type" "fpload")])
@@ -5235,7 +5226,6 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
"#"
""
[(pc)]
- "
{
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
@@ -5246,7 +5236,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
emit_insn (gen_lfiwax (operands[2], operands[1]));
emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
@@ -5270,7 +5260,6 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx"
"#"
""
[(pc)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
@@ -5298,7 +5287,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx"
}
emit_insn (gen_floatdi<mode>2 (dest, tmp));
DONE;
-}"
+}
[(set_attr "length" "12")
(set_attr "type" "fpload")])
@@ -5312,7 +5301,6 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
"#"
""
[(pc)]
- "
{
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
@@ -5323,7 +5311,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
emit_insn (gen_lfiwzx (operands[2], operands[1]));
emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
@@ -5341,7 +5329,6 @@ (define_expand "floatsidf2"
(clobber (match_dup 5))
(clobber (match_dup 6))])]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
@@ -5365,7 +5352,7 @@ (define_expand "floatsidf2"
operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
operands[5] = gen_reg_rtx (DFmode);
operands[6] = gen_reg_rtx (SImode);
-}")
+})
(define_insn_and_split "*floatsidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
@@ -5379,7 +5366,6 @@ (define_insn_and_split "*floatsidf2_internal"
"#"
""
[(pc)]
- "
{
rtx lowword, highword;
gcc_assert (MEM_P (operands[4]));
@@ -5395,7 +5381,7 @@ (define_insn_and_split "*floatsidf2_internal"
emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE;
-}"
+}
[(set_attr "length" "24")
(set_attr "type" "fp")])
@@ -5409,7 +5395,6 @@ (define_expand "floatunssisf2"
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
- "
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
@@ -5425,7 +5410,7 @@ (define_expand "floatunssisf2"
emit_insn (gen_floatdisf2 (operands[0], dreg));
DONE;
}
-}")
+})
(define_expand "floatunssidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
@@ -5435,7 +5420,6 @@ (define_expand "floatunssidf2"
(clobber (match_dup 4))
(clobber (match_dup 5))])]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
@@ -5458,7 +5442,7 @@ (define_expand "floatunssidf2"
operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
operands[5] = gen_reg_rtx (DFmode);
-}")
+})
(define_insn_and_split "*floatunssidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
@@ -5472,7 +5456,6 @@ (define_insn_and_split "*floatunssidf2_internal"
"#"
""
[(pc)]
- "
{
rtx lowword, highword;
gcc_assert (MEM_P (operands[4]));
@@ -5486,7 +5469,7 @@ (define_insn_and_split "*floatunssidf2_internal"
emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE;
-}"
+}
[(set_attr "length" "20")
(set_attr "type" "fp")])
@@ -5597,7 +5580,6 @@ (define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
- "
{
if (!TARGET_P8_VECTOR)
{
@@ -5614,7 +5596,7 @@ (define_expand "fix_trunc<mode>si2"
}
DONE;
}
-}")
+})
; Like the convert to float patterns, this insn must be split before
; register allocation so that it can allocate the memory slot if it
@@ -5671,7 +5653,6 @@ (define_insn_and_split "fix_trunc<mode>si2_internal"
"#"
""
[(pc)]
- "
{
rtx lowword;
gcc_assert (MEM_P (operands[3]));
@@ -5681,7 +5662,7 @@ (define_insn_and_split "fix_trunc<mode>si2_internal"
emit_move_insn (operands[3], operands[2]);
emit_move_insn (operands[0], lowword);
DONE;
-}"
+}
[(set_attr "length" "16")
(set_attr "type" "fp")])
@@ -5759,14 +5740,13 @@ (define_expand "fixuns_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
- "
{
if (!TARGET_P8_VECTOR)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
@@ -6034,7 +6014,6 @@ (define_expand "floatsisf2"
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
- "
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
@@ -6057,7 +6036,7 @@ (define_expand "floatsisf2"
emit_insn (gen_floatdisf2 (operands[0], dreg));
DONE;
}
-}")
+})
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
@@ -6121,7 +6100,6 @@ (define_expand "floatdisf2"
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
- "
{
if (!TARGET_FCFIDS)
{
@@ -6136,7 +6114,7 @@ (define_expand "floatdisf2"
emit_insn (gen_floatdisf2_internal1 (operands[0], val));
DONE;
}
-}")
+})
(define_insn "floatdisf2_fcfids"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
@@ -6157,12 +6135,11 @@ (define_insn_and_split "*floatdisf2_mem"
"#"
"&& reload_completed"
[(pc)]
- "
{
emit_move_insn (operands[2], operands[1]);
emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")])
;; This is not IEEE compliant if rounding mode is "round to nearest".
@@ -6210,11 +6187,10 @@ (define_expand "floatdisf2_internal2"
(set (match_dup 0) (match_dup 1))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& !TARGET_FCFIDS"
- "
{
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (CCUNSmode);
-}")
+})
(define_expand "floatunsdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -6242,12 +6218,11 @@ (define_insn_and_split "*floatunsdisf2_mem"
"#"
"&& reload_completed"
[(pc)]
- "
{
emit_move_insn (operands[2], operands[1]);
emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
\f
@@ -6670,7 +6645,6 @@ (define_expand "movsi_got"
(unspec:SI [(match_operand:SI 1 "got_operand" "")
(match_dup 2)] UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1"
- "
{
if (GET_CODE (operands[1]) == CONST)
{
@@ -6691,7 +6665,7 @@ (define_expand "movsi_got"
}
operands[2] = rs6000_got_register (operands[1]);
-}")
+})
(define_insn "*movsi_got_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -6975,13 +6949,12 @@ (define_split
(set (match_dup 0)
(ior:SI (match_dup 0)
(match_dup 3)))]
- "
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
-}")
+})
;; Split loading -128..127 to use XXSPLITB and VEXTSW2D
(define_split
@@ -7030,7 +7003,10 @@ (define_expand "mov<mode>"
[(set (match_operand:INT 0 "general_operand" "")
(match_operand:INT 1 "any_operand" ""))]
""
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
;; MR LHZ/LBZ LXSI*ZX STH/STB STXSI*X LI
;; XXLOR load 0 load -1 VSPLTI* # MFVSRWZ
@@ -7137,7 +7113,10 @@ (define_expand "mov<mode>"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
(match_operand:FMOVE32 1 "any_operand" ""))]
"<fmove_ok>"
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
(define_split
[(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
@@ -7148,7 +7127,6 @@ (define_split
&& GET_CODE (SUBREG_REG (operands[0])) == REG
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 3))]
- "
{
long l;
@@ -7160,7 +7138,7 @@ (define_split
operands[2] = gen_lowpart (SImode, operands[0]);
operands[3] = gen_int_mode (l, SImode);
-}")
+})
;; Originally, we tried to keep movsf and movsd common, but the differences
;; addressing was making it rather difficult to hide with mode attributes. In
@@ -7334,7 +7312,10 @@ (define_expand "mov<mode>"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
(match_operand:FMOVE64 1 "any_operand" ""))]
""
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
@@ -7346,7 +7327,6 @@ (define_split
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 1))]
- "
{
int endian = (WORDS_BIG_ENDIAN == 0);
HOST_WIDE_INT value = INTVAL (operands[1]);
@@ -7355,7 +7335,7 @@ (define_split
operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
operands[4] = GEN_INT (value >> 32);
operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
-}")
+})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
@@ -7367,7 +7347,6 @@ (define_split
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
- "
{
int endian = (WORDS_BIG_ENDIAN == 0);
long l[2];
@@ -7378,7 +7357,7 @@ (define_split
operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
operands[4] = gen_int_mode (l[endian], SImode);
operands[5] = gen_int_mode (l[1 - endian], SImode);
-}")
+})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
@@ -7389,7 +7368,6 @@ (define_split
&& GET_CODE (SUBREG_REG (operands[0])) == REG
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 3))]
- "
{
int endian = (WORDS_BIG_ENDIAN == 0);
long l[2];
@@ -7403,7 +7381,7 @@ (define_split
| ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
operands[3] = gen_int_mode (val, DImode);
-}")
+})
;; Don't have reload use general registers to load a constant. It is
;; less efficient than loading the constant into an FP register, since
@@ -7511,7 +7489,10 @@ (define_expand "mov<mode>"
[(set (match_operand:FMOVE128 0 "general_operand" "")
(match_operand:FMOVE128 1 "any_operand" ""))]
""
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
;; It's important to list Y->r and r->Y before r->r because otherwise
;; reload, given m->r, will try to pick r->r and reload it, which
@@ -7897,7 +7878,6 @@ (define_expand "neg<mode>2"
(neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
- "
{
if (FLOAT128_IEEE_P (<MODE>mode))
{
@@ -7931,19 +7911,18 @@ (define_expand "neg<mode>2"
}
DONE;
}
-}")
+})
(define_insn "neg<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d")
(neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
- "*
{
if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
- return \"fneg %L0,%L1\;fneg %0,%1\";
+ return "fneg %L0,%L1\;fneg %0,%1";
else
- return \"fneg %0,%1\;fneg %L0,%L1\";
-}"
+ return "fneg %0,%1\;fneg %L0,%L1";
+}
[(set_attr "type" "fpsimple")
(set_attr "length" "8")])
@@ -7952,7 +7931,6 @@ (define_expand "abs<mode>2"
(abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
- "
{
rtx label;
@@ -7991,7 +7969,7 @@ (define_expand "abs<mode>2"
FAIL;
emit_label (label);
DONE;
-}")
+})
(define_expand "abs<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "")
@@ -8004,7 +7982,6 @@ (define_expand "abs<mode>2_internal"
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
- "
{
const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
@@ -8012,7 +7989,7 @@ (define_expand "abs<mode>2_internal"
operands[4] = gen_reg_rtx (CCFPmode);
operands[5] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word);
operands[6] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word);
-}")
+})
\f
;; Generate IEEE 128-bit -0.0 (0x80000000000000000000000000000000) in a vector
@@ -8546,7 +8523,6 @@ (define_split
&& !direct_move_p (operands[0], operands[1])"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 1))]
- "
{
HOST_WIDE_INT value = INTVAL (operands[1]);
operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
@@ -8555,7 +8531,7 @@ (define_split
DImode);
operands[4] = GEN_INT (value >> 32);
operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
-}")
+})
(define_split
[(set (match_operand:DIFD 0 "nonimmediate_operand" "")
@@ -8659,13 +8635,12 @@ (define_split
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
- "
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
-}")
+})
(define_split
[(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
@@ -8673,13 +8648,12 @@ (define_split
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
- "
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
-}")
+})
(define_split
[(set (match_operand:DI 0 "altivec_register_operand" "")
@@ -8764,7 +8738,6 @@ (define_split
|| (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
- "
{
operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
<MODE>mode);
@@ -8782,7 +8755,7 @@ (define_split
}
else
FAIL;
-}")
+})
(define_split
[(set (match_operand:TI2 0 "nonimmediate_operand" "")
@@ -8800,7 +8773,6 @@ (define_expand "setmemsi"
(use (match_operand:SI 1 "" ""))
(use (match_operand:SI 3 "" ""))])]
""
- "
{
/* If value to set is not zero, use the library routine. */
if (operands[2] != const0_rtx)
@@ -8810,7 +8782,7 @@ (define_expand "setmemsi"
DONE;
else
FAIL;
-}")
+})
;; String compare N insn.
;; Argument 0 is the target (result)
@@ -8891,13 +8863,12 @@ (define_expand "movmemsi"
(use (match_operand:SI 2 "" ""))
(use (match_operand:SI 3 "" ""))])]
""
- "
{
if (expand_block_move (operands))
DONE;
else
FAIL;
-}")
+})
\f
;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also
@@ -9352,10 +9323,9 @@ (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
- "
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
@@ -9489,10 +9459,9 @@ (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 2)
(unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
- "
{
operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
@@ -9587,10 +9556,9 @@ (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
- "
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
@@ -9657,10 +9625,9 @@ (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
- "
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
@@ -9698,12 +9665,11 @@ (define_expand "tls_get_tpointer"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
- "
{
emit_insn (gen_tls_get_tpointer_internal ());
emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
DONE;
-}")
+})
(define_insn "tls_get_tpointer_internal"
[(set (reg:SI 3)
@@ -9717,14 +9683,13 @@ (define_expand "tls_get_addr<mode>"
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
(match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
- "
{
emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
emit_insn (gen_tls_get_addr_internal<mode> ());
emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
DONE;
-}")
+})
(define_insn "tls_get_addr_internal<mode>"
[(set (reg:P 3)
@@ -9759,8 +9724,8 @@ (define_expand "allocate_stack"
(set (reg 1)
(minus (reg 1) (match_dup 1)))]
""
- "
-{ rtx chain = gen_reg_rtx (Pmode);
+{
+ rtx chain = gen_reg_rtx (Pmode);
rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
rtx neg_op0;
rtx insn, par, set, mem;
@@ -9864,7 +9829,7 @@ (define_expand "allocate_stack"
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE;
-}")
+})
;; These patterns say how to save and restore the stack pointer. We need not
;; save the stack pointer at function level since we are careful to
@@ -9897,7 +9862,6 @@ (define_expand "restore_stack_block"
(set (match_operand 0 "register_operand" "")
(match_operand 1 "register_operand" ""))]
""
- "
{
rtvec p;
@@ -9909,14 +9873,13 @@ (define_expand "restore_stack_block"
RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
const0_rtx);
operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
-}")
+})
(define_expand "save_stack_nonlocal"
[(set (match_dup 3) (match_dup 4))
(set (match_operand 0 "memory_operand" "") (match_dup 3))
(set (match_dup 2) (match_operand 1 "register_operand" ""))]
""
- "
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
@@ -9925,7 +9888,7 @@ (define_expand "save_stack_nonlocal"
operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
operands[3] = gen_reg_rtx (Pmode);
operands[4] = gen_frame_mem (Pmode, operands[1]);
-}")
+})
(define_expand "restore_stack_nonlocal"
[(set (match_dup 2) (match_operand 1 "memory_operand" ""))
@@ -9934,7 +9897,6 @@ (define_expand "restore_stack_nonlocal"
(match_dup 6)
(set (match_operand 0 "register_operand" "") (match_dup 3))]
""
- "
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
rtvec p;
@@ -9949,7 +9911,7 @@ (define_expand "restore_stack_nonlocal"
RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
const0_rtx);
operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
-}")
+})
\f
;; TOC register handling.
@@ -9960,16 +9922,15 @@ (define_insn "load_toc_aix_si"
(unspec:SI [(const_int 0)] UNSPEC_TOC))
(use (reg:SI 2))])]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
- "*
{
char buf[30];
extern int need_toc_init;
need_toc_init = 1;
- ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
+ ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
operands[2] = gen_rtx_REG (Pmode, 2);
- return \"lwz %0,%1(%2)\";
-}"
+ return "lwz %0,%1(%2)";
+}
[(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
@@ -9979,19 +9940,18 @@ (define_insn "load_toc_aix_di"
(unspec:DI [(const_int 0)] UNSPEC_TOC))
(use (reg:DI 2))])]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
- "*
{
char buf[30];
extern int need_toc_init;
need_toc_init = 1;
- ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
+ ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC",
!TARGET_ELF || !TARGET_MINIMAL_TOC);
if (TARGET_ELF)
- strcat (buf, \"@toc\");
+ strcat (buf, "@toc");
operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
operands[2] = gen_rtx_REG (Pmode, 2);
- return \"ld %0,%1(%2)\";
-}"
+ return "ld %0,%1(%2)";
+}
[(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
@@ -10018,7 +9978,7 @@ (define_insn "load_toc_v4_PIC_1_normal"
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
- "bcl 20,31,%0\\n%0:"
+ "bcl 20,31,%0\n%0:"
[(set_attr "type" "branch")
(set_attr "length" "4")
(set_attr "cannot_copy" "yes")])
@@ -10029,15 +9989,14 @@ (define_insn "load_toc_v4_PIC_1_476"
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
- "*
{
char name[32];
static char templ[32];
get_ppc476_thunk_name (name);
- sprintf (templ, \"bl %s\\n%%0:\", name);
+ sprintf (templ, "bl %s\n%%0:", name);
return templ;
-}"
+}
[(set_attr "type" "branch")
(set_attr "length" "4")
(set_attr "cannot_copy" "yes")])
@@ -10069,15 +10028,14 @@ (define_insn "load_toc_v4_PIC_1b_476"
UNSPEC_TOCPTR))
(match_dup 1)]
"TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
- "*
{
char name[32];
static char templ[32];
get_ppc476_thunk_name (name);
- sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
+ sprintf (templ, "bl %s\;b $+8\;.long %%0-$", name);
return templ;
-}"
+}
[(set_attr "type" "branch")
(set_attr "length" "16")])
@@ -10123,7 +10081,6 @@ (define_expand "builtin_setjmp_receiver"
"(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
|| (TARGET_TOC && TARGET_MINIMAL_TOC)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
- "
{
#if TARGET_MACHO
if (DEFAULT_ABI == ABI_DARWIN)
@@ -10134,7 +10091,7 @@ (define_expand "builtin_setjmp_receiver"
char tmplab[20];
crtl->uses_pic_offset_table = 1;
- ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
+ ASM_GENERATE_INTERNAL_LABEL(tmplab, "LSJR",
CODE_LABEL_NUMBER (operands[0]));
tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
@@ -10146,7 +10103,7 @@ (define_expand "builtin_setjmp_receiver"
#endif
rs6000_emit_load_toc_table (FALSE);
DONE;
-}")
+})
;; Largetoc support
(define_insn "*largetoc_high"
@@ -10236,7 +10193,6 @@ (define_expand "call"
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNO))])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
@@ -10271,7 +10227,7 @@ (define_expand "call"
gcc_unreachable ();
}
}
-}")
+})
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
@@ -10280,7 +10236,6 @@ (define_expand "call_value"
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNO))])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
@@ -10315,7 +10270,7 @@ (define_expand "call_value"
gcc_unreachable ();
}
}
-}")
+})
;; Call to function in current module. No TOC pointer reload needed.
;; Operand2 is nonzero if we are using the V.4 calling sequence and
@@ -10329,16 +10284,15 @@ (define_insn "*call_local32"
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -10348,16 +10302,15 @@ (define_insn "*call_local64"
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -10368,16 +10321,15 @@ (define_insn "*call_value_local32"
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -10389,16 +10341,15 @@ (define_insn "*call_value_local64"
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -10772,7 +10723,6 @@ (define_expand "untyped_call"
(match_operand 1 "" "")
(match_operand 2 "" "")])]
""
- "
{
int i;
@@ -10791,7 +10741,7 @@ (define_expand "untyped_call"
emit_insn (gen_blockage ());
DONE;
-}")
+})
;; sibling call patterns
(define_expand "sibcall"
@@ -10800,7 +10750,6 @@ (define_expand "sibcall"
(use (match_operand 2 "" ""))
(simple_return)])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
@@ -10817,7 +10766,7 @@ (define_expand "sibcall"
rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
DONE;
}
-}")
+})
(define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "register_operand" "")
@@ -10826,7 +10775,6 @@ (define_expand "sibcall_value"
(use (match_operand 3 "" ""))
(simple_return)])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
@@ -10843,7 +10791,7 @@ (define_expand "sibcall_value"
rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
DONE;
}
-}")
+})
(define_insn "*sibcall_local32"
[(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
@@ -10851,16 +10799,15 @@ (define_insn "*sibcall_local32"
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(simple_return)]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -10870,16 +10817,15 @@ (define_insn "*sibcall_local64"
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(simple_return)]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -10890,16 +10836,15 @@ (define_insn "*sibcall_value_local32"
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(simple_return)]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -10910,16 +10855,15 @@ (define_insn "*sibcall_value_local64"
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(simple_return)]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
@@ -11121,7 +11065,6 @@ (define_expand "cbranch<mode>4"
(match_operand:GPR 2 "reg_or_short_operand" "")]))
(use (match_operand 3 ""))]
""
- "
{
/* Take care of the possibility that operands[2] might be negative but
this might be a logical operation. That insn doesn't exist. */
@@ -11136,7 +11079,7 @@ (define_expand "cbranch<mode>4"
rs6000_emit_cbranch (<MODE>mode, operands);
DONE;
-}")
+})
(define_expand "cbranch<mode>4"
[(use (match_operator 0 "comparison_operator"
@@ -11144,11 +11087,10 @@ (define_expand "cbranch<mode>4"
(match_operand:FP 2 "gpc_reg_operand" "")]))
(use (match_operand 3 ""))]
""
- "
{
rs6000_emit_cbranch (<MODE>mode, operands);
DONE;
-}")
+})
(define_expand "cstore<mode>4_signed"
[(use (match_operator 1 "signed_comparison_operator"
@@ -11795,7 +11737,6 @@ (define_insn ""
(const_int 0)])
(match_operand:SI 3 "const_int_operand" "n")))]
""
- "*
{
int is_bit = ccr_bit (operands[1], 1);
int put_bit = 31 - (INTVAL (operands[3]) & 31);
@@ -11809,8 +11750,8 @@ (define_insn ""
operands[4] = GEN_INT (count);
operands[5] = GEN_INT (put_bit);
- return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
-}"
+ return "mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5";
+}
[(set (attr "type")
(cond [(match_test "TARGET_MFCRF")
(const_string "mfcrf")
@@ -11830,7 +11771,6 @@ (define_insn ""
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))]
""
- "*
{
int is_bit = ccr_bit (operands[1], 1);
int put_bit = 31 - (INTVAL (operands[3]) & 31);
@@ -11838,7 +11778,7 @@ (define_insn ""
/* Force split for non-cc0 compare. */
if (which_alternative == 1)
- return \"#\";
+ return "#";
if (is_bit >= put_bit)
count = is_bit - put_bit;
@@ -11848,8 +11788,8 @@ (define_insn ""
operands[5] = GEN_INT (count);
operands[6] = GEN_INT (put_bit);
- return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
-}"
+ return "mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6";
+}
[(set_attr "type" "shift")
(set_attr "dot" "yes")
(set_attr "length" "8,16")])
@@ -12433,7 +12373,6 @@ (define_insn_and_split ""
""
[(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
(match_dup 5)))]
- "
{
int positive_1, positive_2;
@@ -12469,7 +12408,7 @@ (define_insn_and_split ""
{
operands[5] = const1_rtx;
}
-}")
+})
;; Unconditional branch and return.
@@ -12894,7 +12833,6 @@ (define_insn "*movesi_from_cr_one"
(match_operand 3 "immediate_operand" "n")]
UNSPEC_MOVESI_FROM_CR))])]
"TARGET_MFCRF"
- "*
{
int mask = 0;
int i;
@@ -12902,10 +12840,10 @@ (define_insn "*movesi_from_cr_one"
{
mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
operands[4] = GEN_INT (mask);
- output_asm_insn (\"mfcr %1,%4\", operands);
+ output_asm_insn ("mfcr %1,%4", operands);
}
- return \"\";
-}"
+ return "";
+}
[(set_attr "type" "mfcrf")])
;; Don't include the volatile CRs since their values are not used wrt CR save
@@ -13077,15 +13015,14 @@ (define_insn "*movsi_to_cr"
(match_operand 3 "immediate_operand" "n")]
UNSPEC_MOVESI_TO_CR))])]
""
- "*
{
int mask = 0;
int i;
for (i = 0; i < XVECLEN (operands[0], 0); i++)
mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
operands[4] = GEN_INT (mask);
- return \"mtcrf %4,%2\";
-}"
+ return "mtcrf %4,%2";
+}
[(set_attr "type" "mtcr")])
(define_insn "*mtcrfsi"
@@ -13275,14 +13212,13 @@ (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
(define_expand "eh_return"
[(use (match_operand 0 "general_operand" ""))]
""
- "
{
if (TARGET_32BIT)
emit_insn (gen_eh_set_lr_si (operands[0]));
else
emit_insn (gen_eh_set_lr_di (operands[0]));
DONE;
-}")
+})
; We can't expand this before we know where the link register is stored.
(define_insn "eh_set_lr_<mode>"
@@ -13297,23 +13233,21 @@ (define_split
(clobber (match_scratch 1 ""))]
"reload_completed"
[(const_int 0)]
- "
{
rs6000_emit_eh_reg_restore (operands[0], operands[1]);
DONE;
-}")
+})
(define_insn "prefetch"
[(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
""
- "*
{
if (GET_CODE (operands[0]) == REG)
- return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
- return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
-}"
+ return INTVAL (operands[1]) ? "dcbtst 0,%0" : "dcbt 0,%0";
+ return INTVAL (operands[1]) ? "dcbtst %a0" : "dcbt %a0";
+}
[(set_attr "type" "load")])
\f
;; Handle -fsplit-stack.
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 3bcf087..0a58a75 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -181,7 +181,6 @@ (define_expand "vector_altivec_load_<mode>"
[(set (match_operand:VEC_M 0 "vfloat_operand" "")
(match_operand:VEC_M 1 "memory_operand" ""))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
@@ -198,13 +197,12 @@ (define_expand "vector_altivec_load_<mode>"
emit_insn (gen_altivec_lvx_<mode>_1op (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "vector_altivec_store_<mode>"
[(set (match_operand:VEC_M 0 "memory_operand" "")
(match_operand:VEC_M 1 "vfloat_operand" ""))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
@@ -221,7 +219,7 @@ (define_expand "vector_altivec_store_<mode>"
emit_insn (gen_altivec_stvx_<mode>_1op (operands[1], operands[0]));
DONE;
}
-}")
+})
\f
@@ -272,27 +270,25 @@ (define_expand "neg<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "abs<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "smin<mode>3"
[(set (match_operand:VEC_F 0 "register_operand" "")
@@ -369,7 +365,6 @@ (define_expand "vector_copysign<mode>3"
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
@@ -377,7 +372,7 @@ (define_expand "vector_copysign<mode>3"
operands[2]));
DONE;
}
-}")
+})
\f
;; Vector comparisons
@@ -390,14 +385,13 @@ (define_expand "vcond<mode><mode>"
(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcond<mode><mode>"
[(set (match_operand:VEC_I 0 "vint_operand")
@@ -408,14 +402,13 @@ (define_expand "vcond<mode><mode>"
(match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
(match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcondv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
@@ -427,14 +420,13 @@ (define_expand "vcondv4sfv4si"
(match_operand:V4SF 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcondv4siv4sf"
[(set (match_operand:V4SI 0 "vint_operand" "")
@@ -446,14 +438,13 @@ (define_expand "vcondv4siv4sf"
(match_operand:V4SI 2 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcondv2dfv2di"
[(set (match_operand:V2DF 0 "vfloat_operand")
@@ -500,14 +491,13 @@ (define_expand "vcondu<mode><mode>"
(match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
(match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vconduv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
@@ -519,14 +509,13 @@ (define_expand "vconduv4sfv4si"
(match_operand:V4SF 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vconduv2dfv2di"
[(set (match_operand:V2DF 0 "vfloat_operand")
@@ -575,10 +564,9 @@ (define_expand "vector_nlt<mode>"
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_expand "vector_gtu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
@@ -595,10 +583,9 @@ (define_expand "vector_nltu<mode>"
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_expand "vector_geu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
@@ -615,10 +602,9 @@ (define_expand "vector_ngt<mode>"
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_expand "vector_ngtu<mode>"
[(set (match_operand:VEC_I 3 "vlogical_operand" "")
@@ -627,10 +613,9 @@ (define_expand "vector_ngtu<mode>"
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_insn_and_split "*vector_uneq<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
@@ -669,11 +654,10 @@ (define_insn_and_split "*vector_ltgt<mode>"
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
- "
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
(define_insn_and_split "*vector_ordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
@@ -691,11 +675,10 @@ (define_insn_and_split "*vector_ordered<mode>"
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
- "
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
(define_insn_and_split "*vector_unordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
@@ -713,11 +696,10 @@ (define_insn_and_split "*vector_unordered<mode>"
(set (match_dup 0)
(and:VEC_F (not:VEC_F (match_dup 3))
(not:VEC_F (match_dup 4))))]
- "
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
;; which is in the reverse order that we want
@@ -1030,53 +1012,49 @@ (define_expand "float<VEC_int><mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
(define_expand "floatuns<VEC_int><mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
(define_expand "fix_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
(define_expand "fixuns_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
\f
;; Vector initialization, set, extract
@@ -1273,7 +1251,6 @@ (define_expand "vec_shr_<mode>"
(match_operand:VEC_L 1 "vlogical_operand" "")
(match_operand:QI 2 "reg_or_short_operand" "")]
"TARGET_ALTIVEC"
- "
{
rtx bitshift = operands[2];
rtx shift;
@@ -1315,7 +1292,7 @@ (define_expand "vec_shr_<mode>"
emit_insn (insn);
DONE;
-}")
+})
;; Expanders for rotate each element in a vector
(define_expand "vrotl<mode>3"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2fd0404..9249ce5 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -443,7 +443,6 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
(vec_select:<MODE>
(match_dup 2)
(parallel [(const_int 1) (const_int 0)])))]
- "
{
rtx mem = operands[1];
@@ -475,7 +474,6 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
- "
[(set_attr "type" "vecload")
(set_attr "length" "8")])
@@ -495,7 +493,6 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
(match_dup 2)
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
- "
{
rtx mem = operands[1];
@@ -527,7 +524,6 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
- "
[(set_attr "type" "vecload")
(set_attr "length" "8")])
@@ -551,7 +547,6 @@ (define_insn_and_split "*vsx_le_perm_load_v8hi"
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
- "
{
rtx mem = operands[1];
@@ -583,7 +578,6 @@ (define_insn_and_split "*vsx_le_perm_load_v8hi"
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
- "
[(set_attr "type" "vecload")
(set_attr "length" "8")])
@@ -615,7 +609,6 @@ (define_insn_and_split "*vsx_le_perm_load_v16qi"
(const_int 2) (const_int 3)
(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
- "
{
rtx mem = operands[1];
@@ -647,7 +640,6 @@ (define_insn_and_split "*vsx_le_perm_load_v16qi"
operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0])
: operands[0];
}
- "
[(set_attr "type" "vecload")
(set_attr "length" "8")])
@@ -1037,7 +1029,6 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
#"
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
[(const_int 0)]
- "
{
rtx tmp = (can_create_pseudo_p ()
? gen_reg_rtx_and_attrs (operands[0])
@@ -1046,7 +1037,6 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
rs6000_emit_le_vsx_permute (operands[0], tmp, <MODE>mode);
DONE;
}
- "
[(set_attr "type" "vecload,load")
(set_attr "length" "8,8")])
@@ -1640,7 +1630,6 @@ (define_insn_and_split "vsx_mul_v2di"
"#"
"VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
- "
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -1668,7 +1657,7 @@ (define_insn_and_split "vsx_mul_v2di"
}
emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
DONE;
-}"
+}
[(set_attr "type" "mul")])
(define_insn "*vsx_div<mode>3"
@@ -1690,7 +1679,6 @@ (define_insn_and_split "vsx_div_v2di"
"#"
"VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
- "
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -1726,7 +1714,7 @@ (define_insn_and_split "vsx_div_v2di"
}
emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
DONE;
-}"
+}
[(set_attr "type" "div")])
(define_insn_and_split "vsx_udiv_v2di"
@@ -1738,7 +1726,6 @@ (define_insn_and_split "vsx_udiv_v2di"
"#"
"VECTOR_MEM_VSX_P (V2DImode) && !reload_completed"
[(const_int 0)]
- "
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -1774,7 +1761,7 @@ (define_insn_and_split "vsx_udiv_v2di"
}
emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
DONE;
-}"
+}
[(set_attr "type" "div")])
;; *tdiv* instruction returning the FG flag
@@ -4328,7 +4315,6 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v2df"
"#"
""
[(const_int 0)]
- "
{
rtx tmp = (GET_CODE (operands[2]) == SCRATCH)
? gen_reg_rtx (V2DFmode)
@@ -4336,7 +4322,7 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v2df"
emit_insn (gen_vsx_xxsldwi_v2df (tmp, operands[1], operands[1], const2_rtx));
emit_insn (gen_<VEC_reduc_rtx>v2df3 (operands[0], tmp, operands[1]));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "veccomplex")])
@@ -4351,7 +4337,6 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
"#"
""
[(const_int 0)]
- "
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -4375,7 +4360,7 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
emit_insn (gen_vsx_xxsldwi_v4sf (tmp4, tmp3, tmp3, GEN_INT (3)));
emit_insn (gen_<VEC_reduc_rtx>v4sf3 (op0, tmp4, tmp3));
DONE;
-}"
+}
[(set_attr "length" "16")
(set_attr "type" "veccomplex")])
@@ -4400,7 +4385,6 @@ (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
"#"
""
[(const_int 0)]
- "
{
rtx hi = gen_highpart (DFmode, operands[1]);
rtx lo = (GET_CODE (operands[2]) == SCRATCH)
@@ -4410,7 +4394,7 @@ (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
emit_insn (gen_vsx_extract_v2df (lo, operands[1], const1_rtx));
emit_insn (gen_<VEC_reduc_rtx>df3 (operands[0], hi, lo));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "veccomplex")])
@@ -4428,7 +4412,6 @@ (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v4sf_scalar"
"#"
""
[(const_int 0)]
- "
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@@ -4455,7 +4438,7 @@ (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v4sf_scalar"
emit_insn (gen_<VEC_reduc_rtx>v4sf3 (tmp5, tmp4, tmp3));
emit_insn (gen_vsx_xscvspdp_scalar2 (op0, tmp5));
DONE;
-}"
+}
[(set_attr "length" "20")
(set_attr "type" "veccomplex")])
--
1.8.3.1
^ permalink raw reply [flat|nested] 2+ messages in thread* [PATCH 2/2] rs6000: Delete meaningless arguments to define_{expand,split,peephole2}
2018-02-22 1:09 [PATCH 1/2] rs6000: Use brace blocks in define_insn Segher Boessenkool
@ 2018-02-22 1:09 ` Segher Boessenkool
0 siblings, 0 replies; 2+ messages in thread
From: Segher Boessenkool @ 2018-02-22 1:09 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This removes the (usually empty) constraint arguments to define_expand,
define_split, and define_peephole2: this argument is meaningless and
just noise.
Tested on powerpc64-linux {-m64,-m32}. Committing to trunk.
Segher
2018-02-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Delete contraint arguments to
define_expand, define_split, and define_peephole2, and in
define_insn_and_split if always unused.
* config/rs6000/darwin.md: Ditto.
* config/rs6000/dfp.md: Ditto.
* config/rs6000/rs6000.md: Ditto.
* config/rs6000/sync.md: Ditto.
* config/rs6000/vector.md: Ditto.
* config/rs6000/vsx.md: Ditto.
---
gcc/config/rs6000/altivec.md | 222 ++++++------
gcc/config/rs6000/darwin.md | 30 +-
gcc/config/rs6000/dfp.md | 6 +-
gcc/config/rs6000/rs6000.md | 780 +++++++++++++++++++++----------------------
gcc/config/rs6000/sync.md | 92 ++---
gcc/config/rs6000/vector.md | 404 +++++++++++-----------
gcc/config/rs6000/vsx.md | 134 ++++----
7 files changed, 834 insertions(+), 834 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 55a9f53..2759f2d 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -291,8 +291,8 @@ (define_insn "*altivec_movti"
;; Load up a vector with the most significant bit set by loading up -1 and
;; doing a shift left
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_msb" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_msb"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(const_int 0)]
{
@@ -318,8 +318,8 @@ (define_split
})
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_add_self" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_add_self"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(set (match_dup 0) (match_dup 3))
(set (match_dup 0) (match_dup 4))]
@@ -347,8 +347,8 @@ (define_split
})
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_vsldoi" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_vsldoi"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))
@@ -692,9 +692,9 @@ (define_insn "*altivec_fmav4sf4"
;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
(define_expand "altivec_mulv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (fma:V4SF (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "register_operand" "")
+ [(set (match_operand:V4SF 0 "register_operand")
+ (fma:V4SF (match_operand:V4SF 1 "register_operand")
+ (match_operand:V4SF 2 "register_operand")
(match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
@@ -728,9 +728,9 @@ (define_insn "mulv4si3_p8"
[(set_attr "type" "veccomplex")])
(define_expand "mulv4si3"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero;
@@ -780,9 +780,9 @@ (define_expand "mulv4si3"
})
(define_expand "mulv8hi3"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero = gen_reg_rtx (V8HImode);
@@ -940,9 +940,9 @@ (define_insn "fmav8hi4"
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vmrghb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1004,9 +1004,9 @@ (define_insn "altivec_vmrghb_direct"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghh"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1060,9 +1060,9 @@ (define_insn "altivec_vmrghh_direct"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
@@ -1131,9 +1131,9 @@ (define_insn "*altivec_vmrghsf"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1195,9 +1195,9 @@ (define_insn "altivec_vmrglb_direct"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglh"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1251,9 +1251,9 @@ (define_insn "altivec_vmrglh_direct"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
@@ -1410,9 +1410,9 @@ (define_insn "p8_vmrgow_<mode>_direct"
[(set_attr "type" "vecperm")])
(define_expand "vec_widen_umult_even_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1423,9 +1423,9 @@ (define_expand "vec_widen_umult_even_v16qi"
})
(define_expand "vec_widen_smult_even_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1436,9 +1436,9 @@ (define_expand "vec_widen_smult_even_v16qi"
})
(define_expand "vec_widen_umult_even_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1449,9 +1449,9 @@ (define_expand "vec_widen_umult_even_v8hi"
})
(define_expand "vec_widen_smult_even_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1488,9 +1488,9 @@ (define_expand "vec_widen_smult_even_v4si"
})
(define_expand "vec_widen_umult_odd_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1501,9 +1501,9 @@ (define_expand "vec_widen_umult_odd_v16qi"
})
(define_expand "vec_widen_smult_odd_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1514,9 +1514,9 @@ (define_expand "vec_widen_smult_odd_v16qi"
})
(define_expand "vec_widen_umult_odd_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1527,9 +1527,9 @@ (define_expand "vec_widen_umult_odd_v8hi"
})
(define_expand "vec_widen_smult_odd_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1949,9 +1949,9 @@ (define_insn "altivec_vsumsws_direct"
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vspltb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1997,9 +1997,9 @@ (define_insn "altivec_vspltb_direct"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vsplth"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -2045,9 +2045,9 @@ (define_insn "altivec_vsplth_direct"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -2093,9 +2093,9 @@ (define_insn "altivec_vspltw_direct"
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltsf"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -2147,10 +2147,10 @@ (define_insn "*altivec_vrfiz"
[(set_attr "type" "vecfloat")])
(define_expand "altivec_vperm_<mode>"
- [(set (match_operand:VM 0 "register_operand" "")
- (unspec:VM [(match_operand:VM 1 "register_operand" "")
- (match_operand:VM 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:VM 0 "register_operand")
+ (unspec:VM [(match_operand:VM 1 "register_operand")
+ (match_operand:VM 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
@@ -2189,10 +2189,10 @@ (define_insn "altivec_vperm_v8hiv16qi"
(set_attr "length" "4")])
(define_expand "altivec_vperm_<mode>_uns"
- [(set (match_operand:VM 0 "register_operand" "")
- (unspec:VM [(match_operand:VM 1 "register_operand" "")
- (match_operand:VM 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:VM 0 "register_operand")
+ (unspec:VM [(match_operand:VM 1 "register_operand")
+ (match_operand:VM 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM_UNS))]
"TARGET_ALTIVEC"
{
@@ -2217,10 +2217,10 @@ (define_insn "*altivec_vperm_<mode>_uns_internal"
(set_attr "length" "4")])
(define_expand "vec_permv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
- (match_operand:V16QI 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand")
+ (match_operand:V16QI 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
@@ -2338,9 +2338,9 @@ (define_insn "altivec_vrefp"
[(set_attr "type" "vecfloat")])
(define_expand "altivec_copysign_v4sf3"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))
- (use (match_operand:V4SF 2 "register_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))
+ (use (match_operand:V4SF 2 "register_operand"))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
rtx mask = gen_reg_rtx (V4SImode);
@@ -2584,8 +2584,8 @@ (define_insn "altivec_dststt"
[(set_attr "type" "vecsimple")])
(define_expand "altivec_lvsl"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "memory_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "memory_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -2660,8 +2660,8 @@ (define_insn "altivec_lvsr_direct"
[(set_attr "type" "vecload")])
(define_expand "build_vector_mask_for_load"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
+ [(set (match_operand:V16QI 0 "register_operand")
+ (unspec:V16QI [(match_operand 1 "memory_operand")] UNSPEC_LVSR))]
"TARGET_ALTIVEC"
{
rtx addr;
@@ -3331,8 +3331,8 @@ (define_insn "*p9_neg<mode>2"
[(set_attr "type" "vecsimple")])
(define_expand "neg<mode>2"
- [(set (match_operand:VI2 0 "register_operand" "")
- (neg:VI2 (match_operand:VI2 1 "register_operand" "")))]
+ [(set (match_operand:VI2 0 "register_operand")
+ (neg:VI2 (match_operand:VI2 1 "register_operand")))]
"<VI_unit>"
{
if (!TARGET_P9_VECTOR || (<MODE>mode != V4SImode && <MODE>mode != V2DImode))
@@ -3828,8 +3828,8 @@ (define_expand "mulv16qi3"
})
(define_expand "altivec_negv4sf2"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx neg0;
@@ -3942,8 +3942,8 @@ (define_insn "altivec_stvrxl"
[(set_attr "type" "vecstore")])
(define_expand "vec_unpacks_float_hi_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
{
@@ -3955,8 +3955,8 @@ (define_expand "vec_unpacks_float_hi_v8hi"
})
(define_expand "vec_unpacks_float_lo_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
{
@@ -3968,8 +3968,8 @@ (define_expand "vec_unpacks_float_lo_v8hi"
})
(define_expand "vec_unpacku_float_hi_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
{
@@ -3981,8 +3981,8 @@ (define_expand "vec_unpacku_float_hi_v8hi"
})
(define_expand "vec_unpacku_float_lo_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
{
@@ -4498,13 +4498,13 @@ (define_insn "*cmpeqb_internal"
(define_expand "bcd<bcd_add_sub>_<code>"
[(parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
- (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
- (match_operand:V1TI 2 "register_operand" "")
- (match_operand:QI 3 "const_0_to_1_operand" "")]
+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand")
+ (match_operand:V1TI 2 "register_operand")
+ (match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB)
(match_dup 4)))
- (clobber (match_scratch:V1TI 5 ""))])
- (set (match_operand:SI 0 "register_operand" "")
+ (clobber (match_scratch:V1TI 5))])
+ (set (match_operand:SI 0 "register_operand")
(BCD_TEST:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
"TARGET_P8_VECTOR"
@@ -4519,10 +4519,10 @@ (define_expand "bcd<bcd_add_sub>_<code>"
;; a register class for CR6.
(define_peephole2
- [(parallel [(set (match_operand:V1TI 0 "register_operand" "")
- (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
- (match_operand:V1TI 2 "register_operand" "")
- (match_operand:QI 3 "const_0_to_1_operand" "")]
+ [(parallel [(set (match_operand:V1TI 0 "register_operand")
+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand")
+ (match_operand:V1TI 2 "register_operand")
+ (match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB))
(clobber (reg:CCFP CR6_REGNO))])
(parallel [(set (reg:CCFP CR6_REGNO)
@@ -4531,8 +4531,8 @@ (define_peephole2
(match_dup 2)
(match_dup 3)]
UNSPEC_BCD_ADD_SUB)
- (match_operand:V2DF 4 "zero_constant" "")))
- (clobber (match_operand:V1TI 5 "register_operand" ""))])]
+ (match_operand:V2DF 4 "zero_constant")))
+ (clobber (match_operand:V1TI 5 "register_operand"))])]
"TARGET_P8_VECTOR"
[(parallel [(set (match_dup 0)
(unspec:V1TI [(match_dup 1)
diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md
index 780ad17..48fd5b96 100644
--- a/gcc/config/rs6000/darwin.md
+++ b/gcc/config/rs6000/darwin.md
@@ -171,8 +171,8 @@ (define_insn "movdi_low_st"
;; Mach-O PIC trickery.
(define_expand "macho_high"
- [(set (match_operand 0 "" "")
- (high (match_operand 1 "" "")))]
+ [(set (match_operand 0 "")
+ (high (match_operand 1 "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
@@ -197,9 +197,9 @@ (define_insn "macho_high_di"
"lis %0,ha16(%1)")
(define_expand "macho_low"
- [(set (match_operand 0 "" "")
- (lo_sum (match_operand 1 "" "")
- (match_operand 2 "" "")))]
+ [(set (match_operand 0 "")
+ (lo_sum (match_operand 1 "")
+ (match_operand 2 "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
@@ -225,10 +225,10 @@ (define_insn "macho_low_di"
"la %0,lo16(%2)(%1)")
(define_split
- [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "short_cint_operand" "")))
- (match_operand:V4SI 2 "register_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand")
+ (match_operand:DI 1 "short_cint_operand")))
+ (match_operand:V4SI 2 "register_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_MACHO && TARGET_64BIT"
[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
(set (mem:V4SI (match_dup 3))
@@ -237,7 +237,7 @@ (define_split
(define_expand "load_macho_picbase"
[(set (reg:SI LR_REGNO)
- (unspec [(match_operand 0 "" "")]
+ (unspec [(match_operand 0 "")]
UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
@@ -284,10 +284,10 @@ (define_insn "load_macho_picbase_di"
(set_attr "length" "4")])
(define_expand "macho_correct_pic"
- [(set (match_operand 0 "" "")
- (plus (match_operand 1 "" "")
- (unspec [(match_operand 2 "" "")
- (match_operand 3 "" "")]
+ [(set (match_operand 0 "")
+ (plus (match_operand 1 "")
+ (unspec [(match_operand 2 "")
+ (match_operand 3 "")]
UNSPEC_MPIC_CORRECT)))]
"DEFAULT_ABI == ABI_DARWIN"
{
@@ -383,7 +383,7 @@ (define_insn "*call_value_nonlocal_darwin64"
(define_expand "reload_macho_picbase"
[(set (reg:SI LR_REGNO)
- (unspec [(match_operand 0 "" "")]
+ (unspec [(match_operand 0 "")]
UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 216251f..cd15aa8 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -344,11 +344,11 @@ (define_expand "dfptstsfi_<code>_<mode>"
[(set (match_dup 3)
(compare:CCFP
(unspec:D64_D128
- [(match_operand:SI 1 "const_int_operand" "n")
- (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
+ [(match_operand:SI 1 "const_int_operand")
+ (match_operand:D64_D128 2 "gpc_reg_operand")]
UNSPEC_DTSTSFI)
(match_dup 4)))
- (set (match_operand:SI 0 "register_operand" "")
+ (set (match_operand:SI 0 "register_operand")
(DFP_TEST:SI (match_dup 3)
(const_int 0)))
]
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 999aa37..0976d50 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1576,12 +1576,12 @@ (define_insn "dlmzb"
"dlmzb. %0,%1,%2")
(define_expand "strlensi"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unspec:SI [(match_operand:BLK 1 "general_operand" "")
- (match_operand:QI 2 "const_int_operand" "")
- (match_operand 3 "const_int_operand" "")]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unspec:SI [(match_operand:BLK 1 "general_operand")
+ (match_operand:QI 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")]
UNSPEC_DLMZB_STRLEN))
- (clobber (match_scratch:CC 4 "=x"))]
+ (clobber (match_scratch:CC 4))]
"TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
{
rtx result = operands[0];
@@ -1630,9 +1630,9 @@ (define_expand "strlensi"
;; Fixed-point arithmetic insns.
(define_expand "add<mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
- (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (plus:SDI (match_operand:SDI 1 "gpc_reg_operand")
+ (match_operand:SDI 2 "reg_or_add_cint_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
@@ -1805,9 +1805,9 @@ (define_insn_and_split "*add<mode>3_imm_dot2"
;; add should be last in case the result gets used in an address.
(define_split
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "non_add_cint_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (plus:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "non_add_cint_operand")))]
""
[(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
(set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
@@ -1950,8 +1950,8 @@ (define_insn "add<mode>3_carry_in_m1"
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (not:SDI (match_operand:SDI 1 "gpc_reg_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
@@ -2010,9 +2010,9 @@ (define_insn_and_split "*one_cmpl<mode>2_dot2"
(define_expand "sub<mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
- (match_operand:SDI 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (minus:SDI (match_operand:SDI 1 "reg_or_short_operand")
+ (match_operand:SDI 2 "gpc_reg_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
@@ -2338,8 +2338,8 @@ (define_expand "ffs<mode>2"
(define_expand "popcount<mode>2"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
"TARGET_POPCNTB || TARGET_POPCNTD"
{
rs6000_emit_popcount (operands[0], operands[1]);
@@ -2363,8 +2363,8 @@ (define_insn "popcntd<mode>2"
(define_expand "parity<mode>2"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
"TARGET_POPCNTB"
{
rs6000_emit_parity (operands[0], operands[1]);
@@ -2508,11 +2508,11 @@ (define_insn_and_split "bswapsi2_reg"
;; complex code.
(define_expand "bswapdi2"
- [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
+ [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand")
(bswap:DI
- (match_operand:DI 1 "reg_or_mem_operand" "")))
- (clobber (match_scratch:DI 2 ""))
- (clobber (match_scratch:DI 3 ""))])]
+ (match_operand:DI 1 "reg_or_mem_operand")))
+ (clobber (match_scratch:DI 2))
+ (clobber (match_scratch:DI 3))])]
""
{
rtx dest = operands[0];
@@ -2589,10 +2589,10 @@ (define_insn "*bswapdi2_64bit"
[(set_attr "length" "16,12,36")])
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
- (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
{
@@ -2652,10 +2652,10 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "indexed_or_indirect_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
{
@@ -2714,10 +2714,10 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
- (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:DI 2 "gpc_reg_operand"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
@@ -2748,9 +2748,9 @@ (define_insn "bswapdi2_32bit"
[(set_attr "length" "16,12,36")])
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
- (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand")))
+ (clobber (match_operand:SI 2 "gpc_reg_operand"))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
{
@@ -2800,9 +2800,9 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
+ [(set (match_operand:DI 0 "indexed_or_indirect_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:SI 2 "gpc_reg_operand"))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
{
@@ -2848,9 +2848,9 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_operand:SI 2 "" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (bswap:DI (match_operand:DI 1 "gpc_reg_operand")))
+ (clobber (match_operand:SI 2 ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
{
@@ -2877,9 +2877,9 @@ (define_insn "mul<mode>3"
mulli %0,%1,%2"
[(set_attr "type" "mul")
(set (attr "size")
- (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
+ (cond [(match_operand:GPR 2 "s8bit_cint_operand")
(const_string "8")
- (match_operand:GPR 2 "short_cint_operand" "")
+ (match_operand:GPR 2 "short_cint_operand")
(const_string "16")]
(const_string "<bits>")))])
@@ -3048,9 +3048,9 @@ (define_insn "udiv<mode>3"
;; modulus. If it isn't a power of two, force operands into register and do
;; a normal divide.
(define_expand "div<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "reg_or_cint_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (div:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "reg_or_cint_operand")))]
""
{
if (CONST_INT_P (operands[2])
@@ -3190,10 +3190,10 @@ (define_insn "umod<mode>3"
;; after a divide.
(define_peephole2
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "gpc_reg_operand" "")))
- (set (match_operand:GPR 3 "gpc_reg_operand" "")
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (div:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "gpc_reg_operand")))
+ (set (match_operand:GPR 3 "gpc_reg_operand")
(mod:GPR (match_dup 1)
(match_dup 2)))]
"TARGET_MODULO
@@ -3212,10 +3212,10 @@ (define_peephole2
(match_dup 3)))])
(define_peephole2
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "gpc_reg_operand" "")))
- (set (match_operand:GPR 3 "gpc_reg_operand" "")
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "gpc_reg_operand")))
+ (set (match_operand:GPR 3 "gpc_reg_operand")
(umod:GPR (match_dup 1)
(match_dup 2)))]
"TARGET_MODULO
@@ -3241,9 +3241,9 @@ (define_peephole2
;; those rotate-and-mask operations. Thus, the AND insns come first.
(define_expand "and<mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
- (match_operand:SDI 2 "reg_or_cint_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (and:SDI (match_operand:SDI 1 "gpc_reg_operand")
+ (match_operand:SDI 2 "reg_or_cint_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
@@ -3539,9 +3539,9 @@ (define_insn_and_split "*and<mode>3_2insn_dot2"
(define_expand "<code><mode>3"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
- (match_operand:SDI 2 "reg_or_cint_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand")
+ (match_operand:SDI 2 "reg_or_cint_operand")))]
""
{
if (<MODE>mode == DImode && !TARGET_POWERPC64)
@@ -3570,9 +3570,9 @@ (define_expand "<code><mode>3"
})
(define_split
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "non_logical_cint_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "non_logical_cint_operand")))]
""
[(set (match_dup 3)
(iorxor:GPR (match_dup 1)
@@ -4473,9 +4473,9 @@ (define_insn_and_split "*ashr<mode>3_dot2"
;; Builtins to replace a division to generate FRE reciprocal estimate
;; instructions and the necessary fixup instructions
(define_expand "recip<mode>3"
- [(match_operand:RECIPF 0 "gpc_reg_operand" "")
- (match_operand:RECIPF 1 "gpc_reg_operand" "")
- (match_operand:RECIPF 2 "gpc_reg_operand" "")]
+ [(match_operand:RECIPF 0 "gpc_reg_operand")
+ (match_operand:RECIPF 1 "gpc_reg_operand")
+ (match_operand:RECIPF 2 "gpc_reg_operand")]
"RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
{
rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
@@ -4488,9 +4488,9 @@ (define_expand "recip<mode>3"
;; We used to also check optimize_insn_for_speed_p () but problems with guessed
;; frequencies (pr68212/pr77536) yields that unreliable so it was removed.
(define_split
- [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
- (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
- (match_operand 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:RECIPF 0 "gpc_reg_operand")
+ (div:RECIPF (match_operand 1 "gpc_reg_operand")
+ (match_operand 2 "gpc_reg_operand")))]
"RS6000_RECIP_AUTO_RE_P (<MODE>mode)
&& can_create_pseudo_p () && flag_finite_math_only
&& !flag_trapping_math && flag_reciprocal_math"
@@ -4503,8 +4503,8 @@ (define_split
;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
;; appropriate fixup.
(define_expand "rsqrt<mode>2"
- [(match_operand:RECIPF 0 "gpc_reg_operand" "")
- (match_operand:RECIPF 1 "gpc_reg_operand" "")]
+ [(match_operand:RECIPF 0 "gpc_reg_operand")
+ (match_operand:RECIPF 1 "gpc_reg_operand")]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
{
rs6000_emit_swsqrt (operands[0], operands[1], 1);
@@ -4517,8 +4517,8 @@ (define_expand "rsqrt<mode>2"
;; -mupper-regs-{df,sf} option is enabled.
(define_expand "abs<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
@@ -4545,8 +4545,8 @@ (define_insn "*nabs<mode>2_fpr"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "neg<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
@@ -4561,9 +4561,9 @@ (define_insn "*neg<mode>2_fpr"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "add<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
@@ -4579,9 +4579,9 @@ (define_insn "*add<mode>3_fpr"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "sub<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
@@ -4597,9 +4597,9 @@ (define_insn "*sub<mode>3_fpr"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_expand "mul<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN"
"")
@@ -4615,9 +4615,9 @@ (define_insn "*mul<mode>3_fpr"
(set_attr "fp_type" "fp_mul_<Fs>")])
(define_expand "div<mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
{
if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
@@ -4652,8 +4652,8 @@ (define_insn "*sqrt<mode>2_internal"
(set_attr "fp_type" "fp_sqrt_<Fs>")])
(define_expand "sqrt<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
&& (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
{
@@ -4741,8 +4741,8 @@ (define_insn "*extendsfdf2_snan"
[(set_attr "type" "fp")])
(define_expand "truncdfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"")
@@ -4760,12 +4760,12 @@ (define_insn "*truncdfsf2_fpr"
;; when little-endian.
(define_expand "signbit<mode>2"
[(set (match_dup 2)
- (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))
+ (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand")))
(set (match_dup 3)
(subreg:DI (match_dup 2) 0))
(set (match_dup 4)
(match_dup 5))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(match_dup 6))]
"TARGET_HARD_FLOAT
&& (!FLOAT128_IEEE_P (<MODE>mode)
@@ -4868,11 +4868,11 @@ (define_insn_and_split "*signbit<mode>2_dm_mem"
(define_expand "copysign<mode>3"
[(set (match_dup 3)
- (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))
(set (match_dup 4)
(neg:SFDF (abs:SFDF (match_dup 1))))
- (set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
+ (set (match_operand:SFDF 0 "gpc_reg_operand")
+ (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand")
(match_dup 5))
(match_dup 3)
(match_dup 4)))]
@@ -4922,9 +4922,9 @@ (define_insn "copysign<mode>3_fcpsgn"
;; to allow either DF/SF to use only traditional registers.
(define_expand "s<minmax><mode>3"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"TARGET_MINMAX_<MODE>"
{
rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
@@ -4948,9 +4948,9 @@ (define_insn "*s<minmax><mode>3_vsx"
;; instruction.
(define_insn_and_split "*s<minmax><mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
+ (match_operand:SFDF 2 "gpc_reg_operand")))]
"!TARGET_VSX && TARGET_MINMAX_<MODE>"
"#"
"&& 1"
@@ -4961,10 +4961,10 @@ (define_insn_and_split "*s<minmax><mode>3_fpr"
})
(define_expand "mov<mode>cc"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "")
- (if_then_else:GPR (match_operand 1 "comparison_operator" "")
- (match_operand:GPR 2 "gpc_reg_operand" "")
- (match_operand:GPR 3 "gpc_reg_operand" "")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand")
+ (if_then_else:GPR (match_operand 1 "comparison_operator")
+ (match_operand:GPR 2 "gpc_reg_operand")
+ (match_operand:GPR 3 "gpc_reg_operand")))]
"TARGET_ISEL"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
@@ -5041,10 +5041,10 @@ (define_insn "*isel_reversed_unsigned_<mode>"
;; Floating point conditional move
(define_expand "mov<mode>cc"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
- (if_then_else:SFDF (match_operand 1 "comparison_operator" "")
- (match_operand:SFDF 2 "gpc_reg_operand" "")
- (match_operand:SFDF 3 "gpc_reg_operand" "")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand")
+ (if_then_else:SFDF (match_operand 1 "comparison_operator")
+ (match_operand:SFDF 2 "gpc_reg_operand")
+ (match_operand:SFDF 3 "gpc_reg_operand")))]
"TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
@@ -5321,8 +5321,8 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
; then to have the insns split later (between sched1 and final).
(define_expand "floatsidf2"
- [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
+ [(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
+ (float:DF (match_operand:SI 1 "nonimmediate_operand")))
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 4))
@@ -5389,8 +5389,8 @@ (define_insn_and_split "*floatsidf2_internal"
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
(define_expand "floatunssisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
@@ -5413,8 +5413,8 @@ (define_expand "floatunssisf2"
})
(define_expand "floatunssidf2"
- [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
+ [(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
+ (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand")))
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 4))
@@ -5534,9 +5534,9 @@ (define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
(define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
[(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand")
(unsigned_float:FP_ISA3
- (match_operand:QHI 1 "input_operand" "")))
- (clobber (match_scratch:DI 2 ""))
- (clobber (match_scratch:DI 3 ""))])]
+ (match_operand:QHI 1 "input_operand")))
+ (clobber (match_scratch:DI 2))
+ (clobber (match_scratch:DI 3))])]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
@@ -5577,8 +5577,8 @@ (define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
})
(define_expand "fix_trunc<mode>si2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
{
if (!TARGET_P8_VECTOR)
@@ -5667,8 +5667,8 @@ (define_insn_and_split "fix_trunc<mode>si2_internal"
(set_attr "type" "fp")])
(define_expand "fix_trunc<mode>di2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (fix:DI (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"")
@@ -5737,8 +5737,8 @@ (define_insn_and_split "*fix<uns>_trunc<SFDF:mode><QHSI:mode>2_mem"
})
(define_expand "fixuns_trunc<mode>si2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
{
if (!TARGET_P8_VECTOR)
@@ -5981,9 +5981,9 @@ (define_insn "*xsrdpi<mode>2"
(define_expand "lround<mode>di2"
[(set (match_dup 2)
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand")]
UNSPEC_XSRDPI))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
+ (set (match_operand:DI 0 "gpc_reg_operand")
(unspec:DI [(match_dup 2)]
UNSPEC_FCTID))]
"TARGET_<MODE>_FPR && TARGET_VSX"
@@ -6008,8 +6008,8 @@ (define_insn "stfiwx"
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
(define_expand "floatsisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float:SF (match_operand:SI 1 "nonimmediate_operand")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
@@ -6066,9 +6066,9 @@ (define_insn_and_split "*floatdidf2_mem"
(set_attr "type" "fpload")])
(define_expand "floatunsdidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
+ [(set (match_operand:DF 0 "gpc_reg_operand")
(unsigned_float:DF
- (match_operand:DI 1 "gpc_reg_operand" "")))]
+ (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_FCFIDU"
"")
@@ -6096,8 +6096,8 @@ (define_insn_and_split "*floatunsdidf2_mem"
(set_attr "type" "fpload")])
(define_expand "floatdisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float:SF (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
{
@@ -6166,11 +6166,11 @@ (define_insn_and_split "floatdisf2_internal1"
;; by a bit that won't be lost at that stage, but is below the SFmode
;; rounding position.
(define_expand "floatdisf2_internal2"
- [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
+ [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "")
(const_int 53)))
(clobber (reg:DI CA_REGNO))])
- (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
- (const_int 2047)))
+ (set (match_operand:DI 0 "") (and:DI (match_dup 1)
+ (const_int 2047)))
(set (match_dup 3) (plus:DI (match_dup 3)
(const_int 1)))
(set (match_dup 0) (plus:DI (match_dup 0)
@@ -6182,7 +6182,7 @@ (define_expand "floatdisf2_internal2"
(set (match_dup 0) (and:DI (match_dup 0)
(const_int -2048)))
(set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
- (label_ref (match_operand:DI 2 "" ""))
+ (label_ref (match_operand:DI 2 ""))
(pc)))
(set (match_dup 0) (match_dup 1))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
@@ -6193,8 +6193,8 @@ (define_expand "floatdisf2_internal2"
})
(define_expand "floatunsdisf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"")
@@ -6233,9 +6233,9 @@ (define_insn_and_split "*floatunsdisf2_mem"
;; also allow for the output being the same as one of the inputs.
(define_expand "addti3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "")
- (plus:TI (match_operand:TI 1 "gpc_reg_operand" "")
- (match_operand:TI 2 "reg_or_short_operand" "")))]
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (plus:TI (match_operand:TI 1 "gpc_reg_operand")
+ (match_operand:TI 2 "reg_or_short_operand")))]
"TARGET_64BIT"
{
rtx lo0 = gen_lowpart (DImode, operands[0]);
@@ -6256,9 +6256,9 @@ (define_expand "addti3"
})
(define_expand "subti3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "")
- (minus:TI (match_operand:TI 1 "reg_or_short_operand" "")
- (match_operand:TI 2 "gpc_reg_operand" "")))]
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (minus:TI (match_operand:TI 1 "reg_or_short_operand")
+ (match_operand:TI 2 "gpc_reg_operand")))]
"TARGET_64BIT"
{
rtx lo0 = gen_lowpart (DImode, operands[0]);
@@ -6281,73 +6281,73 @@ (define_expand "subti3"
;; 128-bit logical operations expanders
(define_expand "and<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand")))]
""
"")
(define_expand "ior<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand")))]
""
"")
(define_expand "xor<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand")))]
""
"")
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
- (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")))]
""
"")
(define_expand "nor<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(and:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand"))
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))]
""
"")
(define_expand "andc<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(and:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
- (match_operand:BOOL_128 1 "vlogical_operand" "")))]
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))
+ (match_operand:BOOL_128 1 "vlogical_operand")))]
""
"")
;; Power8 vector logical instructions.
(define_expand "eqv<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(not:BOOL_128
- (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
- (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
+ (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")
+ (match_operand:BOOL_128 2 "vlogical_operand"))))]
"<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
"")
;; Rewrite nand into canonical form
(define_expand "nand<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(ior:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
+ (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand"))
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))]
"<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
"")
;; The canonical form is to have the negated element first, so we need to
;; reverse arguments.
(define_expand "orc<mode>3"
- [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
+ [(set (match_operand:BOOL_128 0 "vlogical_operand")
(ior:BOOL_128
- (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
- (match_operand:BOOL_128 1 "vlogical_operand" "")))]
+ (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))
+ (match_operand:BOOL_128 1 "vlogical_operand")))]
"<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
"")
@@ -6641,8 +6641,8 @@ (define_insn_and_split "*one_cmpl<mode>3_internal"
;; Set up a register with a value from the GOT table
(define_expand "movsi_got"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unspec:SI [(match_operand:SI 1 "got_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unspec:SI [(match_operand:SI 1 "got_operand")
(match_dup 2)] UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1"
{
@@ -6679,9 +6679,9 @@ (define_insn "*movsi_got_internal"
;; Used by sched, shorten_branches and final when the GOT pseudo reg
;; didn't get allocated to a hard register.
(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
- (match_operand:SI 2 "memory_operand" "")]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (unspec:SI [(match_operand:SI 1 "got_no_const_operand")
+ (match_operand:SI 2 "memory_operand")]
UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4
&& flag_pic == 1
@@ -6940,8 +6940,8 @@ (define_insn "*movsi_from_df"
;; sequence.
(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (match_operand:SI 1 "const_int_operand"))]
"(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
&& (INTVAL (operands[1]) & 0xffff) != 0"
[(set (match_dup 0)
@@ -7000,8 +7000,8 @@ (define_split
"")
\f
(define_expand "mov<mode>"
- [(set (match_operand:INT 0 "general_operand" "")
- (match_operand:INT 1 "any_operand" ""))]
+ [(set (match_operand:INT 0 "general_operand")
+ (match_operand:INT 1 "any_operand"))]
""
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
@@ -7056,8 +7056,8 @@ (define_insn "*mov<mode>_internal"
;; an integer register or memory, we store just the high-order 4 bits.
;; This lets us not shift in the most common case of CR0.
(define_expand "movcc"
- [(set (match_operand:CC 0 "nonimmediate_operand" "")
- (match_operand:CC 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:CC 0 "nonimmediate_operand")
+ (match_operand:CC 1 "nonimmediate_operand"))]
""
"")
@@ -7110,8 +7110,8 @@ (define_insn "*movcc_internal1"
;; Move 32-bit binary/decimal floating point
(define_expand "mov<mode>"
- [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
- (match_operand:FMOVE32 1 "any_operand" ""))]
+ [(set (match_operand:FMOVE32 0 "nonimmediate_operand")
+ (match_operand:FMOVE32 1 "any_operand"))]
"<fmove_ok>"
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
@@ -7119,8 +7119,8 @@ (define_expand "mov<mode>"
})
(define_split
- [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
- (match_operand:FMOVE32 1 "const_double_operand" ""))]
+ [(set (match_operand:FMOVE32 0 "gpc_reg_operand")
+ (match_operand:FMOVE32 1 "const_double_operand"))]
"reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
@@ -7309,8 +7309,8 @@ (define_insn_and_split "movsf_from_si"
\f
;; Move 64-bit binary/decimal floating point
(define_expand "mov<mode>"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
- (match_operand:FMOVE64 1 "any_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand")
+ (match_operand:FMOVE64 1 "any_operand"))]
""
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
@@ -7318,8 +7318,8 @@ (define_expand "mov<mode>"
})
(define_split
- [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
- (match_operand:FMOVE64 1 "const_int_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
+ (match_operand:FMOVE64 1 "const_int_operand"))]
"! TARGET_POWERPC64 && reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
@@ -7338,8 +7338,8 @@ (define_split
})
(define_split
- [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
- (match_operand:FMOVE64 1 "const_double_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
+ (match_operand:FMOVE64 1 "const_double_operand"))]
"! TARGET_POWERPC64 && reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
@@ -7360,8 +7360,8 @@ (define_split
})
(define_split
- [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
- (match_operand:FMOVE64 1 "const_double_operand" ""))]
+ [(set (match_operand:FMOVE64 0 "gpc_reg_operand")
+ (match_operand:FMOVE64 1 "const_double_operand"))]
"TARGET_POWERPC64 && reload_completed
&& ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
|| (GET_CODE (operands[0]) == SUBREG
@@ -7486,8 +7486,8 @@ (define_insn "*mov<mode>_softfloat64"
(set_attr "length" "4,4,4,4,4,8,12,16,4")])
\f
(define_expand "mov<mode>"
- [(set (match_operand:FMOVE128 0 "general_operand" "")
- (match_operand:FMOVE128 1 "any_operand" ""))]
+ [(set (match_operand:FMOVE128 0 "general_operand")
+ (match_operand:FMOVE128 1 "any_operand"))]
""
{
rs6000_emit_move (operands[0], operands[1], <MODE>mode);
@@ -7555,8 +7555,8 @@ (define_insn_and_split "*mov<mode>_softfloat"
[(set_attr "length" "20,20,16")])
(define_expand "extenddf<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
@@ -7624,8 +7624,8 @@ (define_insn_and_split "extenddf<mode>2_vsx"
})
(define_expand "extendsf<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
@@ -7640,8 +7640,8 @@ (define_expand "extendsf<mode>2"
})
(define_expand "trunc<mode>df2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand")
+ (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
@@ -7678,8 +7678,8 @@ (define_insn "trunc<mode>df2_internal2"
(set_attr "fp_type" "fp_addsub_d")])
(define_expand "trunc<mode>sf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
@@ -7750,8 +7750,8 @@ (define_insn "fix_trunc_helper<mode>"
(set_attr "length" "20")])
(define_expand "fix_trunc<mode>si2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand")
+ (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
rtx op0 = operands[0];
@@ -7774,8 +7774,8 @@ (define_expand "fix_trunc<mode>si2"
})
(define_expand "fix_trunc<mode>si2_fprs"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:IBM128 1 "gpc_reg_operand" "")))
+ [(parallel [(set (match_operand:SI 0 "gpc_reg_operand")
+ (fix:SI (match_operand:IBM128 1 "gpc_reg_operand")))
(clobber (match_dup 2))
(clobber (match_dup 3))
(clobber (match_dup 4))
@@ -7814,8 +7814,8 @@ (define_insn_and_split "*fix_trunc<mode>si2_internal"
})
(define_expand "fix_trunc<mode>di2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
if (!TARGET_FLOAT128_HW)
@@ -7826,8 +7826,8 @@ (define_expand "fix_trunc<mode>di2"
})
(define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>2"
- [(set (match_operand:SDI 0 "gpc_reg_operand" "")
- (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:SDI 0 "gpc_reg_operand")
+ (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], true);
@@ -7835,8 +7835,8 @@ (define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>2"
})
(define_expand "floatdi<mode>2"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
- (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IEEE128 0 "gpc_reg_operand")
+ (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
if (!TARGET_FLOAT128_HW)
@@ -7847,8 +7847,8 @@ (define_expand "floatdi<mode>2"
})
(define_expand "floatunsdi<IEEE128:mode>2"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
- (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IEEE128 0 "gpc_reg_operand")
+ (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
if (!TARGET_FLOAT128_HW)
@@ -7859,8 +7859,8 @@ (define_expand "floatunsdi<IEEE128:mode>2"
})
(define_expand "floatuns<IEEE128:mode>2"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
- (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IEEE128 0 "gpc_reg_operand")
+ (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rtx op0 = operands[0];
@@ -7874,8 +7874,8 @@ (define_expand "floatuns<IEEE128:mode>2"
})
(define_expand "neg<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
{
@@ -7927,8 +7927,8 @@ (define_insn "neg<mode>2_internal"
(set_attr "length" "8")])
(define_expand "abs<mode>2"
- [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
- (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
+ (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
{
@@ -7972,13 +7972,13 @@ (define_expand "abs<mode>2"
})
(define_expand "abs<mode>2_internal"
- [(set (match_operand:IBM128 0 "gpc_reg_operand" "")
- (match_operand:IBM128 1 "gpc_reg_operand" ""))
+ [(set (match_operand:IBM128 0 "gpc_reg_operand")
+ (match_operand:IBM128 1 "gpc_reg_operand"))
(set (match_dup 3) (match_dup 5))
(set (match_dup 5) (abs:DF (match_dup 5)))
(set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
(set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
- (label_ref (match_operand 2 "" ""))
+ (label_ref (match_operand 2 ""))
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
@@ -7996,7 +7996,7 @@ (define_expand "abs<mode>2_internal"
;; register
(define_expand "ieee_128bit_negative_zero"
- [(set (match_operand:V16QI 0 "register_operand" "") (match_dup 1))]
+ [(set (match_operand:V16QI 0 "register_operand") (match_dup 1))]
"TARGET_FLOAT128_TYPE"
{
rtvec v = rtvec_alloc (16);
@@ -8115,8 +8115,8 @@ (define_insn "*ieee_128bit_vsx_nabs<mode>2_internal"
;; We use expand to convert from IBM double double to IEEE 128-bit
;; and trunc for the opposite.
(define_expand "extendiftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand" "")
- (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:TF 0 "gpc_reg_operand")
+ (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -8124,8 +8124,8 @@ (define_expand "extendiftf2"
})
(define_expand "extendifkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand" "")
- (float_extend:KF (match_operand:IF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:KF 0 "gpc_reg_operand")
+ (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -8133,8 +8133,8 @@ (define_expand "extendifkf2"
})
(define_expand "extendtfkf2"
- [(set (match_operand:KF 0 "gpc_reg_operand" "")
- (float_extend:KF (match_operand:TF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:KF 0 "gpc_reg_operand")
+ (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -8142,8 +8142,8 @@ (define_expand "extendtfkf2"
})
(define_expand "trunciftf2"
- [(set (match_operand:IF 0 "gpc_reg_operand" "")
- (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IF 0 "gpc_reg_operand")
+ (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -8151,8 +8151,8 @@ (define_expand "trunciftf2"
})
(define_expand "truncifkf2"
- [(set (match_operand:IF 0 "gpc_reg_operand" "")
- (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IF 0 "gpc_reg_operand")
+ (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -8160,8 +8160,8 @@ (define_expand "truncifkf2"
})
(define_expand "trunckftf2"
- [(set (match_operand:TF 0 "gpc_reg_operand" "")
- (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:TF 0 "gpc_reg_operand")
+ (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -8169,8 +8169,8 @@ (define_expand "trunckftf2"
})
(define_expand "trunctfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand" "")
- (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))]
+ [(set (match_operand:IF 0 "gpc_reg_operand")
+ (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
"TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
@@ -8349,8 +8349,8 @@ (define_insn_and_split "reload_vsx_from_gpr<mode>"
(set_attr "type" "three")])
(define_split
- [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
- (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
+ [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand")
+ (match_operand:FMOVE128_GPR 1 "input_operand"))]
"reload_completed
&& (int_reg_operand (operands[0], <MODE>mode)
|| int_reg_operand (operands[1], <MODE>mode))
@@ -8516,8 +8516,8 @@ (define_insn "*movdi_internal32"
(set_attr "size" "64")])
(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (match_operand:DI 1 "const_int_operand" ""))]
+ [(set (match_operand:DI 0 "gpc_reg_operand")
+ (match_operand:DI 1 "const_int_operand"))]
"! TARGET_POWERPC64 && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])
&& !direct_move_p (operands[0], operands[1])"
@@ -8534,8 +8534,8 @@ (define_split
})
(define_split
- [(set (match_operand:DIFD 0 "nonimmediate_operand" "")
- (match_operand:DIFD 1 "input_operand" ""))]
+ [(set (match_operand:DIFD 0 "nonimmediate_operand")
+ (match_operand:DIFD 1 "input_operand"))]
"reload_completed && !TARGET_POWERPC64
&& gpr_or_gpr_p (operands[0], operands[1])
&& !direct_move_p (operands[0], operands[1])"
@@ -8630,8 +8630,8 @@ (define_split
;; When non-easy constants can go in the TOC, this should use
;; easy_fp_constant predicate.
(define_split
- [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
- (match_operand:DI 1 "const_int_operand" ""))]
+ [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
+ (match_operand:DI 1 "const_int_operand"))]
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
@@ -8643,8 +8643,8 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
- (match_operand:DI 1 "const_scalar_int_operand" ""))]
+ [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
+ (match_operand:DI 1 "const_scalar_int_operand"))]
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
@@ -8656,8 +8656,8 @@ (define_split
})
(define_split
- [(set (match_operand:DI 0 "altivec_register_operand" "")
- (match_operand:DI 1 "s5bit_cint_operand" ""))]
+ [(set (match_operand:DI 0 "altivec_register_operand")
+ (match_operand:DI 1 "s5bit_cint_operand"))]
"TARGET_VSX && reload_completed"
[(const_int 0)]
{
@@ -8678,8 +8678,8 @@ (define_split
;; Split integer constants that can be loaded with XXSPLTIB and a
;; sign extend operation.
(define_split
- [(set (match_operand:INT_ISA3 0 "altivec_register_operand" "")
- (match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))]
+ [(set (match_operand:INT_ISA3 0 "altivec_register_operand")
+ (match_operand:INT_ISA3 1 "xxspltib_constant_split"))]
"TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
@@ -8731,8 +8731,8 @@ (define_insn "*mov<mode>_ppc64"
(set_attr "length" "8")])
(define_split
- [(set (match_operand:TI2 0 "int_reg_operand" "")
- (match_operand:TI2 1 "const_scalar_int_operand" ""))]
+ [(set (match_operand:TI2 0 "int_reg_operand")
+ (match_operand:TI2 1 "const_scalar_int_operand"))]
"TARGET_POWERPC64
&& (VECTOR_MEM_NONE_P (<MODE>mode)
|| (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
@@ -8758,8 +8758,8 @@ (define_split
})
(define_split
- [(set (match_operand:TI2 0 "nonimmediate_operand" "")
- (match_operand:TI2 1 "input_operand" ""))]
+ [(set (match_operand:TI2 0 "nonimmediate_operand")
+ (match_operand:TI2 1 "input_operand"))]
"reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])
&& !direct_move_p (operands[0], operands[1])
@@ -8768,10 +8768,10 @@ (define_split
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
\f
(define_expand "setmemsi"
- [(parallel [(set (match_operand:BLK 0 "" "")
- (match_operand 2 "const_int_operand" ""))
- (use (match_operand:SI 1 "" ""))
- (use (match_operand:SI 3 "" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "")
+ (match_operand 2 "const_int_operand"))
+ (use (match_operand:SI 1 ""))
+ (use (match_operand:SI 3 ""))])]
""
{
/* If value to set is not zero, use the library routine. */
@@ -8858,10 +8858,10 @@ (define_expand "cmpmemsi"
;; Argument 3 is the alignment
(define_expand "movmemsi"
- [(parallel [(set (match_operand:BLK 0 "" "")
- (match_operand:BLK 1 "" ""))
- (use (match_operand:SI 2 "" ""))
- (use (match_operand:SI 3 "" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "")
+ (match_operand:BLK 1 ""))
+ (use (match_operand:SI 2 ""))
+ (use (match_operand:SI 3 ""))])]
""
{
if (expand_block_move (operands))
@@ -9216,18 +9216,18 @@ (define_insn "*movdf_update2"
;; Also this optimization interferes with scalars going into
;; altivec registers (the code does reloading through the FPRs).
(define_peephole2
- [(set (match_operand:DF 0 "gpc_reg_operand" "")
- (match_operand:DF 1 "any_operand" ""))
- (set (match_operand:DF 2 "gpc_reg_operand" "")
+ [(set (match_operand:DF 0 "gpc_reg_operand")
+ (match_operand:DF 1 "any_operand"))
+ (set (match_operand:DF 2 "gpc_reg_operand")
(match_dup 0))]
"!TARGET_VSX
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
(define_peephole2
- [(set (match_operand:SF 0 "gpc_reg_operand" "")
- (match_operand:SF 1 "any_operand" ""))
- (set (match_operand:SF 2 "gpc_reg_operand" "")
+ [(set (match_operand:SF 0 "gpc_reg_operand")
+ (match_operand:SF 1 "any_operand"))
+ (set (match_operand:SF 2 "gpc_reg_operand")
(match_dup 0))]
"!TARGET_P8_VECTOR
&& peep2_reg_dead_p (2, operands[0])"
@@ -9662,7 +9662,7 @@ (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
"add %0,%1,%2@tls")
(define_expand "tls_get_tpointer"
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand")
(unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
{
@@ -9679,9 +9679,9 @@ (define_insn "tls_get_tpointer_internal"
"bla __get_tpointer")
(define_expand "tls_get_addr<mode>"
- [(set (match_operand:P 0 "gpc_reg_operand" "")
- (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
- (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
+ [(set (match_operand:P 0 "gpc_reg_operand")
+ (unspec:P [(match_operand:P 1 "gpc_reg_operand")
+ (match_operand:P 2 "gpc_reg_operand")] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
{
emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
@@ -9719,8 +9719,8 @@ (define_insn "tls_get_addr_internal<mode>"
;; the constant size. The value is forced into a register if necessary.
;;
(define_expand "allocate_stack"
- [(set (match_operand 0 "gpc_reg_operand" "")
- (minus (reg 1) (match_operand 1 "reg_or_cint_operand" "")))
+ [(set (match_operand 0 "gpc_reg_operand")
+ (minus (reg 1) (match_operand 1 "reg_or_cint_operand")))
(set (reg 1)
(minus (reg 1) (match_dup 1)))]
""
@@ -9841,14 +9841,14 @@ (define_expand "allocate_stack"
;; save area is a memory location.
(define_expand "save_stack_function"
- [(match_operand 0 "any_operand" "")
- (match_operand 1 "any_operand" "")]
+ [(match_operand 0 "any_operand")
+ (match_operand 1 "any_operand")]
""
"DONE;")
(define_expand "restore_stack_function"
- [(match_operand 0 "any_operand" "")
- (match_operand 1 "any_operand" "")]
+ [(match_operand 0 "any_operand")
+ (match_operand 1 "any_operand")]
""
"DONE;")
@@ -9859,8 +9859,8 @@ (define_expand "restore_stack_block"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 2))
(match_dup 5)
- (set (match_operand 0 "register_operand" "")
- (match_operand 1 "register_operand" ""))]
+ (set (match_operand 0 "register_operand")
+ (match_operand 1 "register_operand"))]
""
{
rtvec p;
@@ -9877,8 +9877,8 @@ (define_expand "restore_stack_block"
(define_expand "save_stack_nonlocal"
[(set (match_dup 3) (match_dup 4))
- (set (match_operand 0 "memory_operand" "") (match_dup 3))
- (set (match_dup 2) (match_operand 1 "register_operand" ""))]
+ (set (match_operand 0 "memory_operand") (match_dup 3))
+ (set (match_dup 2) (match_operand 1 "register_operand"))]
""
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
@@ -9891,11 +9891,11 @@ (define_expand "save_stack_nonlocal"
})
(define_expand "restore_stack_nonlocal"
- [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
+ [(set (match_dup 2) (match_operand 1 "memory_operand"))
(set (match_dup 3) (match_dup 4))
(set (match_dup 5) (match_dup 2))
(match_dup 6)
- (set (match_operand 0 "register_operand" "") (match_dup 3))]
+ (set (match_operand 0 "register_operand") (match_dup 3))]
""
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
@@ -10004,7 +10004,7 @@ (define_insn "load_toc_v4_PIC_1_476"
(define_expand "load_toc_v4_PIC_1b"
[(parallel [(set (reg:SI LR_REGNO)
(unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
- (label_ref (match_operand 1 "" ""))]
+ (label_ref (match_operand 1 ""))]
UNSPEC_TOCPTR))
(match_dup 1)])]
"TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
@@ -10077,7 +10077,7 @@ (define_insn "load_toc_v4_PIC_3c"
;; On Darwin, we need to reload the picbase.
(define_expand "builtin_setjmp_receiver"
- [(use (label_ref (match_operand 0 "" "")))]
+ [(use (label_ref (match_operand 0 "")))]
"(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
|| (TARGET_TOC && TARGET_MINIMAL_TOC)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
@@ -10188,9 +10188,9 @@ (define_insn "elf_low"
\f
;; Call and call_value insns
(define_expand "call"
- [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
+ [(parallel [(call (mem:SI (match_operand 0 "address_operand"))
+ (match_operand 1 ""))
+ (use (match_operand 2 ""))
(clobber (reg:SI LR_REGNO))])]
""
{
@@ -10230,10 +10230,10 @@ (define_expand "call"
})
(define_expand "call_value"
- [(parallel [(set (match_operand 0 "" "")
- (call (mem:SI (match_operand 1 "address_operand" ""))
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))
+ [(parallel [(set (match_operand 0 "")
+ (call (mem:SI (match_operand 1 "address_operand"))
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))
(clobber (reg:SI LR_REGNO))])]
""
{
@@ -10718,10 +10718,10 @@ (define_insn "*call_value_indirect_elfv2<mode>_nospec"
;; Call subroutine returning any type.
(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
+ [(parallel [(call (match_operand 0 "")
(const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
+ (match_operand 1 "")
+ (match_operand 2 "")])]
""
{
int i;
@@ -10745,9 +10745,9 @@ (define_expand "untyped_call"
;; sibling call patterns
(define_expand "sibcall"
- [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
+ [(parallel [(call (mem:SI (match_operand 0 "address_operand"))
+ (match_operand 1 ""))
+ (use (match_operand 2 ""))
(simple_return)])]
""
{
@@ -10769,10 +10769,10 @@ (define_expand "sibcall"
})
(define_expand "sibcall_value"
- [(parallel [(set (match_operand 0 "register_operand" "")
- (call (mem:SI (match_operand 1 "address_operand" ""))
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))
+ [(parallel [(set (match_operand 0 "register_operand")
+ (call (mem:SI (match_operand 1 "address_operand"))
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))
(simple_return)])]
""
{
@@ -11061,9 +11061,9 @@ (define_insn "probe_stack_range<P:mode>"
(define_expand "cbranch<mode>4"
[(use (match_operator 0 "comparison_operator"
- [(match_operand:GPR 1 "gpc_reg_operand" "")
- (match_operand:GPR 2 "reg_or_short_operand" "")]))
- (use (match_operand 3 ""))]
+ [(match_operand:GPR 1 "gpc_reg_operand")
+ (match_operand:GPR 2 "reg_or_short_operand")]))
+ (use (match_operand 3))]
""
{
/* Take care of the possibility that operands[2] might be negative but
@@ -11083,9 +11083,9 @@ (define_expand "cbranch<mode>4"
(define_expand "cbranch<mode>4"
[(use (match_operator 0 "comparison_operator"
- [(match_operand:FP 1 "gpc_reg_operand" "")
- (match_operand:FP 2 "gpc_reg_operand" "")]))
- (use (match_operand 3 ""))]
+ [(match_operand:FP 1 "gpc_reg_operand")
+ (match_operand:FP 2 "gpc_reg_operand")]))
+ (use (match_operand 3))]
""
{
rs6000_emit_cbranch (<MODE>mode, operands);
@@ -11502,18 +11502,18 @@ (define_insn "*cmp<mode>_unsigned"
(define_peephole2
[(set (match_operand:SI 0 "register_operand")
- (match_operand:SI 1 "logical_const_operand" ""))
+ (match_operand:SI 1 "logical_const_operand"))
(set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
[(match_dup 0)
- (match_operand:SI 2 "logical_const_operand" "")]))
- (set (match_operand:CC 4 "cc_reg_operand" "")
- (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
+ (match_operand:SI 2 "logical_const_operand")]))
+ (set (match_operand:CC 4 "cc_reg_operand")
+ (compare:CC (match_operand:SI 5 "gpc_reg_operand")
(match_dup 0)))
(set (pc)
(if_then_else (match_operator 6 "equality_operator"
[(match_dup 4) (const_int 0)])
- (match_operand 7 "" "")
- (match_operand 8 "" "")))]
+ (match_operand 7 "")
+ (match_operand 8 "")))]
"peep2_reg_dead_p (3, operands[0])
&& peep2_reg_dead_p (4, operands[4])
&& REGNO (operands[0]) != REGNO (operands[5])"
@@ -11562,21 +11562,21 @@ (define_insn ""
[(set_attr "length" "8")])
(define_split
- [(set (match_operand:CC 3 "cc_reg_operand" "")
- (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "short_cint_operand" "")))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
+ [(set (match_operand:CC 3 "cc_reg_operand")
+ (compare:CC (match_operand:SI 1 "gpc_reg_operand")
+ (match_operand:SI 2 "short_cint_operand")))
+ (set (match_operand:SI 0 "gpc_reg_operand")
+ (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))]
""
[(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
(define_split
- [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
- (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "u_short_cint_operand" "")))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
+ [(set (match_operand:CCUNS 3 "cc_reg_operand")
+ (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand")
+ (match_operand:SI 2 "u_short_cint_operand")))
+ (set (match_operand:SI 0 "gpc_reg_operand")
+ (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))]
""
[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
@@ -11715,12 +11715,12 @@ (define_insn ""
(set_attr "length" "8,16")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
+ [(set (match_operand:CC 0 "cc_reg_not_cr0_operand")
(compare:CC (match_operator:SI 1 "scc_comparison_operator"
- [(match_operand 2 "cc_reg_operand" "")
+ [(match_operand 2 "cc_reg_operand")
(const_int 0)])
(const_int 0)))
- (set (match_operand:SI 3 "gpc_reg_operand" "")
+ (set (match_operand:SI 3 "gpc_reg_operand")
(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
"TARGET_32BIT && reload_completed"
[(set (match_dup 3)
@@ -13002,8 +13002,8 @@ (define_expand "epilogue"
; faster; for instance, on the 601 and 750.
(define_expand "movsi_to_cr_one"
- [(set (match_operand:CC 0 "cc_reg_operand" "")
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
+ [(set (match_operand:CC 0 "cc_reg_operand")
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand")
(match_dup 2)] UNSPEC_MOVESI_TO_CR))]
""
"operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
@@ -13210,7 +13210,7 @@ (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
; This is used in compiling the unwind routines.
(define_expand "eh_return"
- [(use (match_operand 0 "general_operand" ""))]
+ [(use (match_operand 0 "general_operand"))]
""
{
if (TARGET_32BIT)
@@ -13229,8 +13229,8 @@ (define_insn "eh_set_lr_<mode>"
"#")
(define_split
- [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
- (clobber (match_scratch 1 ""))]
+ [(unspec_volatile [(match_operand 0 "register_operand")] UNSPECV_EH_RR)
+ (clobber (match_scratch 1))]
"reload_completed"
[(const_int 0)]
{
@@ -13331,11 +13331,11 @@ (define_insn "bpermd_<mode>"
;; Note that the conditions for expansion are in the FMA_F iterator.
(define_expand "fma<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (match_operand:FMA_F 3 "gpc_reg_operand" "")))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (match_operand:FMA_F 3 "gpc_reg_operand")))]
""
"")
@@ -13355,11 +13355,11 @@ (define_insn "*fma<mode>4_fpr"
; Altivec only has fma and nfms.
(define_expand "fms<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" ""))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand"))))]
"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"")
@@ -13379,34 +13379,34 @@ (define_insn "*fms<mode>4_fpr"
;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
(define_expand "fnma<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))]
"!HONOR_SIGNED_ZEROS (<MODE>mode)"
"")
;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
(define_expand "fnms<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (match_operand:FMA_F 3 "gpc_reg_operand" ""))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (match_operand:FMA_F 3 "gpc_reg_operand"))))]
"!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"")
; Not an official optab name, but used from builtins.
(define_expand "nfma<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (match_operand:FMA_F 3 "gpc_reg_operand" ""))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (match_operand:FMA_F 3 "gpc_reg_operand"))))]
"!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"")
@@ -13427,12 +13427,12 @@ (define_insn "*nfma<mode>4_fpr"
; Not an official optab name, but used from builtins.
(define_expand "nfms<mode>4"
- [(set (match_operand:FMA_F 0 "gpc_reg_operand" "")
+ [(set (match_operand:FMA_F 0 "gpc_reg_operand")
(neg:FMA_F
(fma:FMA_F
- (match_operand:FMA_F 1 "gpc_reg_operand" "")
- (match_operand:FMA_F 2 "gpc_reg_operand" "")
- (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))]
+ (match_operand:FMA_F 1 "gpc_reg_operand")
+ (match_operand:FMA_F 2 "gpc_reg_operand")
+ (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))]
""
"")
@@ -13454,7 +13454,7 @@ (define_insn "*nfmssf4_fpr"
\f
(define_expand "rs6000_get_timebase"
- [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
+ [(use (match_operand:DI 0 "gpc_reg_operand"))]
""
{
if (TARGET_POWERPC64)
@@ -13552,8 +13552,8 @@ (define_insn "rs6000_mtfsf"
;; (addis followed by load) even on power8.
(define_split
- [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand" "")
- (match_operand:INT1 1 "toc_fusion_mem_raw" ""))]
+ [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand")
+ (match_operand:INT1 1 "toc_fusion_mem_raw"))]
"TARGET_TOC_FUSION_INT && can_create_pseudo_p ()"
[(parallel [(set (match_dup 0) (match_dup 2))
(unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
@@ -13603,10 +13603,10 @@ (define_insn "*toc_fusionload_di"
;; insn
(define_peephole2
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "fusion_gpr_addis" ""))
- (set (match_operand:INT1 2 "base_reg_operand" "")
- (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "fusion_gpr_addis"))
+ (set (match_operand:INT1 2 "base_reg_operand")
+ (match_operand:INT1 3 "fusion_gpr_mem_load"))]
"TARGET_P8_FUSION
&& fusion_gpr_load_p (operands[0], operands[1], operands[2],
operands[3])"
@@ -13634,10 +13634,10 @@ (define_insn "fusion_gpr_load_<mode>"
;; ISA 3.0 (power9) fusion support
;; Merge addis with floating load/store to FPRs (or GPRs).
(define_peephole2
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "fusion_gpr_addis" ""))
- (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand" "")
- (match_operand:SFDF 3 "fusion_offsettable_mem_operand" ""))]
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "fusion_gpr_addis"))
+ (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand")
+ (match_operand:SFDF 3 "fusion_offsettable_mem_operand"))]
"TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
&& fusion_p9_p (operands[0], operands[1], operands[2], operands[3])"
[(const_int 0)]
@@ -13647,10 +13647,10 @@ (define_peephole2
})
(define_peephole2
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "fusion_gpr_addis" ""))
- (set (match_operand:SFDF 2 "offsettable_mem_operand" "")
- (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand" ""))]
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "fusion_gpr_addis"))
+ (set (match_operand:SFDF 2 "offsettable_mem_operand")
+ (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand"))]
"TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
&& fusion_p9_p (operands[0], operands[1], operands[2], operands[3])
&& !rtx_equal_p (operands[0], operands[3])"
@@ -13661,22 +13661,22 @@ (define_peephole2
})
(define_peephole2
- [(set (match_operand:SDI 0 "int_reg_operand" "")
- (match_operand:SDI 1 "upper16_cint_operand" ""))
+ [(set (match_operand:SDI 0 "int_reg_operand")
+ (match_operand:SDI 1 "upper16_cint_operand"))
(set (match_dup 0)
(ior:SDI (match_dup 0)
- (match_operand:SDI 2 "u_short_cint_operand" "")))]
+ (match_operand:SDI 2 "u_short_cint_operand")))]
"TARGET_P9_FUSION"
[(set (match_dup 0)
(unspec:SDI [(match_dup 1)
(match_dup 2)] UNSPEC_FUSION_P9))])
(define_peephole2
- [(set (match_operand:SDI 0 "int_reg_operand" "")
- (match_operand:SDI 1 "upper16_cint_operand" ""))
- (set (match_operand:SDI 2 "int_reg_operand" "")
+ [(set (match_operand:SDI 0 "int_reg_operand")
+ (match_operand:SDI 1 "upper16_cint_operand"))
+ (set (match_operand:SDI 2 "int_reg_operand")
(ior:SDI (match_dup 0)
- (match_operand:SDI 3 "u_short_cint_operand" "")))]
+ (match_operand:SDI 3 "u_short_cint_operand")))]
"TARGET_P9_FUSION
&& !rtx_equal_p (operands[0], operands[2])
&& peep2_reg_dead_p (2, operands[0])"
@@ -13892,10 +13892,10 @@ (define_mode_attr FP128_64 [(TF "DF")
(KF "DI")])
(define_expand "unpack<mode>"
- [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
+ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand")
(unspec:<FP128_64>
- [(match_operand:FMOVE128 1 "register_operand" "")
- (match_operand:QI 2 "const_0_to_1_operand" "")]
+ [(match_operand:FMOVE128 1 "register_operand")
+ (match_operand:QI 2 "const_0_to_1_operand")]
UNSPEC_UNPACK_128BIT))]
"FLOAT128_2REG_P (<MODE>mode)"
"")
diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md
index f4f7bc2..74bc407 100644
--- a/gcc/config/rs6000/sync.md
+++ b/gcc/config/rs6000/sync.md
@@ -38,7 +38,7 @@ (define_code_attr fetchop_pred
(ior "logical_operand") (xor "logical_operand") (and "and_operand")])
(define_expand "mem_thread_fence"
- [(match_operand:SI 0 "const_int_operand" "")] ;; model
+ [(match_operand:SI 0 "const_int_operand")] ;; model
""
{
enum memmodel model = memmodel_base (INTVAL (operands[0]));
@@ -136,9 +136,9 @@ (define_insn "load_quadpti"
(set_attr "length" "4")])
(define_expand "atomic_load<mode>"
- [(set (match_operand:AINT 0 "register_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "")) ;; memory
- (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
+ [(set (match_operand:AINT 0 "register_operand") ;; output
+ (match_operand:AINT 1 "memory_operand")) ;; memory
+ (use (match_operand:SI 2 "const_int_operand"))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
@@ -200,9 +200,9 @@ (define_insn "store_quadpti"
(set_attr "length" "4")])
(define_expand "atomic_store<mode>"
- [(set (match_operand:AINT 0 "memory_operand" "") ;; memory
- (match_operand:AINT 1 "register_operand" "")) ;; input
- (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
+ [(set (match_operand:AINT 0 "memory_operand") ;; memory
+ (match_operand:AINT 1 "register_operand")) ;; input
+ (use (match_operand:SI 2 "const_int_operand"))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
@@ -287,8 +287,8 @@ (define_insn "load_locked<QHI:mode>_si"
;; is indexed or indirect before register allocation.
(define_expand "load_lockedti"
- [(use (match_operand:TI 0 "quad_int_reg_operand" ""))
- (use (match_operand:TI 1 "memory_operand" ""))]
+ [(use (match_operand:TI 0 "quad_int_reg_operand"))
+ (use (match_operand:TI 1 "memory_operand"))]
"TARGET_SYNC_TI"
{
rtx op0 = operands[0];
@@ -341,9 +341,9 @@ (define_insn "store_conditional<mode>"
;; is indexed or indirect before register allocation.
(define_expand "store_conditionalti"
- [(use (match_operand:CC 0 "cc_reg_operand" ""))
- (use (match_operand:TI 1 "memory_operand" ""))
- (use (match_operand:TI 2 "quad_int_reg_operand" ""))]
+ [(use (match_operand:CC 0 "cc_reg_operand"))
+ (use (match_operand:TI 1 "memory_operand"))
+ (use (match_operand:TI 2 "quad_int_reg_operand"))]
"TARGET_SYNC_TI"
{
rtx op0 = operands[0];
@@ -385,14 +385,14 @@ (define_insn "store_conditionalpti"
[(set_attr "type" "store_c")])
(define_expand "atomic_compare_and_swap<mode>"
- [(match_operand:SI 0 "int_reg_operand" "") ;; bool out
- (match_operand:AINT 1 "int_reg_operand" "") ;; val out
- (match_operand:AINT 2 "memory_operand" "") ;; memory
- (match_operand:AINT 3 "reg_or_short_operand" "") ;; expected
- (match_operand:AINT 4 "int_reg_operand" "") ;; desired
- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
- (match_operand:SI 6 "const_int_operand" "") ;; model succ
- (match_operand:SI 7 "const_int_operand" "")] ;; model fail
+ [(match_operand:SI 0 "int_reg_operand") ;; bool out
+ (match_operand:AINT 1 "int_reg_operand") ;; val out
+ (match_operand:AINT 2 "memory_operand") ;; memory
+ (match_operand:AINT 3 "reg_or_short_operand") ;; expected
+ (match_operand:AINT 4 "int_reg_operand") ;; desired
+ (match_operand:SI 5 "const_int_operand") ;; is_weak
+ (match_operand:SI 6 "const_int_operand") ;; model succ
+ (match_operand:SI 7 "const_int_operand")] ;; model fail
""
{
rs6000_expand_atomic_compare_and_swap (operands);
@@ -400,10 +400,10 @@ (define_expand "atomic_compare_and_swap<mode>"
})
(define_expand "atomic_exchange<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
- (match_operand:AINT 2 "int_reg_operand" "") ;; input
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
+ (match_operand:AINT 2 "int_reg_operand") ;; input
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_exchange (operands);
@@ -411,10 +411,10 @@ (define_expand "atomic_exchange<mode>"
})
(define_expand "atomic_<fetchop_name><mode>"
- [(match_operand:AINT 0 "memory_operand" "") ;; memory
+ [(match_operand:AINT 0 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 0)
- (match_operand:AINT 1 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 2 "const_int_operand" "")] ;; model
+ (match_operand:AINT 1 "<fetchop_pred>")) ;; operand
+ (match_operand:SI 2 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[0], operands[1],
@@ -423,9 +423,9 @@ (define_expand "atomic_<fetchop_name><mode>"
})
(define_expand "atomic_nand<mode>"
- [(match_operand:AINT 0 "memory_operand" "") ;; memory
- (match_operand:AINT 1 "int_reg_operand" "") ;; operand
- (match_operand:SI 2 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "memory_operand") ;; memory
+ (match_operand:AINT 1 "int_reg_operand") ;; operand
+ (match_operand:SI 2 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[0], operands[1],
@@ -434,11 +434,11 @@ (define_expand "atomic_nand<mode>"
})
(define_expand "atomic_fetch_<fetchop_name><mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 1)
- (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ (match_operand:AINT 2 "<fetchop_pred>")) ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
@@ -447,10 +447,10 @@ (define_expand "atomic_fetch_<fetchop_name><mode>"
})
(define_expand "atomic_fetch_nand<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
- (match_operand:AINT 2 "int_reg_operand" "") ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
+ (match_operand:AINT 2 "int_reg_operand") ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[1], operands[2],
@@ -459,11 +459,11 @@ (define_expand "atomic_fetch_nand<mode>"
})
(define_expand "atomic_<fetchop_name>_fetch<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 1)
- (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ (match_operand:AINT 2 "<fetchop_pred>")) ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
@@ -472,10 +472,10 @@ (define_expand "atomic_<fetchop_name>_fetch<mode>"
})
(define_expand "atomic_nand_fetch<mode>"
- [(match_operand:AINT 0 "int_reg_operand" "") ;; output
- (match_operand:AINT 1 "memory_operand" "") ;; memory
- (match_operand:AINT 2 "int_reg_operand" "") ;; operand
- (match_operand:SI 3 "const_int_operand" "")] ;; model
+ [(match_operand:AINT 0 "int_reg_operand") ;; output
+ (match_operand:AINT 1 "memory_operand") ;; memory
+ (match_operand:AINT 2 "int_reg_operand") ;; operand
+ (match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[1], operands[2],
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 0a58a75..6e2576e 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -111,8 +111,8 @@ (define_code_attr VEC_reduc_rtx [(plus "add")
;; Vector move instructions. Little-endian VSX loads and stores require
;; special handling to circumvent "element endianness."
(define_expand "mov<mode>"
- [(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
- (match_operand:VEC_M 1 "any_operand" ""))]
+ [(set (match_operand:VEC_M 0 "nonimmediate_operand")
+ (match_operand:VEC_M 1 "any_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (can_create_pseudo_p ())
@@ -147,21 +147,21 @@ (define_expand "mov<mode>"
;; Generic vector floating point load/store instructions. These will match
;; insns defined in vsx.md or altivec.md depending on the switches.
(define_expand "vector_load_<mode>"
- [(set (match_operand:VEC_M 0 "vfloat_operand" "")
- (match_operand:VEC_M 1 "memory_operand" ""))]
+ [(set (match_operand:VEC_M 0 "vfloat_operand")
+ (match_operand:VEC_M 1 "memory_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_store_<mode>"
- [(set (match_operand:VEC_M 0 "memory_operand" "")
- (match_operand:VEC_M 1 "vfloat_operand" ""))]
+ [(set (match_operand:VEC_M 0 "memory_operand")
+ (match_operand:VEC_M 1 "vfloat_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Splits if a GPR register was chosen for the move
(define_split
- [(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
- (match_operand:VEC_L 1 "input_operand" ""))]
+ [(set (match_operand:VEC_L 0 "nonimmediate_operand")
+ (match_operand:VEC_L 1 "input_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
&& reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])
@@ -178,8 +178,8 @@ (define_split
;; instructions silently ignore the bottom 3 bits of the address, and VSX does
;; not.
(define_expand "vector_altivec_load_<mode>"
- [(set (match_operand:VEC_M 0 "vfloat_operand" "")
- (match_operand:VEC_M 1 "memory_operand" ""))]
+ [(set (match_operand:VEC_M 0 "vfloat_operand")
+ (match_operand:VEC_M 1 "memory_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
@@ -200,8 +200,8 @@ (define_expand "vector_altivec_load_<mode>"
})
(define_expand "vector_altivec_store_<mode>"
- [(set (match_operand:VEC_M 0 "memory_operand" "")
- (match_operand:VEC_M 1 "vfloat_operand" ""))]
+ [(set (match_operand:VEC_M 0 "memory_operand")
+ (match_operand:VEC_M 1 "vfloat_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
@@ -225,23 +225,23 @@ (define_expand "vector_altivec_store_<mode>"
\f
;; Generic floating point vector arithmetic support
(define_expand "add<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "sub<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "mul<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -252,9 +252,9 @@ (define_expand "mul<mode>3"
})
(define_expand "div<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
{
if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
@@ -267,8 +267,8 @@ (define_expand "div<mode>3"
})
(define_expand "neg<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -279,8 +279,8 @@ (define_expand "neg<mode>2"
})
(define_expand "abs<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -291,23 +291,23 @@ (define_expand "abs<mode>2"
})
(define_expand "smin<mode>3"
- [(set (match_operand:VEC_F 0 "register_operand" "")
- (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
- (match_operand:VEC_F 2 "register_operand" "")))]
+ [(set (match_operand:VEC_F 0 "register_operand")
+ (smin:VEC_F (match_operand:VEC_F 1 "register_operand")
+ (match_operand:VEC_F 2 "register_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "smax<mode>3"
- [(set (match_operand:VEC_F 0 "register_operand" "")
- (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
- (match_operand:VEC_F 2 "register_operand" "")))]
+ [(set (match_operand:VEC_F 0 "register_operand")
+ (smax:VEC_F (match_operand:VEC_F 1 "register_operand")
+ (match_operand:VEC_F 2 "register_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "sqrt<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode
@@ -321,49 +321,49 @@ (define_expand "sqrt<mode>2"
})
(define_expand "rsqrte<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_RSQRT))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "re<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRES))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "ftrunc<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_ceil<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRIP))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_floor<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRIM))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_btrunc<mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_copysign<mode>3"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -377,13 +377,13 @@ (define_expand "vector_copysign<mode>3"
\f
;; Vector comparisons
(define_expand "vcond<mode><mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
(if_then_else:VEC_F
(match_operator 3 "comparison_operator"
- [(match_operand:VEC_F 4 "vfloat_operand" "")
- (match_operand:VEC_F 5 "vfloat_operand" "")])
- (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(match_operand:VEC_F 4 "vfloat_operand")
+ (match_operand:VEC_F 5 "vfloat_operand")])
+ (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
@@ -411,13 +411,13 @@ (define_expand "vcond<mode><mode>"
})
(define_expand "vcondv4sfv4si"
- [(set (match_operand:V4SF 0 "vfloat_operand" "")
+ [(set (match_operand:V4SF 0 "vfloat_operand")
(if_then_else:V4SF
(match_operator 3 "comparison_operator"
- [(match_operand:V4SI 4 "vint_operand" "")
- (match_operand:V4SI 5 "vint_operand" "")])
- (match_operand:V4SF 1 "vfloat_operand" "")
- (match_operand:V4SF 2 "vfloat_operand" "")))]
+ [(match_operand:V4SI 4 "vint_operand")
+ (match_operand:V4SI 5 "vint_operand")])
+ (match_operand:V4SF 1 "vfloat_operand")
+ (match_operand:V4SF 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
@@ -429,13 +429,13 @@ (define_expand "vcondv4sfv4si"
})
(define_expand "vcondv4siv4sf"
- [(set (match_operand:V4SI 0 "vint_operand" "")
+ [(set (match_operand:V4SI 0 "vint_operand")
(if_then_else:V4SI
(match_operator 3 "comparison_operator"
- [(match_operand:V4SF 4 "vfloat_operand" "")
- (match_operand:V4SF 5 "vfloat_operand" "")])
- (match_operand:V4SI 1 "vint_operand" "")
- (match_operand:V4SI 2 "vint_operand" "")))]
+ [(match_operand:V4SF 4 "vfloat_operand")
+ (match_operand:V4SF 5 "vfloat_operand")])
+ (match_operand:V4SI 1 "vint_operand")
+ (match_operand:V4SI 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
@@ -500,13 +500,13 @@ (define_expand "vcondu<mode><mode>"
})
(define_expand "vconduv4sfv4si"
- [(set (match_operand:V4SF 0 "vfloat_operand" "")
+ [(set (match_operand:V4SF 0 "vfloat_operand")
(if_then_else:V4SF
(match_operator 3 "comparison_operator"
- [(match_operand:V4SI 4 "vint_operand" "")
- (match_operand:V4SI 5 "vint_operand" "")])
- (match_operand:V4SF 1 "vfloat_operand" "")
- (match_operand:V4SF 2 "vfloat_operand" "")))]
+ [(match_operand:V4SI 4 "vint_operand")
+ (match_operand:V4SI 5 "vint_operand")])
+ (match_operand:V4SF 1 "vfloat_operand")
+ (match_operand:V4SF 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
@@ -536,32 +536,32 @@ (define_expand "vconduv2dfv2di"
})
(define_expand "vector_eq<mode>"
- [(set (match_operand:VEC_C 0 "vlogical_operand" "")
- (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
- (match_operand:VEC_C 2 "vlogical_operand" "")))]
+ [(set (match_operand:VEC_C 0 "vlogical_operand")
+ (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
+ (match_operand:VEC_C 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_gt<mode>"
- [(set (match_operand:VEC_C 0 "vlogical_operand" "")
- (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
- (match_operand:VEC_C 2 "vlogical_operand" "")))]
+ [(set (match_operand:VEC_C 0 "vlogical_operand")
+ (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
+ (match_operand:VEC_C 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_ge<mode>"
- [(set (match_operand:VEC_F 0 "vlogical_operand" "")
- (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand" "")
- (match_operand:VEC_F 2 "vlogical_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vlogical_operand")
+ (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand")
+ (match_operand:VEC_F 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; >= for integer vectors: swap operands and apply not-greater-than
(define_expand "vector_nlt<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
- (match_operand:VEC_I 1 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
+ (match_operand:VEC_I 1 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@@ -569,18 +569,18 @@ (define_expand "vector_nlt<mode>"
})
(define_expand "vector_gtu<mode>"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; >= for integer vectors: swap operands and apply not-greater-than
(define_expand "vector_nltu<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
- (match_operand:VEC_I 1 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
+ (match_operand:VEC_I 1 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@@ -588,18 +588,18 @@ (define_expand "vector_nltu<mode>"
})
(define_expand "vector_geu<mode>"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (geu:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; <= for integer vectors: apply not-greater-than
(define_expand "vector_ngt<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
- (match_operand:VEC_I 2 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
+ (match_operand:VEC_I 2 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@@ -607,10 +607,10 @@ (define_expand "vector_ngt<mode>"
})
(define_expand "vector_ngtu<mode>"
- [(set (match_operand:VEC_I 3 "vlogical_operand" "")
- (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
- (match_operand:VEC_I 2 "vlogical_operand" "")))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_I 3 "vlogical_operand")
+ (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
+ (match_operand:VEC_I 2 "vlogical_operand")))
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@@ -618,9 +618,9 @@ (define_expand "vector_ngtu<mode>"
})
(define_insn_and_split "*vector_uneq<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@@ -639,9 +639,9 @@ (define_insn_and_split "*vector_uneq<mode>"
})
(define_insn_and_split "*vector_ltgt<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@@ -660,9 +660,9 @@ (define_insn_and_split "*vector_ltgt<mode>"
})
(define_insn_and_split "*vector_ordered<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@@ -681,9 +681,9 @@ (define_insn_and_split "*vector_ordered<mode>"
})
(define_insn_and_split "*vector_unordered<mode>"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@@ -704,22 +704,22 @@ (define_insn_and_split "*vector_unordered<mode>"
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
;; which is in the reverse order that we want
(define_expand "vector_select_<mode>"
- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_L 0 "vlogical_operand")
(if_then_else:VEC_L
- (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
+ (ne:CC (match_operand:VEC_L 3 "vlogical_operand")
(match_dup 4))
- (match_operand:VEC_L 2 "vlogical_operand" "")
- (match_operand:VEC_L 1 "vlogical_operand" "")))]
+ (match_operand:VEC_L 2 "vlogical_operand")
+ (match_operand:VEC_L 1 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"operands[4] = CONST0_RTX (<MODE>mode);")
(define_expand "vector_select_<mode>_uns"
- [(set (match_operand:VEC_L 0 "vlogical_operand" "")
+ [(set (match_operand:VEC_L 0 "vlogical_operand")
(if_then_else:VEC_L
- (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
+ (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand")
(match_dup 4))
- (match_operand:VEC_L 2 "vlogical_operand" "")
- (match_operand:VEC_L 1 "vlogical_operand" "")))]
+ (match_operand:VEC_L 2 "vlogical_operand")
+ (match_operand:VEC_L 1 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"operands[4] = CONST0_RTX (<MODE>mode);")
@@ -728,10 +728,10 @@ (define_expand "vector_select_<mode>_uns"
(define_expand "vector_eq_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
- (match_operand:VEC_A 2 "vlogical_operand" ""))]
+ (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand")
+ (match_operand:VEC_A 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_A 0 "vlogical_operand" "")
+ (set (match_operand:VEC_A 0 "vlogical_operand")
(eq:VEC_A (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@@ -895,10 +895,10 @@ (define_expand "vector_ae_<mode>_p"
(define_expand "vector_gt_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
- (match_operand:VEC_A 2 "vlogical_operand" ""))]
+ (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand")
+ (match_operand:VEC_A 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_A 0 "vlogical_operand" "")
+ (set (match_operand:VEC_A 0 "vlogical_operand")
(gt:VEC_A (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@@ -907,10 +907,10 @@ (define_expand "vector_gt_<mode>_p"
(define_expand "vector_ge_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
- (match_operand:VEC_F 2 "vfloat_operand" ""))]
+ (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand")
+ (match_operand:VEC_F 2 "vfloat_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_F 0 "vfloat_operand" "")
+ (set (match_operand:VEC_F 0 "vfloat_operand")
(ge:VEC_F (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@@ -919,10 +919,10 @@ (define_expand "vector_ge_<mode>_p"
(define_expand "vector_gtu_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
- (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" ""))]
+ (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand"))]
UNSPEC_PREDICATE))
- (set (match_operand:VEC_I 0 "vlogical_operand" "")
+ (set (match_operand:VEC_I 0 "vlogical_operand")
(gtu:VEC_I (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@@ -984,33 +984,33 @@ (define_expand "cr6_test_for_lt_reverse"
\f
;; Vector count leading zeros
(define_expand "clz<mode>2"
- [(set (match_operand:VEC_I 0 "register_operand" "")
- (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
+ [(set (match_operand:VEC_I 0 "register_operand")
+ (clz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P8_VECTOR")
;; Vector count trailing zeros
(define_expand "ctz<mode>2"
- [(set (match_operand:VEC_I 0 "register_operand" "")
- (ctz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
+ [(set (match_operand:VEC_I 0 "register_operand")
+ (ctz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P9_VECTOR")
;; Vector population count
(define_expand "popcount<mode>2"
- [(set (match_operand:VEC_I 0 "register_operand" "")
- (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
+ [(set (match_operand:VEC_I 0 "register_operand")
+ (popcount:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P8_VECTOR")
;; Vector parity
(define_expand "parity<mode>2"
- [(set (match_operand:VEC_IP 0 "register_operand" "")
- (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand" "")))]
+ [(set (match_operand:VEC_IP 0 "register_operand")
+ (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand")))]
"TARGET_P9_VECTOR")
\f
;; Same size conversions
(define_expand "float<VEC_int><mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -1021,8 +1021,8 @@ (define_expand "float<VEC_int><mode>2"
})
(define_expand "floatuns<VEC_int><mode>2"
- [(set (match_operand:VEC_F 0 "vfloat_operand" "")
- (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
+ [(set (match_operand:VEC_F 0 "vfloat_operand")
+ (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -1033,8 +1033,8 @@ (define_expand "floatuns<VEC_int><mode>2"
})
(define_expand "fix_trunc<mode><VEC_int>2"
- [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
- (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:<VEC_INT> 0 "vint_operand")
+ (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -1045,8 +1045,8 @@ (define_expand "fix_trunc<mode><VEC_int>2"
})
(define_expand "fixuns_trunc<mode><VEC_int>2"
- [(set (match_operand:<VEC_INT> 0 "vint_operand" "")
- (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
+ [(set (match_operand:<VEC_INT> 0 "vint_operand")
+ (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@@ -1059,8 +1059,8 @@ (define_expand "fixuns_trunc<mode><VEC_int>2"
\f
;; Vector initialization, set, extract
(define_expand "vec_init<mode><VEC_base_l>"
- [(match_operand:VEC_E 0 "vlogical_operand" "")
- (match_operand:VEC_E 1 "" "")]
+ [(match_operand:VEC_E 0 "vlogical_operand")
+ (match_operand:VEC_E 1 "")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_init (operands[0], operands[1]);
@@ -1068,9 +1068,9 @@ (define_expand "vec_init<mode><VEC_base_l>"
})
(define_expand "vec_set<mode>"
- [(match_operand:VEC_E 0 "vlogical_operand" "")
- (match_operand:<VEC_base> 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:VEC_E 0 "vlogical_operand")
+ (match_operand:<VEC_base> 1 "register_operand")
+ (match_operand 2 "const_int_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
@@ -1078,9 +1078,9 @@ (define_expand "vec_set<mode>"
})
(define_expand "vec_extract<mode><VEC_base_l>"
- [(match_operand:<VEC_base> 0 "register_operand" "")
- (match_operand:VEC_E 1 "vlogical_operand" "")
- (match_operand 2 "const_int_operand" "")]
+ [(match_operand:<VEC_base> 0 "register_operand")
+ (match_operand:VEC_E 1 "vlogical_operand")
+ (match_operand 2 "const_int_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_extract (operands[0], operands[1], operands[2]);
@@ -1089,9 +1089,9 @@ (define_expand "vec_extract<mode><VEC_base_l>"
\f
;; Convert double word types to single word types
(define_expand "vec_pack_trunc_v2df"
- [(match_operand:V4SF 0 "vfloat_operand" "")
- (match_operand:V2DF 1 "vfloat_operand" "")
- (match_operand:V2DF 2 "vfloat_operand" "")]
+ [(match_operand:V4SF 0 "vfloat_operand")
+ (match_operand:V2DF 1 "vfloat_operand")
+ (match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SFmode);
@@ -1104,9 +1104,9 @@ (define_expand "vec_pack_trunc_v2df"
})
(define_expand "vec_pack_sfix_trunc_v2df"
- [(match_operand:V4SI 0 "vint_operand" "")
- (match_operand:V2DF 1 "vfloat_operand" "")
- (match_operand:V2DF 2 "vfloat_operand" "")]
+ [(match_operand:V4SI 0 "vint_operand")
+ (match_operand:V2DF 1 "vfloat_operand")
+ (match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SImode);
@@ -1119,9 +1119,9 @@ (define_expand "vec_pack_sfix_trunc_v2df"
})
(define_expand "vec_pack_ufix_trunc_v2df"
- [(match_operand:V4SI 0 "vint_operand" "")
- (match_operand:V2DF 1 "vfloat_operand" "")
- (match_operand:V2DF 2 "vfloat_operand" "")]
+ [(match_operand:V4SI 0 "vint_operand")
+ (match_operand:V2DF 1 "vfloat_operand")
+ (match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SImode);
@@ -1135,8 +1135,8 @@ (define_expand "vec_pack_ufix_trunc_v2df"
;; Convert single word types to double word
(define_expand "vec_unpacks_hi_v4sf"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SF 1 "vfloat_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SF 1 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
{
rtx reg = gen_reg_rtx (V4SFmode);
@@ -1147,8 +1147,8 @@ (define_expand "vec_unpacks_hi_v4sf"
})
(define_expand "vec_unpacks_lo_v4sf"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SF 1 "vfloat_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SF 1 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
{
rtx reg = gen_reg_rtx (V4SFmode);
@@ -1159,8 +1159,8 @@ (define_expand "vec_unpacks_lo_v4sf"
})
(define_expand "vec_unpacks_float_hi_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@@ -1171,8 +1171,8 @@ (define_expand "vec_unpacks_float_hi_v4si"
})
(define_expand "vec_unpacks_float_lo_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@@ -1183,8 +1183,8 @@ (define_expand "vec_unpacks_float_lo_v4si"
})
(define_expand "vec_unpacku_float_hi_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@@ -1195,8 +1195,8 @@ (define_expand "vec_unpacku_float_hi_v4si"
})
(define_expand "vec_unpacku_float_lo_v4si"
- [(match_operand:V2DF 0 "vfloat_operand" "")
- (match_operand:V4SI 1 "vint_operand" "")]
+ [(match_operand:V2DF 0 "vfloat_operand")
+ (match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@@ -1209,10 +1209,10 @@ (define_expand "vec_unpacku_float_lo_v4si"
\f
;; Align vector loads with a permute.
(define_expand "vec_realign_load_<mode>"
- [(match_operand:VEC_K 0 "vlogical_operand" "")
- (match_operand:VEC_K 1 "vlogical_operand" "")
- (match_operand:VEC_K 2 "vlogical_operand" "")
- (match_operand:V16QI 3 "vlogical_operand" "")]
+ [(match_operand:VEC_K 0 "vlogical_operand")
+ (match_operand:VEC_K 1 "vlogical_operand")
+ (match_operand:VEC_K 2 "vlogical_operand")
+ (match_operand:V16QI 3 "vlogical_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (BYTES_BIG_ENDIAN)
@@ -1234,8 +1234,8 @@ (define_expand "vec_realign_load_<mode>"
;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
;; since the load already handles it.
(define_expand "movmisalign<mode>"
- [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
- (match_operand:VEC_N 1 "any_operand" ""))]
+ [(set (match_operand:VEC_N 0 "nonimmediate_operand")
+ (match_operand:VEC_N 1 "any_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
"")
@@ -1247,9 +1247,9 @@ (define_expand "movmisalign<mode>"
;; Note that the vec_shr operation is actually defined as
;; 'shift toward element 0' so is a shr for LE and shl for BE.
(define_expand "vec_shr_<mode>"
- [(match_operand:VEC_L 0 "vlogical_operand" "")
- (match_operand:VEC_L 1 "vlogical_operand" "")
- (match_operand:QI 2 "reg_or_short_operand" "")]
+ [(match_operand:VEC_L 0 "vlogical_operand")
+ (match_operand:VEC_L 1 "vlogical_operand")
+ (match_operand:QI 2 "reg_or_short_operand")]
"TARGET_ALTIVEC"
{
rtx bitshift = operands[2];
@@ -1296,33 +1296,33 @@ (define_expand "vec_shr_<mode>"
;; Expanders for rotate each element in a vector
(define_expand "vrotl<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for arithmetic shift left on each vector element
(define_expand "vashl<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for logical shift right on each vector element
(define_expand "vlshr<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for arithmetic shift right on each vector element
(define_expand "vashr<mode>3"
- [(set (match_operand:VEC_I 0 "vint_operand" "")
- (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
- (match_operand:VEC_I 2 "vint_operand" "")))]
+ [(set (match_operand:VEC_I 0 "vint_operand")
+ (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
+ (match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
\f
@@ -1336,8 +1336,8 @@ (define_expand "vashr<mode>3"
(define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
- [(match_operand:<VEC_base> 0 "register_operand" "")
- (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
+ [(match_operand:<VEC_base> 0 "register_operand")
+ (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))]
"VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)"
{
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9249ce5..a65ff75 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -652,8 +652,8 @@ (define_insn "*vsx_le_perm_store_<mode>"
(set_attr "length" "12")])
(define_split
- [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_D 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_D 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:<MODE>
@@ -696,8 +696,8 @@ (define_split
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_D 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_D 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:<MODE>
@@ -722,8 +722,8 @@ (define_insn "*vsx_le_perm_store_<mode>"
(set_attr "length" "12")])
(define_split
- [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_W 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_W 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:<MODE>
@@ -768,8 +768,8 @@ (define_split
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
- (match_operand:VSX_W 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand")
+ (match_operand:VSX_W 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:<MODE>
@@ -797,8 +797,8 @@ (define_insn "*vsx_le_perm_store_v8hi"
(set_attr "length" "12")])
(define_split
- [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
- (match_operand:V8HI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V8HI 0 "indexed_or_indirect_operand")
+ (match_operand:V8HI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:V8HI
@@ -847,8 +847,8 @@ (define_split
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
- (match_operand:V8HI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V8HI 0 "indexed_or_indirect_operand")
+ (match_operand:V8HI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:V8HI
@@ -882,8 +882,8 @@ (define_insn "*vsx_le_perm_store_v16qi"
(set_attr "length" "12")])
(define_split
- [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
- (match_operand:V16QI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V16QI 0 "indexed_or_indirect_operand")
+ (match_operand:V16QI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:V16QI
@@ -940,8 +940,8 @@ (define_split
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
- (match_operand:V16QI 1 "vsx_register_operand" ""))]
+ [(set (match_operand:V16QI 0 "indexed_or_indirect_operand")
+ (match_operand:V16QI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:V16QI
@@ -1051,8 +1051,8 @@ (define_insn "*vsx_le_perm_store_<mode>"
(set_attr "length" "12,8")])
(define_split
- [(set (match_operand:VSX_LE_128 0 "memory_operand" "")
- (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_LE_128 0 "memory_operand")
+ (match_operand:VSX_LE_128 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR"
[(const_int 0)]
{
@@ -1093,10 +1093,10 @@ (define_peephole2
;; VSX registers on a little endian system. The vector types and IEEE 128-bit
;; floating point are handled by the more generic swap elimination pass.
(define_peephole2
- [(set (match_operand:TI 0 "vsx_register_operand" "")
- (rotate:TI (match_operand:TI 1 "vsx_register_operand" "")
+ [(set (match_operand:TI 0 "vsx_register_operand")
+ (rotate:TI (match_operand:TI 1 "vsx_register_operand")
(const_int 64)))
- (set (match_operand:TI 2 "vsx_register_operand" "")
+ (set (match_operand:TI 2 "vsx_register_operand")
(rotate:TI (match_dup 0)
(const_int 64)))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
@@ -1107,8 +1107,8 @@ (define_peephole2
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:VSX_LE_128 0 "memory_operand" "")
- (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_LE_128 0 "memory_operand")
+ (match_operand:VSX_LE_128 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR"
[(const_int 0)]
{
@@ -1256,8 +1256,8 @@ (define_insn "*vsx_mov<mode>_32bit"
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
- [(set (match_operand:VSX_M 0 "vsx_register_operand" "")
- (match_operand:VSX_M 1 "memory_operand" ""))]
+ [(set (match_operand:VSX_M 0 "vsx_register_operand")
+ (match_operand:VSX_M 1 "memory_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
/* Expand to swaps if needed, prior to swap optimization. */
@@ -1269,8 +1269,8 @@ (define_expand "vsx_load_<mode>"
})
(define_expand "vsx_store_<mode>"
- [(set (match_operand:VSX_M 0 "memory_operand" "")
- (match_operand:VSX_M 1 "vsx_register_operand" ""))]
+ [(set (match_operand:VSX_M 0 "memory_operand")
+ (match_operand:VSX_M 1 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
/* Expand to swaps if needed, prior to swap optimization. */
@@ -1767,10 +1767,10 @@ (define_insn_and_split "vsx_udiv_v2di"
;; *tdiv* instruction returning the FG flag
(define_expand "vsx_tdiv<mode>3_fg"
[(set (match_dup 3)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
- (match_operand:VSX_B 2 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")
+ (match_operand:VSX_B 2 "vsx_register_operand")]
UNSPEC_VSX_TDIV))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(gt:SI (match_dup 3)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -1781,10 +1781,10 @@ (define_expand "vsx_tdiv<mode>3_fg"
;; *tdiv* instruction returning the FE flag
(define_expand "vsx_tdiv<mode>3_fe"
[(set (match_dup 3)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
- (match_operand:VSX_B 2 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")
+ (match_operand:VSX_B 2 "vsx_register_operand")]
UNSPEC_VSX_TDIV))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(eq:SI (match_dup 3)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -1875,9 +1875,9 @@ (define_insn "*vsx_rsqrte<mode>2"
;; *tsqrt* returning the fg flag
(define_expand "vsx_tsqrt<mode>2_fg"
[(set (match_dup 2)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")]
UNSPEC_VSX_TSQRT))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(gt:SI (match_dup 2)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -1888,9 +1888,9 @@ (define_expand "vsx_tsqrt<mode>2_fg"
;; *tsqrt* returning the fe flag
(define_expand "vsx_tsqrt<mode>2_fe"
[(set (match_dup 2)
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")]
UNSPEC_VSX_TSQRT))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand")
(eq:SI (match_dup 2)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -2290,9 +2290,9 @@ (define_insn "vsx_xscvspdpn_directmove"
;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long)
(define_expand "vsx_xvcvsxddp_scale"
- [(match_operand:V2DF 0 "vsx_register_operand" "")
- (match_operand:V2DI 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DF 0 "vsx_register_operand")
+ (match_operand:V2DI 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@@ -2313,9 +2313,9 @@ (define_insn "vsx_xvcvsxddp"
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvuxddp_scale"
- [(match_operand:V2DF 0 "vsx_register_operand" "")
- (match_operand:V2DI 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DF 0 "vsx_register_operand")
+ (match_operand:V2DI 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@@ -2336,9 +2336,9 @@ (define_insn "vsx_xvcvuxddp"
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvdpsxds_scale"
- [(match_operand:V2DI 0 "vsx_register_operand" "")
- (match_operand:V2DF 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DI 0 "vsx_register_operand")
+ (match_operand:V2DF 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@@ -2379,9 +2379,9 @@ (define_insn "vsx_xvcvspsxws"
;; convert vector of 64-bit floating point numbers to vector of
;; 64-bit unsigned integer
(define_expand "vsx_xvcvdpuxds_scale"
- [(match_operand:V2DI 0 "vsx_register_operand" "")
- (match_operand:V2DF 1 "vsx_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")]
+ [(match_operand:V2DI 0 "vsx_register_operand")
+ (match_operand:V2DF 1 "vsx_register_operand")
+ (match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@@ -3148,10 +3148,10 @@ (define_insn "*vsx_stxvd2x16_le_V16QI"
;; Convert a TImode value into V1TImode
(define_expand "vsx_set_v1ti"
- [(match_operand:V1TI 0 "nonimmediate_operand" "")
- (match_operand:V1TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "input_operand" "")
- (match_operand:QI 3 "u5bit_cint_operand" "")]
+ [(match_operand:V1TI 0 "nonimmediate_operand")
+ (match_operand:V1TI 1 "nonimmediate_operand")
+ (match_operand:TI 2 "input_operand")
+ (match_operand:QI 3 "u5bit_cint_operand")]
"VECTOR_MEM_VSX_P (V1TImode)"
{
if (operands[3] != const0_rtx)
@@ -4065,9 +4065,9 @@ (define_insn_and_split "*vsx_insert_extract_v4sf_p9_2"
;; Expanders for builtins
(define_expand "vsx_mergel_<mode>"
- [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
+ [(use (match_operand:VSX_D 0 "vsx_register_operand"))
+ (use (match_operand:VSX_D 1 "vsx_register_operand"))
+ (use (match_operand:VSX_D 2 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
rtvec v;
@@ -4091,9 +4091,9 @@ (define_expand "vsx_mergel_<mode>"
})
(define_expand "vsx_mergeh_<mode>"
- [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 1 "vsx_register_operand" ""))
- (use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
+ [(use (match_operand:VSX_D 0 "vsx_register_operand"))
+ (use (match_operand:VSX_D 1 "vsx_register_operand"))
+ (use (match_operand:VSX_D 2 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
rtvec v;
@@ -4445,21 +4445,21 @@ (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v4sf_scalar"
\f
;; Power8 Vector fusion. The fused ops must be physically adjacent.
(define_peephole
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "short_cint_operand" ""))
- (set (match_operand:VSX_M 2 "vsx_register_operand" "")
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "short_cint_operand"))
+ (set (match_operand:VSX_M 2 "vsx_register_operand")
(mem:VSX_M (plus:P (match_dup 0)
- (match_operand:P 3 "int_reg_operand" ""))))]
+ (match_operand:P 3 "int_reg_operand"))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
"li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
(define_peephole
- [(set (match_operand:P 0 "base_reg_operand" "")
- (match_operand:P 1 "short_cint_operand" ""))
- (set (match_operand:VSX_M 2 "vsx_register_operand" "")
- (mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand" "")
+ [(set (match_operand:P 0 "base_reg_operand")
+ (match_operand:P 1 "short_cint_operand"))
+ (set (match_operand:VSX_M 2 "vsx_register_operand")
+ (mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand")
(match_dup 0))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
"li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"
--
1.8.3.1
^ permalink raw reply [flat|nested] 2+ messages in thread
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2018-02-22 1:09 [PATCH 1/2] rs6000: Use brace blocks in define_insn Segher Boessenkool
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