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From: will schmidt <will_schmidt@vnet.ibm.com>
To: Carl Love <cel@us.ibm.com>,
	segher@gcc.gnu.org, dje.gcc@gmail.com, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 3/5] Add TI to TD (128-bit DFP) and TD to TI support
Date: Thu, 08 Oct 2020 09:22:51 -0500	[thread overview]
Message-ID: <8498915202b4a00d9ae49b754c5b809ffa06db99.camel@vnet.ibm.com> (raw)
In-Reply-To: <83fcf5b2c9a66ed7fd187209328f8c6015331a1c.camel@us.ibm.com>

On Mon, 2020-10-05 at 11:52 -0700, Carl Love wrote:
> Will, Segher:
> 
> Add support for converting to/from 128-bit integers and 128-bit 
> decimal floating point formats.
> 
> The updates from the previous version of the patch:
> 
> Just a fix for the change log per Will's comments.
> 
> No regression failures were found when run on a P9.
> 
> Please let me know if this is ready for mainline. 
> 
>                Carl
> 
> --------------------------------------------------------------
> 
> 
> gcc/ChangeLog
> 
> 2020-10-05  Carl Love  <cel@us.ibm.com>
> 	* config/rs6000/dfp.md (floattitd2, fixtdti2): New define_insns.
> 	* config/rs6000/rs6000-call.c (P10V_BUILTIN_VCMPNET_P, P10V_BUILTIN_VCMPAET_P):
> 	New overloaded definitions.
> 
> gcc/testsuite/ChangeLog
> 
> 2020-10-05  Carl Love  <cel@us.ibm.com>
> 	* gcc.target/powerpc/int_128bit-runnable.c:  Update test.


Maybe 'Add 128-bit DFP conversion tests' to give it better meaning.


> ---
>  gcc/config/rs6000/dfp.md                      | 14 +++++
>  gcc/config/rs6000/rs6000-call.c               |  4 ++
>  .../gcc.target/powerpc/int_128bit-runnable.c  | 62 +++++++++++++++++++
>  3 files changed, 80 insertions(+)
> 
> diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
> index 8f822732bac..0e82e315fee 100644
> --- a/gcc/config/rs6000/dfp.md
> +++ b/gcc/config/rs6000/dfp.md
> @@ -222,6 +222,13 @@
>    "dcffixq %0,%1"
>    [(set_attr "type" "dfp")])
> 
> +(define_insn "floattitd2"
> +  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> +	(float:TD (match_operand:TI 1 "gpc_reg_operand" "v")))]
> +  "TARGET_POWER10"
> +  "dcffixqq %0,%1"
> +  [(set_attr "type" "dfp")])
> +
>  ;; Convert a decimal64/128 to a decimal64/128 whose value is an integer.
>  ;; This is the first stage of converting it to an integer type.
> 
> @@ -241,6 +248,13 @@
>    "TARGET_DFP"
>    "dctfix<q> %0,%1"
>    [(set_attr "type" "dfp")])
> +
> +(define_insn "fixtdti2"
> +  [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
> +	(fix:TI (match_operand:TD 1 "gpc_reg_operand" "d")))]
> +  "TARGET_POWER10"
> +  "dctfixqq %0,%1"
> +  [(set_attr "type" "dfp")])
> 
>  ;; Decimal builtin support


ok

> 
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index 87fff5c1c80..8d00a25d806 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -4967,6 +4967,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
>      RS6000_BTI_bool_V2DI, 0 },
>    { P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P,
>      RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
> +  { P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P,
> +    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
> 
>    { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
>      RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
> @@ -5074,6 +5076,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
>      RS6000_BTI_bool_V2DI, 0 },
>    { P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P,
>      RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
> +  { P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P,
> +    RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 },
>    { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
>      RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
>    { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,

ok

> diff --git a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
> index 85ad544e22b..ec3dcf3dff1 100644
> --- a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
> +++ b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c
> @@ -38,6 +38,7 @@
>  #if DEBUG
>  #include <stdio.h>
>  #include <stdlib.h>
> +#include <math.h>
> 
> 
>  void print_i128(__int128_t val)
> @@ -59,6 +60,13 @@ int main ()
>    __int128_t arg1, result;
>    __uint128_t uarg2;
> 
> +  _Decimal128 arg1_dfp128, result_dfp128, expected_result_dfp128;
> +
> +  struct conv_t {
> +    __uint128_t u128;
> +    _Decimal128 d128;
> +  } conv, conv2;
> +
>    vector signed long long int vec_arg1_di, vec_arg2_di;
>    vector unsigned long long int vec_uarg1_di, vec_uarg2_di, vec_uarg3_di;
>    vector unsigned long long int vec_uresult_di;
> @@ -2249,6 +2257,60 @@ int main ()
>      abort();
>  #endif
>    }
> +  
> +  /* DFP to __int128 and __int128 to DFP conversions */
> +  /* Can't get printing of DFP values to work.  Print the DFP value as an
> +     unsigned int so we can see the bit patterns.  */

Drop 'Can't get ...', just 'Print the DFP...' should be sufficient.

> +  conv.u128 = 0x2208000000000000ULL;
> +  conv.u128 = (conv.u128 << 64) | 0x4ULL;   //DFP bit pattern for integer 4
> +  expected_result_dfp128 = conv.d128;
> 
> +  arg1 = 4;
> +
> +  conv.d128 = (_Decimal128) arg1;
> +
> +  result_dfp128 = (_Decimal128) arg1;
> +  if (((conv.u128 >>64) != 0x2208000000000000ULL) &&
> +      ((conv.u128 & 0xFFFFFFFFFFFFFFFF) != 0x4ULL)) {
> +#if DEBUG
> +    printf("ERROR:  convert int128 value ");
> +    print_i128 (arg1);
> +    conv.d128 = result_dfp128;
> +    printf("\nto DFP value 0x%llx %llx (printed as hex bit string) ",
> +	   (unsigned long long)((conv.u128) >>64),
> +	   (unsigned long long)((conv.u128) & 0xFFFFFFFFFFFFFFFF));
> +
> +    conv.d128 = expected_result_dfp128;
> +    printf("\ndoes not match expected_result = 0x%llx %llx\n\n",
> +	   (unsigned long long) (conv.u128>>64),
> +	   (unsigned long long) (conv.u128 & 0xFFFFFFFFFFFFFFFF));
> +#else
> +    abort();
> +#endif
> +  }
> +
> +  expected_result = 4;
> +
> +  conv.u128 = 0x2208000000000000ULL;
> +  conv.u128 = (conv.u128 << 64) | 0x4ULL;  // 4 as DFP
> +  arg1_dfp128 = conv.d128;
> +
> +  result = (__int128_t) arg1_dfp128;
> +
> +  if (result != expected_result) {
> +#if DEBUG
> +    printf("ERROR:  convert DFP value ");
> +    printf("0x%llx %llx (printed as hex bit string) ",
> +	   (unsigned long long)(conv.u128>>64),
> +	   (unsigned long long)(conv.u128 & 0xFFFFFFFFFFFFFFFF));
> +    printf("to __int128 value = ");
> +    print_i128 (result);
> +    printf("\ndoes not match expected_result = ");
> +    print_i128 (expected_result);
> +    printf("\n");
> +#else
> +    abort();
> +#endif
> +  }
>    return 0;
>  }


  reply	other threads:[~2020-10-08 14:22 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-21 21:17 [Patch 0/5] rs6000, 128-bit Binary Integer Operations Carl Love
2020-09-21 23:56 ` [PATCH 1/5] RS6000 Add 128-bit Binary Integer sign extend operations Carl Love
2020-09-24 18:20   ` will schmidt
2020-10-05 18:51     ` Carl Love
2020-10-07 21:08       ` will schmidt
2020-10-12 20:15         ` Carl Love
2020-10-12 20:51           ` Segher Boessenkool
2020-10-12 20:43         ` Segher Boessenkool
2020-10-12 21:06           ` Carl Love
2020-09-21 23:56 ` [PATCH 2/5] RS6000 add 128-bit Integer Operations Carl Love
2020-09-24 18:21   ` will schmidt
2020-10-05 18:52     ` [PATCH 2a/5] rs6000, vec_rlnm builtin fix arguments Carl Love
2020-10-07 21:08       ` will schmidt
2020-10-12 20:15         ` Carl Love
2020-10-12 23:37           ` Segher Boessenkool
2020-10-05 18:52     ` [PATCH 2b/5] RS6000 add 128-bit Integer Operations Carl Love
2020-10-07 21:53       ` will schmidt
2020-10-12 20:16         ` Carl Love
2020-10-13  0:23         ` Segher Boessenkool
2021-01-19 22:33           ` [PATCH 0/6 ver3] " Carl Love
2021-01-19 22:33           ` [PATCH 1/6 ver 3] rs6000, Fix arguments in altivec_vrlwmi and altivec_rlwdi builtins Carl Love
2021-01-19 22:33           ` [PATCH 2/6 ver 3] RS6000 Add 128-bit Binary Integer sign extend operations Carl Love
2021-01-19 22:33           ` [PATCH 3/6 ver 3] RS6000 add 128-bit Integer Operations part 1 Carl Love
2021-01-19 22:33           ` [PATCH 4/6 ver 3] Add TI to TD (128-bit DFP) and TD to TI support Carl Love
2021-01-19 22:33           ` [PATCH 5/6 ver 3] rs6000, Add test 128-bit shifts for just the int128 type Carl Love
2021-01-19 22:33           ` [PATCH 6/6 ver 3] Conversions between 128-bit integer and floating point values Carl Love
2020-09-21 23:56 ` [PATCH 3/5] Add TI to TD (128-bit DFP) and TD to TI support Carl Love
2020-09-24 18:21   ` will schmidt
2020-10-05 18:52     ` Carl Love
2020-10-08 14:22       ` will schmidt [this message]
2020-10-12 20:15         ` Carl Love
2020-09-21 23:56 ` [PATCH 4/5] Test 128-bit shifts for just the int128 type Carl Love
2020-09-24 18:21   ` will schmidt
2020-10-05 18:52     ` Carl Love
2020-10-08 14:50       ` will schmidt
2020-10-12 20:15         ` Carl Love
2020-09-21 23:57 ` [PATCH 5/5] Conversions between 128-bit integer and floating point values Carl Love
2020-09-24 18:22   ` will schmidt
2020-10-05 18:52     ` Carl Love
2020-10-08 15:35       ` will schmidt
2020-10-12 20:16         ` Carl Love

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