From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 66564 invoked by alias); 19 Feb 2018 15:32:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 66547 invoked by uid 89); 19 Feb 2018 15:32:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 19 Feb 2018 15:32:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1DADA1529; Mon, 19 Feb 2018 07:32:06 -0800 (PST) Received: from armament.cambridge.arm.com (armament.cambridge.arm.com [10.2.206.231]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A6353F318; Mon, 19 Feb 2018 07:32:04 -0800 (PST) Subject: Re: [Patch][aarch64][PR target/83335] Fix regression, ICE on gcc.target/aarch64/asm-2.c To: sellcey@cavium.com, gcc-patches , "james.greenhalgh" , Marcus Shawcroft , Christophe Lyon References: <1515190466.18339.14.camel@cavium.com> <1518825893.6296.12.camel@cavium.com> From: "Richard Earnshaw (lists)" Message-ID: <84d20171-cece-11b5-ffb7-dc897ad61caf@arm.com> Date: Mon, 19 Feb 2018 15:32:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1518825893.6296.12.camel@cavium.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-SW-Source: 2018-02/txt/msg01102.txt.bz2 On 17/02/18 00:04, Steve Ellcey wrote: > On Thu, 2018-02-15 at 14:01 +0000, Richard Earnshaw (lists) wrote: >>   >> Wouldn't it be better to call output_operand_lossage() with a suitable >> diagnostic message?  If the operand isn't in Pmode assembly will >> (should) fail anyway. >> >> R. > > How about this patch?  In addtion to the code change I updated asm-2.c > with the error message that you getin ILP32 mode and I added asm-4.c > which does not give an error message in either LP64 or ILP32 mode. > > Steve Ellcey > sellcey@cavium.com > > 2018-02-16  Steve Ellcey   > > PR target/83335 > * config/aarch64/aarch64.c (aarch64_print_address_internal): > Change gcc_assert call to output_operand_lossage. I think this is OK. However, I note that __builtin_extend_pointer is undocumented (it appears to be intended only for use in the exception unwinding code). Should it now be made an officially supported builtin? It appears to be the only semi-portable way of getting a Pmode address out of a language level pointer and thus important for use on targets where the two differ in size. R. > > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index 7c9c6e5..34b75f8 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -7044,7 +7044,8 @@ aarch64_print_address_internal (FILE *f, machine_mode mode, rtx x, >    unsigned int size; >   >    /* Check all addresses are Pmode - including ILP32.  */ > -  gcc_assert (GET_MODE (x) == Pmode); > +  if (GET_MODE (x) != Pmode) > +    output_operand_lossage ("invalid address mode"); >   >    if (aarch64_classify_address (&addr, x, mode, true, type)) >      switch (addr.type) > > > 2018-02-16  Steve Ellcey   > > PR target/83335 > * gcc/testsuite/gcc.target/aarch64/asm-2.c: Add dg-error for > ILP32 mode. > * gcc/testsuite/gcc.target/aarch64/asm-4.c: New test. > > diff --git a/gcc/testsuite/gcc.target/aarch64/asm-2.c b/gcc/testsuite/gcc.target/aarch64/asm-2.c > index 3f978f5..65b3a84 100644 > --- a/gcc/testsuite/gcc.target/aarch64/asm-2.c > +++ b/gcc/testsuite/gcc.target/aarch64/asm-2.c > @@ -6,5 +6,5 @@ int x; >  void >  f (void) >  { > -  asm volatile ("%a0" :: "X" (&x)); > +  asm volatile ("%a0" :: "X" (&x)); /* { dg-error "invalid address mode" "" { target ilp32 } } */ >  } > diff --git a/gcc/testsuite/gcc.target/aarch64/asm-4.c b/gcc/testsuite/gcc.target/aarch64/asm-4.c > index e69de29..abe2af5 100644 > --- a/gcc/testsuite/gcc.target/aarch64/asm-4.c > +++ b/gcc/testsuite/gcc.target/aarch64/asm-4.c > @@ -0,0 +1,10 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O0" } */ > + > +int x; > + > +void > +f (void) > +{ > +  asm volatile ("%a0" :: "X" (__builtin_extend_pointer (&x))); > +} >