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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 12:47:41.3707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ba0b11e-b546-47eb-af72-08dbc5a14367 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8389 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 10/5/23 13:26, Richard Earnshaw wrote: > > > On 03/10/2023 16:18, Victor Do Nascimento wrote: >> Motivated by the need to print system register names in output >> assembly, this patch adds the required logic to >> `aarch64_print_operand' to accept rtxs of type CONST_STRING and >> process these accordingly. >> >> Consequently, an rtx such as: >> >>    (set (reg/i:DI 0 x0) >>           (unspec:DI [(const_string ("amcgcr_el0"))]) >> >> can now be output correctly using the following output pattern when >> composing `define_insn's: >> >>    "mrs\t%x0, %1" >> >> gcc/ChangeLog >> >>     * gcc/config/aarch64/aarch64.cc (aarch64_print_operand): Add >>     support for CONST_STRING. >> --- >>   gcc/config/aarch64/aarch64.cc | 6 ++++++ >>   1 file changed, 6 insertions(+) >> >> diff --git a/gcc/config/aarch64/aarch64.cc >> b/gcc/config/aarch64/aarch64.cc >> index dd5ac1cbc8d..d6dd0586ac1 100644 >> --- a/gcc/config/aarch64/aarch64.cc >> +++ b/gcc/config/aarch64/aarch64.cc >> @@ -12400,6 +12400,12 @@ aarch64_print_operand (FILE *f, rtx x, int code) >>         switch (GET_CODE (x)) >>       { >> +    case CONST_STRING: >> +      { >> +        const char *output_op = XSTR (x, 0); >> +        asm_fprintf (f, "%s", output_op); >> +        break; >> +      } >>       case REG: >>         if (aarch64_sve_data_mode_p (GET_MODE (x))) >>           { > > Didn't we discuss (off list) always printing out the generic register > names, so that there was less dependency on having a specific assembler > version that knows about newer sysregs? > > R. That's right, Richard. We did settle on generic register names. The example above is unfortunate and can, nay should, be amended to be less misleading. It's not wrong to say that an rtx such as >> (set (reg/i:DI 0 x0) >> (unspec:DI [(const_string ("amcgcr_el0"))]) would now be understood by the `aarch64_print_operand' function, but we'd never see that being generated as a result of this work. For "amcgcr_el0" what we'd expect to see reaching the back-end is, in fact, the following: (set (reg/i:DI 0 x0) (unspec:DI [(const_string ("s3_3_c13_c2_2"))]) Thanks for picking up on this and bringing it to my attention! V.