From: Sudakshina Das <sudi.das@arm.com>
To: Sam Tebbs <sam.tebbs@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Marcus Shawcroft <marcus.shawcroft@arm.com>
Cc: nd <nd@arm.com>, Richard Earnshaw <richard.earnshaw@arm.com>,
James Greenhalgh <james.greenhalgh@arm.com>
Subject: Re: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode
Date: Mon, 23 Jul 2018 16:01:00 -0000 [thread overview]
Message-ID: <85b58ddb-3da2-67c6-1514-e308201191d3@arm.com> (raw)
In-Reply-To: <953dbdd2-e20c-4587-3e0d-ad1a65fc93c6@arm.com>
Hi Sam
On Monday 23 July 2018 11:39 AM, Sam Tebbs wrote:
> Hi all,
>
> This patch extends the aarch64_get_lane_zero_extendsi instruction
> definition to
> also cover DI mode. This prevents a redundant AND instruction from being
> generated due to the pattern failing to be matched.
>
> Example:
>
> typedef char v16qi __attribute__ ((vector_size (16)));
>
> unsigned long long
> foo (v16qi a)
> {
> Â return a[0];
> }
>
> Previously generated:
>
> foo:
>        umov   w0, v0.b[0]
>        and    x0, x0, 255
> Â Â Â Â Â Â Â ret
>
> And now generates:
>
> foo:
>        umov   w0, v0.b[0]
> Â Â Â Â Â Â Â ret
>
> Bootstrapped on aarch64-none-linux-gnu and tested on aarch64-none-elf
> with no
> regressions.
>
> gcc/
> 2018-07-23Â Sam Tebbs <sam.tebbs@arm.com>
>
> Â Â Â Â Â Â Â * config/aarch64/aarch64-simd.md
> Â Â Â (*aarch64_get_lane_zero_extendsi<mode>):
> Â Â Â Â Â Â Â Rename to...
> (*aarch64_get_lane_zero_extend<mode><VDQQH:mode>): ... This.
> Â Â Â Â Â Â Â Use GPI iterator instead of SI mode.
>
> gcc/testsuite
> 2018-07-23Â Sam Tebbs <sam.tebbs@arm.com>
>
> Â Â Â Â Â Â Â * gcc.target/aarch64/extract_zero_extend.c: New file
>
You will need an approval from a maintainer, but I would only add one
request to this:
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 89e38e6..15fb661 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3032,15 +3032,16 @@
  [(set_attr "type" "neon_to_gp<q>")]
 )
-(define_insn "*aarch64_get_lane_zero_extendsi<mode>"
-Â [(set (match_operand:SI 0 "register_operand" "=r")
-Â Â Â (zero_extend:SI
+(define_insn "*aarch64_get_lane_zero_extend<mode><VDQQH:mode>"
+Â [(set (match_operand:GPI 0 "register_operand" "=r")
+Â Â Â (zero_extend:GPI
Since you are adding 4 new patterns with this change, could you add
more cases in your test as well to make sure you have coverage for each
of them.
Thanks
Sudi
     (vec_select:<VEL>
       (match_operand:VDQQH 1 "register_operand" "w")
       (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_SIMD"
  {
-Â Â Â operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL
(operands[2]));
+Â Â Â operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â INTVAL (operands[2]));
    return "umov\\t%w0, %1.<Vetype>[%2]";
  }
  [(set_attr "type" "neon_to_gp<q>")]
next prev parent reply other threads:[~2018-07-23 16:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-23 10:39 Sam Tebbs
2018-07-23 16:01 ` Sudakshina Das [this message]
2018-07-25 13:09 ` Sam Tebbs
2018-07-25 18:08 ` Sudakshina Das
2018-07-26 16:52 ` Sam Tebbs
2018-07-31 22:16 ` James Greenhalgh
2018-08-01 9:13 ` Sam Tebbs
2018-08-01 10:20 ` Sudakshina Das
2018-07-27 12:39 ` Sudakshina Das
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