From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 87188 invoked by alias); 23 Jul 2018 16:01:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 87177 invoked by uid 89); 23 Jul 2018 16:01:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR01-HE1-obe.outbound.protection.outlook.com Received: from mail-he1eur01on0064.outbound.protection.outlook.com (HELO EUR01-HE1-obe.outbound.protection.outlook.com) (104.47.0.64) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 23 Jul 2018 16:01:27 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wrb8jrBRuTaKSoj6Wo+jvvrk2iOTsg+SgzcZdyCaxf8=; b=f2GKqtxhyUWEy1YeV9sIhXH4obnC0GOryTiEkZN7JBC8IBxs3x7/hwtSwlzwuzSZtd86hsjILlYkKIeDvOW1mqCBl53c6wKuAEbSUpVD0Ogoy1YC93vV2+jdBnW6FsN0+BLCdzOOJvnhXEWkldRSWe1Trpze/tJmNSjTwD/lUcg= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Sudi.Das@arm.com; Received: from [10.37.12.138] (217.140.96.140) by DB6PR0801MB1719.eurprd08.prod.outlook.com (2603:10a6:4:3a::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.973.20; Mon, 23 Jul 2018 16:01:23 +0000 Subject: Re: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode To: Sam Tebbs , "gcc-patches@gcc.gnu.org" , Marcus Shawcroft Cc: nd , Richard Earnshaw , James Greenhalgh References: <953dbdd2-e20c-4587-3e0d-ad1a65fc93c6@arm.com> From: Sudakshina Das Message-ID: <85b58ddb-3da2-67c6-1514-e308201191d3@arm.com> Date: Mon, 23 Jul 2018 16:01:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <953dbdd2-e20c-4587-3e0d-ad1a65fc93c6@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Return-Path: sudi.das@arm.com Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-IsSubscribed: yes X-SW-Source: 2018-07/txt/msg01266.txt.bz2 Hi Sam On Monday 23 July 2018 11:39 AM, Sam Tebbs wrote: > Hi all, > > This patch extends the aarch64_get_lane_zero_extendsi instruction > definition to > also cover DI mode. This prevents a redundant AND instruction from being > generated due to the pattern failing to be matched. > > Example: > > typedef char v16qi __attribute__ ((vector_size (16))); > > unsigned long long > foo (v16qi a) > { >   return a[0]; > } > > Previously generated: > > foo: >         umov    w0, v0.b[0] >         and     x0, x0, 255 >         ret > > And now generates: > > foo: >         umov    w0, v0.b[0] >         ret > > Bootstrapped on aarch64-none-linux-gnu and tested on aarch64-none-elf > with no > regressions. > > gcc/ > 2018-07-23  Sam Tebbs > >         * config/aarch64/aarch64-simd.md >     (*aarch64_get_lane_zero_extendsi): >         Rename to... > (*aarch64_get_lane_zero_extend): ... This. >         Use GPI iterator instead of SI mode. > > gcc/testsuite > 2018-07-23  Sam Tebbs > >         * gcc.target/aarch64/extract_zero_extend.c: New file > You will need an approval from a maintainer, but I would only add one request to this: diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 89e38e6..15fb661 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3032,15 +3032,16 @@    [(set_attr "type" "neon_to_gp")]  ) -(define_insn "*aarch64_get_lane_zero_extendsi" -  [(set (match_operand:SI 0 "register_operand" "=r") -    (zero_extend:SI +(define_insn "*aarch64_get_lane_zero_extend" +  [(set (match_operand:GPI 0 "register_operand" "=r") +    (zero_extend:GPI Since you are adding 4 new patterns with this change, could you add more cases in your test as well to make sure you have coverage for each of them. Thanks Sudi        (vec_select:          (match_operand:VDQQH 1 "register_operand" "w")          (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]    "TARGET_SIMD"    { -    operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); +    operands[2] = aarch64_endian_lane_rtx (mode, +                       INTVAL (operands[2]));      return "umov\\t%w0, %1.[%2]";    }    [(set_attr "type" "neon_to_gp")]