You mean theadvector doesn't want the current RVV1.0 register overlap magic as follows ? The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not). The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not). If yes, I suggest disable the overlap constraint using attribute, More details you can learn from (set_attr "group_overlap" juzhe.zhong@rivai.ai 发件人： joshua 发送时间： 2023-12-22 11:33 收件人： 钟居哲; gcc-patches 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Jeff Law; Christoph Müllner; jinma; Cooper Qu 主题： 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension Hi Juzhe, Thank you for your comprehensive comments. Classifying theadvector intrinsics into 3 kinds is really important to make our patchset more organized. For 1) and 3), I will split out the patches soon and hope they will be merged quickly. For 2), according to the differences between vector and xtheadvector, it can be classfied into 3 kinds. First is renamed load/store, renamed narrowing integer right shift, renamed narrowing fixed-point clip, and etc. I think we can use ASM targethook to rewrite the whole string of the instructions, although it will still be a heavy work. Second is no pseudo instruction like vneg/vfneg. We will add these pseudo instructions in binutils to make xtheadvector more compatible with vector. Third is that destination vector register cannot overlap source vector register group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot come up with any better way than pattern copy. Do you have any suggestions? Joshua ------------------------------------------------------------------ 发件人：钟居哲 发送时间：2023年12月21日(星期四) 07:04 收件人："cooper.joshua"; "gcc-patches" 抄　送："jim.wilson.gcc"; palmer; andrew; "philipp.tomsich"; Jeff Law; "Christoph Müllner"; "cooper.joshua"; jinma; Cooper Qu 主　题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension Hi, Joshua. Thanks for working hard on clean up codes and support tons of work on theadvector. After fully review this patch, I understand you have 3 kinds of theadvector intrinsics from the codebase of current RVV1.0 GCC. 1). instructions that can leverage all current codes of RVV1.0 intrinsic with simply adding "th." prefix directly. 2). instructions that leverage current MD patterns but with some tweak and patterns copy since they are not simply added "th.". 3). new instructions that current RVV1.0 doesn't have like vlb instructions. Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out the better way to do that (Current this patch with copying patterns is not approach I like) So, I hope you can break this big patch into 3 different series patches. 1. Support partial theadvector instructions which leverage directly from current RVV1.0 with simple adding "th." prefix. 2. Support totally different name theadvector instructions but share same patterns as RVV1.0 instructions. 3. Support new headvector instructions like vlib...etc. I think 1 and 3 separate patches can be quickly merged after my more details reviewed and approved in the following patches you send like V4 ?. For 2, it's a bit more complicate, but I think we can support like ARM and other targets, use ASM targethook to rewrite the whole string of the instructions. For example, like strided load/store, you can know this instructions from attribute: (set_attr "type" "vlds") juzhe.zhong@rivai.ai From: Jun Sha (Joshua) Date: 2023-12-20 20:20 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in order not to generate instructions that xtheadvector does not support, causing 36 changes in vector.md. For the th. prefix issue, we use current_output_insn and the ASM_OUTPUT_OPCODE hook instead of directly modifying patterns in vector.md. We have run the GCC test suite and can confirm that there are no regressions. All the test results can be found in the following links, Run without xtheadvector: https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html Run with xtheadvector: https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html Furthermore, we have run the tests in https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, and all the tests passed. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner RISC-V: Refactor riscv-vector-builtins-bases.cc RISC-V: Split csr_operand in predicates.md for vector patterns RISC-V: Introduce XTheadVector as a subset of V1.0.0 RISC-V: Adds the prefix "th." for the instructions of XTheadVector RISC-V: Handle differences between XTheadvector and Vector RISC-V: Add support for xtheadvector-specific intrinsics --- gcc/common/config/riscv/riscv-common.cc | 23 + gcc/config.gcc | 4 +- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/predicates.md | 8 +- gcc/config/riscv/riscv-c.cc | 8 +- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-string.cc | 3 + gcc/config/riscv/riscv-v.cc | 13 +- .../riscv/riscv-vector-builtins-bases.cc | 18 +- .../riscv/riscv-vector-builtins-bases.h | 19 + .../riscv/riscv-vector-builtins-shapes.cc | 149 + .../riscv/riscv-vector-builtins-shapes.h | 3 + .../riscv/riscv-vector-builtins-types.def | 120 + gcc/config/riscv/riscv-vector-builtins.cc | 315 +- gcc/config/riscv/riscv-vector-builtins.h | 5 +- gcc/config/riscv/riscv-vector-switch.def | 150 +- gcc/config/riscv/riscv.cc | 46 +- gcc/config/riscv/riscv.h | 4 + gcc/config/riscv/riscv.opt | 2 + gcc/config/riscv/riscv_th_vector.h | 49 + gcc/config/riscv/t-riscv | 16 + .../riscv/thead-vector-builtins-functions.def | 659 ++++ gcc/config/riscv/thead-vector-builtins.cc | 887 ++++++ gcc/config/riscv/thead-vector-builtins.h | 123 + gcc/config/riscv/thead-vector.md | 2827 +++++++++++++++++ gcc/config/riscv/vector-iterators.md | 186 +- gcc/config/riscv/vector.md | 44 +- .../riscv/predef-__riscv_th_v_intrinsic.c | 11 + .../gcc.target/riscv/rvv/base/abi-1.c | 2 +- .../gcc.target/riscv/rvv/base/pragma-1.c | 2 +- .../gcc.target/riscv/rvv/xtheadvector.c | 13 + .../riscv/rvv/xtheadvector/prefix.c | 12 + .../riscv/rvv/xtheadvector/vlb-vsb.c | 68 + .../riscv/rvv/xtheadvector/vlbu-vsb.c | 68 + .../riscv/rvv/xtheadvector/vlh-vsh.c | 68 + .../riscv/rvv/xtheadvector/vlhu-vsh.c | 68 + .../riscv/rvv/xtheadvector/vlw-vsw.c | 68 + .../riscv/rvv/xtheadvector/vlwu-vsw.c | 68 + gcc/testsuite/lib/target-supports.exp | 12 + 39 files changed, 5931 insertions(+), 213 deletions(-) create mode 100644 gcc/config/riscv/riscv_th_vector.h create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def create mode 100644 gcc/config/riscv/thead-vector-builtins.cc create mode 100644 gcc/config/riscv/thead-vector-builtins.h create mode 100644 gcc/config/riscv/thead-vector.md create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c