From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id 20C2D3858D35 for ; Thu, 12 Jan 2023 08:15:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 20C2D3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.96,319,1665475200"; d="scan'208";a="96707533" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa1.mentor.iphmx.com with ESMTP; 12 Jan 2023 00:15:44 -0800 IronPort-SDR: fKZNI9VIvBg0H2oEMftYrs3emj9bgncwmGjIvJSu0uzy6PdEbBYs48wLeFrgGw7ztDVhQ3cXAA bqv0pKRHGzzNw+IVsXhRci9gODnqCBo0lVPT2hP7RCVCTwIVKP+pNG4GNG+LSOI97kg/MEs4eM 16938EUG4tOSi7SMJsYJVePGO3zbrQuKjP/+70xhqVy5X/r3/tI4ampY8Yt6G25fN2B5cr7Ukl 3CQbrhD2QScAVd4ZEizCfIZYvd1YZoxc5Y+//4ognjOudj3oStCzNdYxWoobai2AV+HLlZX+8E efY= From: Thomas Schwinge To: Chung-Lin Tang CC: Chung-Lin Tang , , "Tom de Vries" , Catherine Moore Subject: Re: [PATCH, nvptx, 2/2] Reimplement libgomp barriers for nvptx: bar.red instruction support in GCC In-Reply-To: <16675a67-3dd2-fc62-fd38-6eaa24da66f7@gmail.com> References: <16675a67-3dd2-fc62-fd38-6eaa24da66f7@gmail.com> User-Agent: Notmuch/0.29.3+94~g74c3f1b (https://notmuchmail.org) Emacs/28.2 (x86_64-pc-linux-gnu) Date: Thu, 12 Jan 2023 09:15:27 +0100 Message-ID: <871qo0qicg.fsf@euler.schwinge.homeip.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) To svr-ies-mbx-10.mgc.mentorg.com (139.181.222.10) X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Chung-Lin! On 2022-09-21T15:45:54+0800, Chung-Lin Tang via Gcc-patches wrote: > [...] The attached patch adds bar.red instructions to the nvptx port [...= ] I see GCC report: [...] build/genrecog [...]/source-gcc/gcc/common.md [...]/source-gcc/gcc/conf= ig/nvptx/nvptx.md \ insn-conditions.md > tmp-recog.cc [...]/source-gcc/gcc/config/nvptx/nvptx.md:2297:1: warning: source miss= ing a mode? [...]/source-gcc/gcc/config/nvptx/nvptx.md:2297:1: warning: source miss= ing a mode? [...]/source-gcc/gcc/config/nvptx/nvptx.md:2297:1: warning: source miss= ing a mode? Statistics for recog: [...] 2297 (define_insn "nvptx_barred_" 2298 [(set (match_operand: 0 "nvptx_register_operand" "= =3DR") 2299 (unspec_volatile 2300 [(match_operand:SI 1 "nvptx_nonmemory_operand" "Ri") 2301 (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri") 2302 (match_operand:SI 3 "const_int_operand" "i") 2303 (match_operand:BI 4 "nvptx_register_operand" "R")] 2304 BARRED))] 2305 "" 2306 "\\tbar.red.. \\t%0, %1, %2, %p3%4;";= " 2307 [(set_attr "predicable" "no")]) Gr=C3=BC=C3=9Fe Thomas > gcc/ChangeLog: > > * config/nvptx/nvptx.cc (nvptx_print_operand): Add 'p' > case, adjust comments. > (enum nvptx_builtins): Add NVPTX_BUILTIN_BAR_RED_AND, > NVPTX_BUILTIN_BAR_RED_OR, and NVPTX_BUILTIN_BAR_RED_POPC. > (nvptx_expand_bar_red): New function. > (nvptx_init_builtins): > Add DEFs of __builtin_nvptx_bar_red_[and/or/popc]. > (nvptx_expand_builtin): Use nvptx_expand_bar_red to expand > NVPTX_BUILTIN_BAR_RED_[AND/OR/POPC] cases. > > * config/nvptx/nvptx.md (define_c_enum "unspecv"): Add > UNSPECV_BARRED_AND, UNSPECV_BARRED_OR, and UNSPECV_BARRED_POPC. > (BARRED): New int iterator. > (barred_op,barred_mode,barred_ptxtype): New int attrs. > (nvptx_barred_): New define_insn. > diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc > index 49cc681..afc3a890 100644 > --- a/gcc/config/nvptx/nvptx.cc > +++ b/gcc/config/nvptx/nvptx.cc > @@ -2879,6 +2879,7 @@ nvptx_mem_maybe_shared_p (const_rtx x) > t -- print a type opcode suffix, promoting QImode to 32 bits > T -- print a type size in bits > u -- print a type opcode suffix without promotions. > + p -- print a '!' for constant 0. > x -- print a destination operand that may also be a bit bucket. */ > > static void > @@ -3012,6 +3013,11 @@ nvptx_print_operand (FILE *file, rtx x, int code) > fprintf (file, "@!"); > goto common; > > + case 'p': > + if (INTVAL (x) =3D=3D 0) > + fprintf (file, "!"); > + break; > + > case 'c': > mode =3D GET_MODE (XEXP (x, 0)); > switch (x_code) > @@ -6151,9 +6157,90 @@ enum nvptx_builtins > NVPTX_BUILTIN_CMP_SWAPLL, > NVPTX_BUILTIN_MEMBAR_GL, > NVPTX_BUILTIN_MEMBAR_CTA, > + NVPTX_BUILTIN_BAR_RED_AND, > + NVPTX_BUILTIN_BAR_RED_OR, > + NVPTX_BUILTIN_BAR_RED_POPC, > NVPTX_BUILTIN_MAX > }; > > +/* Expander for 'bar.red' instruction builtins. */ > + > +static rtx > +nvptx_expand_bar_red (tree exp, rtx target, > + machine_mode ARG_UNUSED (m), int ARG_UNUSED (ignore)) > +{ > + int code =3D DECL_MD_FUNCTION_CODE (TREE_OPERAND (CALL_EXPR_FN (exp), = 0)); > + machine_mode mode =3D TYPE_MODE (TREE_TYPE (exp)); > + > + if (!target) > + target =3D gen_reg_rtx (mode); > + > + rtx pred, dst; > + rtx bar =3D expand_expr (CALL_EXPR_ARG (exp, 0), > + NULL_RTX, SImode, EXPAND_NORMAL); > + rtx nthr =3D expand_expr (CALL_EXPR_ARG (exp, 1), > + NULL_RTX, SImode, EXPAND_NORMAL); > + rtx cpl =3D expand_expr (CALL_EXPR_ARG (exp, 2), > + NULL_RTX, SImode, EXPAND_NORMAL); > + rtx redop =3D expand_expr (CALL_EXPR_ARG (exp, 3), > + NULL_RTX, SImode, EXPAND_NORMAL); > + if (CONST_INT_P (bar)) > + { > + if (INTVAL (bar) < 0 || INTVAL (bar) > 15) > + { > + error_at (EXPR_LOCATION (exp), > + "barrier value must be within [0,15]"); > + return const0_rtx; > + } > + } > + else if (!REG_P (bar)) > + bar =3D copy_to_mode_reg (SImode, bar); > + > + if (!CONST_INT_P (nthr) && !REG_P (nthr)) > + nthr =3D copy_to_mode_reg (SImode, nthr); > + > + if (!CONST_INT_P (cpl)) > + { > + error_at (EXPR_LOCATION (exp), > + "complement argument must be constant"); > + return const0_rtx; > + } > + > + pred =3D gen_reg_rtx (BImode); > + if (!REG_P (redop)) > + redop =3D copy_to_mode_reg (SImode, redop); > + emit_insn (gen_rtx_SET (pred, gen_rtx_NE (BImode, redop, GEN_INT (0)))= ); > + redop =3D pred; > + > + rtx pat; > + switch (code) > + { > + case NVPTX_BUILTIN_BAR_RED_AND: > + dst =3D gen_reg_rtx (BImode); > + pat =3D gen_nvptx_barred_and (dst, bar, nthr, cpl, redop); > + break; > + case NVPTX_BUILTIN_BAR_RED_OR: > + dst =3D gen_reg_rtx (BImode); > + pat =3D gen_nvptx_barred_or (dst, bar, nthr, cpl, redop); > + break; > + case NVPTX_BUILTIN_BAR_RED_POPC: > + dst =3D gen_reg_rtx (SImode); > + pat =3D gen_nvptx_barred_popc (dst, bar, nthr, cpl, redop); > + break; > + default: > + gcc_unreachable (); > + } > + emit_insn (pat); > + if (GET_MODE (dst) =3D=3D BImode) > + { > + rtx tmp =3D gen_reg_rtx (mode); > + emit_insn (gen_rtx_SET (tmp, gen_rtx_NE (mode, dst, GEN_INT (0))))= ; > + dst =3D tmp; > + } > + emit_move_insn (target, dst); > + return target; > +} > + > static GTY(()) tree nvptx_builtin_decls[NVPTX_BUILTIN_MAX]; > > /* Return the NVPTX builtin for CODE. */ > @@ -6194,6 +6281,13 @@ nvptx_init_builtins (void) > DEF (MEMBAR_GL, "membar_gl", (VOID, VOID, NULL_TREE)); > DEF (MEMBAR_CTA, "membar_cta", (VOID, VOID, NULL_TREE)); > > + DEF (BAR_RED_AND, "bar_red_and", > + (UINT, UINT, UINT, UINT, UINT, NULL_TREE)); > + DEF (BAR_RED_OR, "bar_red_or", > + (UINT, UINT, UINT, UINT, UINT, NULL_TREE)); > + DEF (BAR_RED_POPC, "bar_red_popc", > + (UINT, UINT, UINT, UINT, UINT, NULL_TREE)); > + > #undef DEF > #undef ST > #undef UINT > @@ -6236,6 +6330,11 @@ nvptx_expand_builtin (tree exp, rtx target, rtx AR= G_UNUSED (subtarget), > emit_insn (gen_nvptx_membar_cta ()); > return NULL_RTX; > > + case NVPTX_BUILTIN_BAR_RED_AND: > + case NVPTX_BUILTIN_BAR_RED_OR: > + case NVPTX_BUILTIN_BAR_RED_POPC: > + return nvptx_expand_bar_red (exp, target, mode, ignore); > + > default: gcc_unreachable (); > } > } > diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md > index 8ed6850..740c4de 100644 > --- a/gcc/config/nvptx/nvptx.md > +++ b/gcc/config/nvptx/nvptx.md > @@ -58,6 +58,9 @@ > UNSPECV_CAS_LOCAL > UNSPECV_XCHG > UNSPECV_ST > + UNSPECV_BARRED_AND > + UNSPECV_BARRED_OR > + UNSPECV_BARRED_POPC > UNSPECV_BARSYNC > UNSPECV_WARPSYNC > UNSPECV_UNIFORM_WARP_CHECK > @@ -2274,6 +2277,35 @@ > "TARGET_PTX_6_0" > "%.\\tbar.warp.sync\\t0xffffffff;") > > +(define_int_iterator BARRED > + [UNSPECV_BARRED_AND > + UNSPECV_BARRED_OR > + UNSPECV_BARRED_POPC]) > +(define_int_attr barred_op > + [(UNSPECV_BARRED_AND "and") > + (UNSPECV_BARRED_OR "or") > + (UNSPECV_BARRED_POPC "popc")]) > +(define_int_attr barred_mode > + [(UNSPECV_BARRED_AND "BI") > + (UNSPECV_BARRED_OR "BI") > + (UNSPECV_BARRED_POPC "SI")]) > +(define_int_attr barred_ptxtype > + [(UNSPECV_BARRED_AND "pred") > + (UNSPECV_BARRED_OR "pred") > + (UNSPECV_BARRED_POPC "u32")]) > + > +(define_insn "nvptx_barred_" > + [(set (match_operand: 0 "nvptx_register_operand" "=3DR") > + (unspec_volatile > + [(match_operand:SI 1 "nvptx_nonmemory_operand" "Ri") > + (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri") > + (match_operand:SI 3 "const_int_operand" "i") > + (match_operand:BI 4 "nvptx_register_operand" "R")] > + BARRED))] > + "" > + "\\tbar.red.. \\t%0, %1, %2, %p3%4;";" > + [(set_attr "predicable" "no")]) > + > (define_insn "nvptx_uniform_warp_check" > [(unspec_volatile [(const_int 0)] UNSPECV_UNIFORM_WARP_CHECK)] > "" ----------------- Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstra=C3=9Fe 201= , 80634 M=C3=BCnchen; Gesellschaft mit beschr=C3=A4nkter Haftung; Gesch=C3= =A4ftsf=C3=BChrer: Thomas Heurung, Frank Th=C3=BCrauf; Sitz der Gesellschaf= t: M=C3=BCnchen; Registergericht M=C3=BCnchen, HRB 106955