From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 121511 invoked by alias); 9 Dec 2016 13:17:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 121495 invoked by uid 89); 9 Dec 2016 13:17:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=Expect, 6467 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Dec 2016 13:17:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88561707; Fri, 9 Dec 2016 05:17:15 -0800 (PST) Received: from localhost (e105548-lin.manchester.arm.com [10.45.32.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32CAA3F477 for ; Fri, 9 Dec 2016 05:17:15 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [37/67] Use scalar_int_mode when emitting cstores References: <87h96dp8u6.fsf@e105548-lin.cambridge.arm.com> Date: Fri, 09 Dec 2016 13:17:00 -0000 In-Reply-To: <87h96dp8u6.fsf@e105548-lin.cambridge.arm.com> (Richard Sandiford's message of "Fri, 09 Dec 2016 12:48:01 +0000") Message-ID: <871sxhjl7q.fsf@e105548-lin.cambridge.arm.com> User-Agent: Gnus/5.130012 (Ma Gnus v0.12) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2016-12/txt/msg00809.txt.bz2 cstore patterns always have a scalar integer result, which has the value 0 for "false" and STORE_FLAG_VALUE for "true". This patch makes that explicit using scalar_int_mode. gcc/ 2016-11-24 Richard Sandiford Alan Hayward David Sherwood * target.def (cstore_mode): Return a scalar_int_mode. * doc/tm.texi: Regenerate. * config/sparc/sparc.c (sparc_cstore_mode): Return a scalar_int_mode. * targhooks.h (default_cstore_mode): Likewise. * targhooks.c (default_cstore_mode): Likewise, using a forced conversion. * expmed.c (emit_cstore): Expect the target of the cstore to be a scalar_int_mode. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 28bb0c5..e152d62 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -646,7 +646,7 @@ static void sparc_print_operand_address (FILE *, machine_mode, rtx); static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t, machine_mode, secondary_reload_info *); -static machine_mode sparc_cstore_mode (enum insn_code icode); +static scalar_int_mode sparc_cstore_mode (enum insn_code icode); static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *); static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *); static unsigned int sparc_min_arithmetic_precision (void); @@ -12788,7 +12788,7 @@ sparc_modes_tieable_p (machine_mode mode1, machine_mode mode2) /* Implement TARGET_CSTORE_MODE. */ -static machine_mode +static scalar_int_mode sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED) { return (TARGET_ARCH64 ? DImode : SImode); diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 4993817..05f0719 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -2900,7 +2900,7 @@ This hook defines a class of registers which could be used for spilling pseudos This hook should return @code{true} if given class of registers should be an allocno class in any way. Usually RA uses only one register class from all classes containing the same register set. In some complicated cases, you need to have two or more such classes as allocno ones for RA correct work. Not defining this hook is equivalent to returning @code{false} for all inputs. @end deftypefn -@deftypefn {Target Hook} machine_mode TARGET_CSTORE_MODE (enum insn_code @var{icode}) +@deftypefn {Target Hook} scalar_int_mode TARGET_CSTORE_MODE (enum insn_code @var{icode}) This hook defines the machine mode to use for the boolean result of conditional store patterns. The ICODE argument is the instruction code for the cstore being performed. Not definiting this hook is the same as accepting the mode encoded into operand 0 of the cstore expander patterns. @end deftypefn diff --git a/gcc/expmed.c b/gcc/expmed.c index dea4923..3939c3d 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -5228,7 +5228,8 @@ emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, struct expand_operand ops[4]; rtx op0, comparison, subtarget; rtx_insn *last; - machine_mode result_mode = targetm.cstore_mode (icode); + scalar_int_mode result_mode = targetm.cstore_mode (icode); + scalar_int_mode int_target_mode; last = get_last_insn (); x = prepare_operand (icode, x, 2, mode, compare_mode, unsignedp); @@ -5240,9 +5241,11 @@ emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, } if (target_mode == VOIDmode) - target_mode = result_mode; + int_target_mode = result_mode; + else + int_target_mode = as_a (target_mode); if (!target) - target = gen_reg_rtx (target_mode); + target = gen_reg_rtx (int_target_mode); comparison = gen_rtx_fmt_ee (code, result_mode, x, y); @@ -5258,20 +5261,20 @@ emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, subtarget = ops[0].value; /* If we are converting to a wider mode, first convert to - TARGET_MODE, then normalize. This produces better combining + INT_TARGET_MODE, then normalize. This produces better combining opportunities on machines that have a SIGN_EXTRACT when we are testing a single bit. This mostly benefits the 68k. If STORE_FLAG_VALUE does not have the sign bit set when interpreted in MODE, we can do this conversion as unsigned, which is usually more efficient. */ - if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (result_mode)) + if (GET_MODE_SIZE (int_target_mode) > GET_MODE_SIZE (result_mode)) { convert_move (target, subtarget, val_signbit_known_clear_p (result_mode, STORE_FLAG_VALUE)); op0 = target; - result_mode = target_mode; + result_mode = int_target_mode; } else op0 = subtarget; @@ -5307,7 +5310,7 @@ emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, } /* If we were converting to a smaller mode, do the conversion now. */ - if (target_mode != result_mode) + if (int_target_mode != result_mode) { convert_move (target, op0, 0); return target; diff --git a/gcc/target.def b/gcc/target.def index fa765de..c450a1d 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -5063,7 +5063,7 @@ DEFHOOK for the cstore being performed. Not definiting this hook is the same\ as accepting the mode encoded into operand 0 of the cstore expander\ patterns.", - machine_mode, (enum insn_code icode), + scalar_int_mode, (enum insn_code icode), default_cstore_mode) /* This target hook allows the backend to compute the register pressure diff --git a/gcc/targhooks.c b/gcc/targhooks.c index 4f7744f..8951bc3 100644 --- a/gcc/targhooks.c +++ b/gcc/targhooks.c @@ -1838,10 +1838,10 @@ default_pch_valid_p (const void *data_p, size_t len) /* Default version of cstore_mode. */ -machine_mode +scalar_int_mode default_cstore_mode (enum insn_code icode) { - return insn_data[(int) icode].operand[0].mode; + return as_a (insn_data[(int) icode].operand[0].mode); } /* Default version of member_type_forces_blk. */ diff --git a/gcc/targhooks.h b/gcc/targhooks.h index 1a56ec7..151c0f0 100644 --- a/gcc/targhooks.h +++ b/gcc/targhooks.h @@ -229,7 +229,7 @@ extern const char *default_pch_valid_p (const void *, size_t); extern void default_asm_output_ident_directive (const char*); -extern machine_mode default_cstore_mode (enum insn_code); +extern scalar_int_mode default_cstore_mode (enum insn_code); extern bool default_member_type_forces_blk (const_tree, machine_mode); extern void default_atomic_assign_expand_fenv (tree *, tree *, tree *); extern tree build_va_arg_indirect_ref (tree);