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From: Richard Sandiford <richard@codesourcery.com>
To: Nigel Stephens <nigel@mips.com>
Mail-Followup-To: Nigel Stephens <nigel@mips.com>,Sandra Loosemore <sandra@codesourcery.com>,  GCC Patches <gcc-patches@gcc.gnu.org>,  Guy Morrogh <guym@mips.com>,  David Ung <davidu@mips.com>,  Thiemo Seufer <ths@mips.com>,  Mark Mitchell <mark@codesourcery.com>, richard@codesourcery.com
Cc: Sandra Loosemore <sandra@codesourcery.com>,  GCC Patches <gcc-patches@gcc.gnu.org>,  Guy Morrogh <guym@mips.com>,  David Ung <davidu@mips.com>,  Thiemo Seufer <ths@mips.com>,  Mark Mitchell <mark@codesourcery.com>
Subject: Re: PATCH: fine-tuning for can_store_by_pieces
References: <46C3343A.5080407@codesourcery.com> <87ps1nop2x.fsf@firetop.home> 	<46C778D6.5060808@codesourcery.com> <87y7g6r50c.fsf@firetop.home> 	<46CA222D.2050107@codesourcery.com> <87ps1h5mda.fsf@firetop.home> 	<46CABE2A.2090406@mips.com>
Date: Tue, 21 Aug 2007 11:53:00 -0000
In-Reply-To: <46CABE2A.2090406@mips.com> (Nigel Stephens's message of "Tue\, 21 	Aug 2007 11\:27\:54 +0100")
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Nigel Stephens <nigel@mips.com> writes:
> Richard Sandiford wrote:
>> Sandra Loosemore <sandra@codesourcery.com> writes:
>>   
>>> OK, but what I was really asking was, is there a way to *test* for
>>> situations where we should generate the lui/ori/sw sequences instead
>>> of the lw/sw?  Some combination of TARGET_foo flags and/or the size of
>>> the string?
>>>     
>>
>> Well, I suppose:
>>
>>     !optimize_size && !TARGET_MIPS16 && mips_issue_rate () > 1
>
> Many MIPS dual-issue processors are asymettric, and may be able to issue 
> lui, ori and sw down only one pipe or the other -- not both in parallel. 
> So I don't think that testing mips_issue_rate() is sufficient.

True.  I suppose I'm biased because all the processors whose schedulers
I've worked on could issue stores down one pipe and arithmetic
instructions down the other.

I assume you think we should stick the uncoditional zero here?

Richard