From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.31]) by sourceware.org (Postfix) with UTF8SMTPS id EDE5A385696A for ; Fri, 12 May 2023 06:19:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EDE5A385696A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1683872338; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=BOFvjAy0QARu90Cor20Kn4XITeDPmo+0EcMsqp+kt/g=; b=gvEOnrJ68iAJynzuQ2FKxgiFJrOEs5wbYDZMzcis+zwRtq79zQYGKyNrtFraKWUEqHiXnt aFY70r8HehV0jXw4CyeOpR2lJIn7ROoaIOkY5lk4+1YHWDdrmo00a4oNmEQf5Q5eFk5Oh9 td00WNOBNZUa1XO8HAEfflPCova8ETR+1XpXB4L0NoLr4ynszHKxcMH8SPLS1QGDQx3XkS StElWtDETPSysZcAyrzVqkc7BwP0BMOuPkWthIHMe6xC58zDzZXrEFFJe0XD6M+7+LvA8a 9pffkah5lRloC5ZAFcNQhgrPe5bhyjzGc/cbPdZp9HokdeSORb8nVD8yUU9xXQ== Mime-Version: 1.0 References: Content-Type: multipart/alternative; boundary=4317d28705d0bf74f39b98c415c1647285a4620464f91afec5176aa1e76b To: From: "Jie Mei" X-Mailer: git-send-email 2.40.1 Date: Fri, 12 May 2023 14:18:58 +0800 X-Lms-Return-Path: Content-Transfer-Encoding: 8bit Subject: [PATCH v2 8/9] MIPS: Add CACHE instruction for mips16e2 Message-Id: <873b50976b7503863a13b747f3685c8481c7ef5c.1683871682.git.jie.mei@oss.cipunited.com> In-Reply-To: X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_NUMSUBJECT,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --4317d28705d0bf74f39b98c415c1647285a4620464f91afec5176aa1e76b Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.c(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above. (AVAIL_NON_MIPS16 (cache..)): Update to AVAIL_MIPS16E2_OR_NON_MIPS16. * config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2. * config/mips/mips.md (mips_cache): Mark as extended MIPS16. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cache.c: New tests for mips16e2. --- gcc/config/mips/mips.cc | 25 ++++++++++++-- gcc/config/mips/mips.h | 3 +- gcc/config/mips/mips.md | 3 +- .../gcc.target/mips/mips16e2-cache.c | 34 +++++++++++++++++++ 4 files changed, 60 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 275efc5a390..e6f4701ad3a 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2845,6 +2845,9 @@ mips_9bit_offset_address_p (rtx x, machine_mode mode) return (mips_classify_address (&addr, x, mode, false) && addr.type =3D=3D ADDRESS_REG && CONST_INT_P (addr.offset) + && (!TARGET_MIPS16E2 + || M16_REG_P (REGNO (addr.reg)) + || REGNO (addr.reg) >=3D FIRST_PSEUDO_REGISTER) && MIPS_9BIT_OFFSET_P (INTVAL (addr.offset))); } =20 @@ -15412,9 +15415,13 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx) The function is available on the current target if !TARGET_MIPS16. =20 BUILTIN_AVAIL_MIPS16 - The function is available on the current target if TARGET_MIPS16. */ + The function is available on the current target if TARGET_MIPS16. + + BUILTIN_AVAIL_MIPS16E2 + The function is available on the current target if TARGET_MIPS16E2. */ #define BUILTIN_AVAIL_NON_MIPS16 1 #define BUILTIN_AVAIL_MIPS16 2 +#define BUILTIN_AVAIL_MIPS16E2 4 =20 /* Declare an availability predicate for built-in functions that require non-MIPS16 mode and also require COND to be true. @@ -15426,6 +15433,17 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx) return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ } =20 +/* Declare an availability predicate for built-in functions that + require non-MIPS16 mode or MIPS16E2 and also require COND to be true. + NAME is the main part of the predicate's name. */ +#define AVAIL_MIPS16E2_OR_NON_MIPS16(NAME, COND) \ + static unsigned int \ + mips_builtin_avail_##NAME (void) \ + { \ + return ((COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16E2 \ + : 0); \ + } + /* Declare an availability predicate for built-in functions that support both MIPS16 and non-MIPS16 code and also require COND to be true. NAME is the main part of the predicate's name. */ @@ -15471,7 +15489,7 @@ AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_D= SP) AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI) -AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) +AVAIL_MIPS16E2_OR_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) AVAIL_NON_MIPS16 (msa, TARGET_MSA) =20 /* Construct a mips_builtin_description from the given arguments. @@ -17471,7 +17489,8 @@ mips_expand_builtin (tree exp, rtx target, rtx subt= arget ATTRIBUTE_UNUSED, d =3D &mips_builtins[fcode]; avail =3D d->avail (); gcc_assert (avail !=3D 0); - if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16)) + if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16) + && (!TARGET_MIPS16E2 || !(avail & BUILTIN_AVAIL_MIPS16E2))) { error ("built-in function %qE not supported for MIPS16", DECL_NAME (fndecl)); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 1947be25aca..207b8871b12 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1385,7 +1385,8 @@ struct mips_cpu_info { #define TARGET_CACHE_BUILTIN (mips_isa >=3D MIPS_ISA_MIPS3) =20 /* The CACHE instruction is available. */ -#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) +#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && (!TARGET_MIPS16 \ + || TARGET_MIPS16E2)) =0C /* Tell collect what flags to pass to nm. */ #ifndef NM_FLAGS diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 5ef8d99d99c..7eb65891820 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5751,7 +5751,8 @@ (match_operand:QI 1 "address_operand" "ZD")] UNSPEC_MIPS_CACHE))] "ISA_HAS_CACHE" - "cache\t%X0,%a1") + "cache\t%X0,%a1" + [(set_attr "extended_mips16" "yes")]) =20 ;; Similar, but with the operands hard-coded to an R10K cache barrier ;; operation. We keep the pattern distinct so that we can identify diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite= /gcc.target/mips/mips16e2-cache.c new file mode 100644 index 00000000000..dcc39b580f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c @@ -0,0 +1,34 @@ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=3D32 -mips32r2 -mips16 -m= mips16e2" } */ +/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* = } { "-O0" } { "" } } */ + +/* Test cache. */ + +void +test01 (int *area) +{ + __builtin_mips_cache (20, area); +} + +void +test02 (const short *area) +{ + __builtin_mips_cache (24, area + 10); +} + +void +test03 (volatile unsigned int *area, int offset) +{ + __builtin_mips_cache (0, area + offset); +} + +void +test04 (const volatile unsigned char *area) +{ + __builtin_mips_cache (4, area - 80); +} + +/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */ +/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */ + --=20 2.40.1= --4317d28705d0bf74f39b98c415c1647285a4620464f91afec5176aa1e76b--