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[188.29.164.162]) by smtp.gmail.com with ESMTPSA id i16sm5717604wrf.19.2017.11.03.09.18.11 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Nov 2017 09:18:11 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [3/10] Add available_vector_sizes to target-supports.exp References: <87inerqqyz.fsf@linaro.org> Date: Fri, 03 Nov 2017 16:18:00 -0000 In-Reply-To: <87inerqqyz.fsf@linaro.org> (Richard Sandiford's message of "Fri, 03 Nov 2017 16:14:44 +0000") Message-ID: <874lqbqqta.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2017-11/txt/msg00216.txt.bz2 This patch adds a routine that lists the available vector sizes for a target and uses it for some existing target conditions. Later patches add more uses. The cases are taken from multiple_sizes. 2017-11-03 Richard Sandiford Alan Hayward David Sherwood gcc/testsuite/ * lib/target-supports.exp (available_vector_sizes): New proc. (check_effective_target_vect_multiple_sizes): Use it. (check_effective_target_vect64): Likewise. (check_effective_target_vect_sizes_32B_16B): Likewise. Index: gcc/testsuite/lib/target-supports.exp =================================================================== --- gcc/testsuite/lib/target-supports.exp 2017-11-03 12:16:58.605777011 +0000 +++ gcc/testsuite/lib/target-supports.exp 2017-11-03 16:06:12.625838683 +0000 @@ -6581,46 +6581,38 @@ foreach N {2 3 4 8} { }] } -# Return 1 if the target supports multiple vector sizes +# Return the list of vector sizes (in bits) that each target supports. +# A vector length of "0" indicates variable-length vectors. -proc check_effective_target_vect_multiple_sizes { } { - global et_vect_multiple_sizes_saved - global et_index - - set et_vect_multiple_sizes_saved($et_index) 0 - if { [istarget aarch64*-*-*] - || [is-effective-target arm_neon] - || (([istarget i?86-*-*] || [istarget x86_64-*-*]) - && ([check_avx_available] && ![check_prefer_avx128])) } { - set et_vect_multiple_sizes_saved($et_index) 1 +proc available_vector_sizes { } { + set result {} + if { [istarget aarch64*-*-*] } { + lappend result 128 64 + } elseif { [istarget arm*-*-*] + && [check_effective_target_arm_neon_ok] } { + lappend result 128 64 + } elseif { (([istarget i?86-*-*] || [istarget x86_64-*-*]) + && ([check_avx_available] && ![check_prefer_avx128])) } { + lappend result 256 128 + } elseif { [istarget sparc*-*-*] } { + lappend result 64 + } else { + # The traditional default asumption. + lappend result 128 } + return $result +} + +# Return 1 if the target supports multiple vector sizes - verbose "check_effective_target_vect_multiple_sizes:\ - returning $et_vect_multiple_sizes_saved($et_index)" 2 - return $et_vect_multiple_sizes_saved($et_index) +proc check_effective_target_vect_multiple_sizes { } { + return [expr { [llength [available_vector_sizes]] > 1 }] } # Return 1 if the target supports vectors of 64 bits. proc check_effective_target_vect64 { } { - global et_vect64_saved - global et_index - - if [info exists et_vect64_saved($et_index)] { - verbose "check_effective_target_vect64: using cached result" 2 - } else { - set et_vect64_saved($et_index) 0 - if { ([is-effective-target arm_neon] - && [check_effective_target_arm_little_endian]) - || [istarget aarch64*-*-*] - || [istarget sparc*-*-*] } { - set et_vect64_saved($et_index) 1 - } - } - - verbose "check_effective_target_vect64:\ - returning $et_vect64_saved($et_index)" 2 - return $et_vect64_saved($et_index) + return [expr { [lsearch -exact [available_vector_sizes] 64] >= 0 }] } # Return 1 if the target supports vector copysignf calls. @@ -7747,11 +7739,7 @@ proc check_avx_available { } { # Return true if 32- and 16-bytes vectors are available. proc check_effective_target_vect_sizes_32B_16B { } { - if { [check_avx_available] && ![check_prefer_avx128] } { - return 1; - } else { - return 0; - } + return [expr { [available_vector_sizes] == [list 256 128] }] } # Return true if 16- and 8-bytes vectors are available.