From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 86333 invoked by alias); 9 Dec 2016 13:11:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 86261 invoked by uid 89); 9 Dec 2016 13:11:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=truth X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Dec 2016 13:11:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A3104707; Fri, 9 Dec 2016 05:11:25 -0800 (PST) Received: from localhost (e105548-lin.manchester.arm.com [10.45.32.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2283D3F477 for ; Fri, 9 Dec 2016 05:11:24 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [28/67] Use is_a for miscellaneous types of test References: <87h96dp8u6.fsf@e105548-lin.cambridge.arm.com> Date: Fri, 09 Dec 2016 13:11:00 -0000 In-Reply-To: <87h96dp8u6.fsf@e105548-lin.cambridge.arm.com> (Richard Sandiford's message of "Fri, 09 Dec 2016 12:48:01 +0000") Message-ID: <874m2dl01w.fsf@e105548-lin.cambridge.arm.com> User-Agent: Gnus/5.130012 (Ma Gnus v0.12) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2016-12/txt/msg00800.txt.bz2 This patch adds is_a checks to various places that were explicitly or implicitly restricted to integers already, in cases where adding an explicit is_a is useful for later patches. In simplify_if_then_else, the: GET_MODE (XEXP (XEXP (t, 0), N)) expressions were equivalent to: GET_MODE (XEXP (t, 0)) due to the type of operation. gcc/ 2016-11-24 Richard Sandiford Alan Hayward David Sherwood * combine.c (sign_extend_short_imm): Add is_a checks. (try_combine): Likewise. (simplify_if_then_else): Likewise. * cse.c (cse_insn): Likewise. * dwarf2out.c (mem_loc_descriptor): Likewise. * emit-rtl.c (gen_lowpart_common): Likewise. * simplify-rtx.c (simplify_truncation): Likewise. (simplify_ternary_operation): Likewise. * tree-ssa-loop-ivopts.c (force_expr_to_var_cost): Likewise. diff --git a/gcc/combine.c b/gcc/combine.c index 7f943be..92b2ec9 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -1631,11 +1631,13 @@ setup_incoming_promotions (rtx_insn *first) static rtx sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec) { - if (GET_MODE_PRECISION (mode) < prec - && CONST_INT_P (src) + scalar_int_mode int_mode; + if (CONST_INT_P (src) + && is_a (mode, &int_mode) + && GET_MODE_PRECISION (int_mode) < prec && INTVAL (src) > 0 - && val_signbit_known_set_p (mode, INTVAL (src))) - src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (mode)); + && val_signbit_known_set_p (int_mode, INTVAL (src))) + src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode)); return src; } @@ -3150,6 +3152,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1); machine_mode compare_mode, orig_compare_mode; enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN; + scalar_int_mode mode; newpat = PATTERN (i3); newpat_dest = SET_DEST (newpat); @@ -3160,8 +3163,9 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, &cc_use_insn))) { compare_code = orig_compare_code = GET_CODE (*cc_use_loc); - compare_code = simplify_compare_const (compare_code, - GET_MODE (i2dest), op0, &op1); + if (is_a (GET_MODE (i2dest), &mode)) + compare_code = simplify_compare_const (compare_code, mode, + op0, &op1); target_canonicalize_comparison (&compare_code, &op0, &op1, 1); } @@ -6263,7 +6267,7 @@ simplify_if_then_else (rtx x) int i; enum rtx_code false_code; rtx reversed; - scalar_int_mode int_mode; + scalar_int_mode int_mode, inner_mode; /* Simplify storing of the truth value. */ if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) @@ -6458,7 +6462,7 @@ simplify_if_then_else (rtx x) rtx cond_op0 = XEXP (cond, 0); rtx cond_op1 = XEXP (cond, 1); enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; - machine_mode m = int_mode; + scalar_int_mode m = int_mode; rtx z = 0, c1 = NULL_RTX; if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS @@ -6475,6 +6479,7 @@ simplify_if_then_else (rtx x) && rtx_equal_p (XEXP (t, 1), f)) c1 = XEXP (t, 0), op = GET_CODE (t), z = f; else if (GET_CODE (t) == SIGN_EXTEND + && is_a (GET_MODE (XEXP (t, 0)), &inner_mode) && (GET_CODE (XEXP (t, 0)) == PLUS || GET_CODE (XEXP (t, 0)) == MINUS || GET_CODE (XEXP (t, 0)) == IOR @@ -6488,13 +6493,14 @@ simplify_if_then_else (rtx x) && (num_sign_bit_copies (f, GET_MODE (f)) > (unsigned int) (GET_MODE_PRECISION (int_mode) - - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0)))))) + - GET_MODE_PRECISION (inner_mode)))) { c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); extend_op = SIGN_EXTEND; - m = GET_MODE (XEXP (t, 0)); + m = inner_mode; } else if (GET_CODE (t) == SIGN_EXTEND + && is_a (GET_MODE (XEXP (t, 0)), &inner_mode) && (GET_CODE (XEXP (t, 0)) == PLUS || GET_CODE (XEXP (t, 0)) == IOR || GET_CODE (XEXP (t, 0)) == XOR) @@ -6504,13 +6510,14 @@ simplify_if_then_else (rtx x) && (num_sign_bit_copies (f, GET_MODE (f)) > (unsigned int) (GET_MODE_PRECISION (int_mode) - - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1)))))) + - GET_MODE_PRECISION (inner_mode)))) { c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); extend_op = SIGN_EXTEND; - m = GET_MODE (XEXP (t, 0)); + m = inner_mode; } else if (GET_CODE (t) == ZERO_EXTEND + && is_a (GET_MODE (XEXP (t, 0)), &inner_mode) && (GET_CODE (XEXP (t, 0)) == PLUS || GET_CODE (XEXP (t, 0)) == MINUS || GET_CODE (XEXP (t, 0)) == IOR @@ -6523,14 +6530,15 @@ simplify_if_then_else (rtx x) && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) && ((nonzero_bits (f, GET_MODE (f)) - & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) + & ~GET_MODE_MASK (inner_mode)) == 0)) { c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); extend_op = ZERO_EXTEND; - m = GET_MODE (XEXP (t, 0)); + m = inner_mode; } else if (GET_CODE (t) == ZERO_EXTEND + && is_a (GET_MODE (XEXP (t, 0)), &inner_mode) && (GET_CODE (XEXP (t, 0)) == PLUS || GET_CODE (XEXP (t, 0)) == IOR || GET_CODE (XEXP (t, 0)) == XOR) @@ -6539,12 +6547,12 @@ simplify_if_then_else (rtx x) && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) && ((nonzero_bits (f, GET_MODE (f)) - & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) + & ~GET_MODE_MASK (inner_mode)) == 0)) { c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); extend_op = ZERO_EXTEND; - m = GET_MODE (XEXP (t, 0)); + m = inner_mode; } if (z) diff --git a/gcc/cse.c b/gcc/cse.c index e3fda8e..2f29062 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -4878,13 +4878,14 @@ cse_insn (rtx_insn *insn) value. */ if (flag_expensive_optimizations && ! src_related + && is_a (mode, &int_mode) && GET_CODE (src) == AND && CONST_INT_P (XEXP (src, 1)) - && GET_MODE_SIZE (mode) < UNITS_PER_WORD) + && GET_MODE_SIZE (int_mode) < UNITS_PER_WORD) { machine_mode tmode; rtx new_and = gen_rtx_AND (VOIDmode, NULL_RTX, XEXP (src, 1)); - FOR_EACH_WIDER_MODE (tmode, mode) + FOR_EACH_WIDER_MODE (tmode, int_mode) { if (GET_MODE_SIZE (tmode) > UNITS_PER_WORD) break; @@ -4905,7 +4906,7 @@ cse_insn (rtx_insn *insn) if (REG_P (larger_elt->exp)) { src_related - = gen_lowpart (mode, larger_elt->exp); + = gen_lowpart (int_mode, larger_elt->exp); break; } diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 7bf210d..0b8b12d 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -14626,31 +14626,29 @@ mem_loc_descriptor (rtx rtl, machine_mode mode, case SIGN_EXTEND: case ZERO_EXTEND: - if (!is_a (mode, &int_mode)) + if (!is_a (mode, &int_mode) + || !is_a (GET_MODE (XEXP (rtl, 0)), &inner_mode)) break; - op0 = mem_loc_descriptor (XEXP (rtl, 0), GET_MODE (XEXP (rtl, 0)), + op0 = mem_loc_descriptor (XEXP (rtl, 0), inner_mode, mem_mode, VAR_INIT_STATUS_INITIALIZED); if (op0 == 0) break; else if (GET_CODE (rtl) == ZERO_EXTEND && GET_MODE_SIZE (int_mode) <= DWARF2_ADDR_SIZE - && GET_MODE_BITSIZE (GET_MODE (XEXP (rtl, 0))) - < HOST_BITS_PER_WIDE_INT + && GET_MODE_BITSIZE (inner_mode) < HOST_BITS_PER_WIDE_INT /* If DW_OP_const{1,2,4}u won't be used, it is shorter to expand zero extend as two shifts instead of masking. */ - && GET_MODE_SIZE (GET_MODE (XEXP (rtl, 0))) <= 4) + && GET_MODE_SIZE (inner_mode) <= 4) { - machine_mode imode = GET_MODE (XEXP (rtl, 0)); mem_loc_result = op0; add_loc_descr (&mem_loc_result, - int_loc_descriptor (GET_MODE_MASK (imode))); + int_loc_descriptor (GET_MODE_MASK (inner_mode))); add_loc_descr (&mem_loc_result, new_loc_descr (DW_OP_and, 0, 0)); } else if (GET_MODE_SIZE (int_mode) <= DWARF2_ADDR_SIZE) { - int shift = DWARF2_ADDR_SIZE - - GET_MODE_SIZE (GET_MODE (XEXP (rtl, 0))); + int shift = DWARF2_ADDR_SIZE - GET_MODE_SIZE (inner_mode); shift *= BITS_PER_UNIT; if (GET_CODE (rtl) == SIGN_EXTEND) op = DW_OP_shra; @@ -14667,7 +14665,7 @@ mem_loc_descriptor (rtx rtl, machine_mode mode, dw_die_ref type_die1, type_die2; dw_loc_descr_ref cvt; - type_die1 = base_type_for_mode (GET_MODE (XEXP (rtl, 0)), + type_die1 = base_type_for_mode (inner_mode, GET_CODE (rtl) == ZERO_EXTEND); if (type_die1 == NULL) break; @@ -15212,14 +15210,15 @@ mem_loc_descriptor (rtx rtl, machine_mode mode, if (CONST_INT_P (XEXP (rtl, 1)) && CONST_INT_P (XEXP (rtl, 2)) && is_a (mode, &int_mode) + && is_a (GET_MODE (XEXP (rtl, 0)), &inner_mode) + && GET_MODE_SIZE (int_mode) <= DWARF2_ADDR_SIZE + && GET_MODE_SIZE (inner_mode) <= DWARF2_ADDR_SIZE && ((unsigned) INTVAL (XEXP (rtl, 1)) + (unsigned) INTVAL (XEXP (rtl, 2)) - <= GET_MODE_BITSIZE (int_mode)) - && GET_MODE_SIZE (int_mode) <= DWARF2_ADDR_SIZE - && GET_MODE_SIZE (GET_MODE (XEXP (rtl, 0))) <= DWARF2_ADDR_SIZE) + <= GET_MODE_BITSIZE (int_mode))) { int shift, size; - op0 = mem_loc_descriptor (XEXP (rtl, 0), GET_MODE (XEXP (rtl, 0)), + op0 = mem_loc_descriptor (XEXP (rtl, 0), inner_mode, mem_mode, VAR_INIT_STATUS_INITIALIZED); if (op0 == 0) break; @@ -15231,8 +15230,7 @@ mem_loc_descriptor (rtx rtl, machine_mode mode, size = INTVAL (XEXP (rtl, 1)); shift = INTVAL (XEXP (rtl, 2)); if (BITS_BIG_ENDIAN) - shift = GET_MODE_BITSIZE (GET_MODE (XEXP (rtl, 0))) - - shift - size; + shift = GET_MODE_BITSIZE (inner_mode) - shift - size; if (shift + size != (int) DWARF2_ADDR_SIZE) { add_loc_descr (&mem_loc_result, diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c index 569a478..9fbd7a2 100644 --- a/gcc/emit-rtl.c +++ b/gcc/emit-rtl.c @@ -1408,9 +1408,11 @@ gen_lowpart_common (machine_mode mode, rtx x) if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) return 0; + scalar_int_mode int_mode, int_innermode, from_mode; if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) - && (GET_MODE_CLASS (mode) == MODE_INT - || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) + && is_a (mode, &int_mode) + && is_a (innermode, &int_innermode) + && is_a (GET_MODE (XEXP (x, 0)), &from_mode)) { /* If we are getting the low-order part of something that has been sign- or zero-extended, we can either just use the object being @@ -1420,12 +1422,12 @@ gen_lowpart_common (machine_mode mode, rtx x) This case is used mostly by combine and cse. */ - if (GET_MODE (XEXP (x, 0)) == mode) + if (from_mode == int_mode) return XEXP (x, 0); - else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) - return gen_lowpart_common (mode, XEXP (x, 0)); - else if (msize < xsize) - return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); + else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (from_mode)) + return gen_lowpart_common (int_mode, XEXP (x, 0)); + else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode)) + return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0)); } else if (GET_CODE (x) == SUBREG || REG_P (x) || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index 854d026..ac7cb24 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -808,21 +808,22 @@ simplify_truncation (machine_mode mode, rtx op, if the MEM has a mode-dependent address. */ if ((GET_CODE (op) == LSHIFTRT || GET_CODE (op) == ASHIFTRT) + && is_a (mode, &int_mode) && is_a (op_mode, &int_op_mode) && MEM_P (XEXP (op, 0)) && CONST_INT_P (XEXP (op, 1)) - && (INTVAL (XEXP (op, 1)) % GET_MODE_BITSIZE (mode)) == 0 + && INTVAL (XEXP (op, 1)) % GET_MODE_BITSIZE (int_mode) == 0 && INTVAL (XEXP (op, 1)) > 0 && INTVAL (XEXP (op, 1)) < GET_MODE_BITSIZE (int_op_mode) && ! mode_dependent_address_p (XEXP (XEXP (op, 0), 0), MEM_ADDR_SPACE (XEXP (op, 0))) && ! MEM_VOLATILE_P (XEXP (op, 0)) - && (GET_MODE_SIZE (mode) >= UNITS_PER_WORD + && (GET_MODE_SIZE (int_mode) >= UNITS_PER_WORD || WORDS_BIG_ENDIAN == BYTES_BIG_ENDIAN)) { - int byte = subreg_lowpart_offset (mode, int_op_mode); + int byte = subreg_lowpart_offset (int_mode, int_op_mode); int shifted_bytes = INTVAL (XEXP (op, 1)) / BITS_PER_UNIT; - return adjust_address_nv (XEXP (op, 0), mode, + return adjust_address_nv (XEXP (op, 0), int_mode, (WORDS_BIG_ENDIAN ? byte - shifted_bytes : byte + shifted_bytes)); @@ -2975,19 +2976,21 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode, is (lt foo (const_int 0)), so we can perform the above simplification if STORE_FLAG_VALUE is 1. */ - if (STORE_FLAG_VALUE == 1 + if (is_a (mode, &int_mode) + && STORE_FLAG_VALUE == 1 && trueop1 == const1_rtx && GET_CODE (op0) == LSHIFTRT && CONST_INT_P (XEXP (op0, 1)) - && INTVAL (XEXP (op0, 1)) == GET_MODE_PRECISION (mode) - 1) - return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx); + && INTVAL (XEXP (op0, 1)) == GET_MODE_PRECISION (int_mode) - 1) + return gen_rtx_GE (int_mode, XEXP (op0, 0), const0_rtx); /* (xor (comparison foo bar) (const_int sign-bit)) when STORE_FLAG_VALUE is the sign bit. */ - if (val_signbit_p (mode, STORE_FLAG_VALUE) + if (is_a (mode, &int_mode) + && val_signbit_p (int_mode, STORE_FLAG_VALUE) && trueop1 == const_true_rtx && COMPARISON_P (op0) - && (reversed = reversed_comparison (op0, mode))) + && (reversed = reversed_comparison (op0, int_mode))) return reversed; tem = simplify_byte_swapping_operation (code, mode, op0, op1); @@ -3407,17 +3410,17 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode, return op0; /* Optimize (lshiftrt (clz X) C) as (eq X 0). */ if (GET_CODE (op0) == CLZ + && is_a (GET_MODE (XEXP (op0, 0)), &inner_mode) && CONST_INT_P (trueop1) && STORE_FLAG_VALUE == 1 && INTVAL (trueop1) < (HOST_WIDE_INT)width) { - machine_mode imode = GET_MODE (XEXP (op0, 0)); unsigned HOST_WIDE_INT zero_val = 0; - if (CLZ_DEFINED_VALUE_AT_ZERO (imode, zero_val) - && zero_val == GET_MODE_PRECISION (imode) + if (CLZ_DEFINED_VALUE_AT_ZERO (inner_mode, zero_val) + && zero_val == GET_MODE_PRECISION (inner_mode) && INTVAL (trueop1) == exact_log2 (zero_val)) - return simplify_gen_relational (EQ, mode, imode, + return simplify_gen_relational (EQ, mode, inner_mode, XEXP (op0, 0), const0_rtx); } goto canonicalize_shift; @@ -5260,7 +5263,9 @@ simplify_const_relational_operation (enum rtx_code code, } /* Optimize integer comparisons with zero. */ - if (trueop1 == const0_rtx && !side_effects_p (trueop0)) + if (is_a (mode, &int_mode) + && trueop1 == const0_rtx + && !side_effects_p (trueop0)) { /* Some addresses are known to be nonzero. We don't know their sign, but equality comparisons are known. */ @@ -5279,7 +5284,7 @@ simplify_const_relational_operation (enum rtx_code code, rtx inner_const = avoid_constant_pool_reference (XEXP (op0, 1)); if (CONST_INT_P (inner_const) && inner_const != const0_rtx) { - int sign_bitnum = GET_MODE_PRECISION (mode) - 1; + int sign_bitnum = GET_MODE_PRECISION (int_mode) - 1; int has_sign = (HOST_BITS_PER_WIDE_INT >= sign_bitnum && (UINTVAL (inner_const) & (HOST_WIDE_INT_1U @@ -5415,13 +5420,9 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode, machine_mode op0_mode, rtx op0, rtx op1, rtx op2) { - unsigned int width = GET_MODE_PRECISION (mode); bool any_change = false; rtx tem, trueop2; - - /* VOIDmode means "infinite" precision. */ - if (width == 0) - width = HOST_BITS_PER_WIDE_INT; + scalar_int_mode int_mode, int_op0_mode; switch (code) { @@ -5455,17 +5456,20 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode, if (CONST_INT_P (op0) && CONST_INT_P (op1) && CONST_INT_P (op2) - && ((unsigned) INTVAL (op1) + (unsigned) INTVAL (op2) <= width) - && width <= (unsigned) HOST_BITS_PER_WIDE_INT) + && is_a (mode, &int_mode) + && INTVAL (op1) + INTVAL (op2) <= GET_MODE_PRECISION (int_mode)) { /* Extracting a bit-field from a constant */ unsigned HOST_WIDE_INT val = UINTVAL (op0); HOST_WIDE_INT op1val = INTVAL (op1); HOST_WIDE_INT op2val = INTVAL (op2); - if (BITS_BIG_ENDIAN) - val >>= GET_MODE_PRECISION (op0_mode) - op2val - op1val; - else + if (!BITS_BIG_ENDIAN) val >>= op2val; + else if (is_a (op0_mode, &int_op0_mode)) + val >>= GET_MODE_PRECISION (int_op0_mode) - op2val - op1val; + else + /* Not enough information to calculate the bit position. */ + break; if (HOST_BITS_PER_WIDE_INT != op1val) { @@ -5478,7 +5482,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode, val |= ~ ((HOST_WIDE_INT_1U << op1val) - 1); } - return gen_int_mode (val, mode); + return gen_int_mode (val, int_mode); } break; diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c index 00b287a..3653586 100644 --- a/gcc/tree-ssa-loop-ivopts.c +++ b/gcc/tree-ssa-loop-ivopts.c @@ -4336,6 +4336,7 @@ force_expr_to_var_cost (tree expr, bool speed) tree op0, op1; comp_cost cost0, cost1, cost; machine_mode mode; + scalar_int_mode int_mode; if (!costs_initialized) { @@ -4452,8 +4453,9 @@ force_expr_to_var_cost (tree expr, bool speed) mult = op0; if (mult != NULL_TREE + && is_a (mode, &int_mode) && cst_and_fits_in_hwi (TREE_OPERAND (mult, 1)) - && get_shiftadd_cost (expr, mode, cost0, cost1, mult, + && get_shiftadd_cost (expr, int_mode, cost0, cost1, mult, speed, &sa_cost)) return sa_cost; }