From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) by sourceware.org (Postfix) with ESMTPS id 1771F3858409 for ; Fri, 21 Jul 2023 14:05:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1771F3858409 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=oracle.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oracle.com Received: from pps.filterd (m0246629.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36LCoH83016202 for ; Fri, 21 Jul 2023 14:05:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=references : from : to : cc : subject : in-reply-to : date : message-id : content-type : mime-version; s=corp-2023-03-30; bh=xwJ5vnqwfxnCsJ9afJnmwS52Om+XTj8UDG0cA0oEaQ4=; b=iBfF3+c9L5mvUkhObAI1fnC3kXCjnoihD7Tk9yimSwxxUwI3gzyDzbNKiJRfbFtuJZrE xL35rV4mylyk+BcQPvY/KwSby6Bl+Ox1Ws8Zhe6h3x67Lfti9uvJy/zXxxVEu9X2zCpg hzo92ctS1qwyH1hSyInJNQxr3/QlNUwB1pfLCGb7FL5d4bbPzKrubQSUbPlKAB55J/YA fqOs5sEPrpm4u9iUrxd4QX58ugBfkGv8HxRonsp0wdiRrZSCTm8Pt4QHhjh3YbD9Sl1K 8dL0gmviARaRsZ3mYSpP4RgVK4lpjxmEf1/eLjxxaxDB6I9n3+OESXcHRyARUPT4bkZw FQ== Received: from iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta03.appoci.oracle.com [130.35.103.27]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3run783xt3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 21 Jul 2023 14:05:56 +0000 Received: from pps.filterd (iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 36LCAwtn023859 for ; Fri, 21 Jul 2023 14:05:55 GMT Received: from nam10-mw2-obe.outbound.protection.outlook.com (mail-mw2nam10lp2105.outbound.protection.outlook.com [104.47.55.105]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTPS id 3ruhwa9xxt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 21 Jul 2023 14:05:54 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bgf1EkUwtbCKZLPomgz6Oxv+AnovA0+t0IPTWHNps3CdXEtGv6ifYNbAl+5RFBVPOTfyQASCUx1Tk/3kQ7q7v04VGFGWrcm5iifnkwzIa//rFWH/YoVCG5Nbzkt6DviNN9P6YERVKOYf78WmEpxOnQ1s0hyjBm5jXQPu0tHWuFslW6TeopaK1qMovzIWr9XucW0mfUz9Ho8JlVMe+0xcCCYIBeaBx7kDGI6sEMKIdcxO+ZFbcJBH+sWD5yflSBC6MZABJGNWlKfTiE3B74Bxq40hBWGAqq/l8rpbV7lS1nxRO2i+iQuL+OxAI9+GSjBYjXU3rD0PD3EksnIOEWbFVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xwJ5vnqwfxnCsJ9afJnmwS52Om+XTj8UDG0cA0oEaQ4=; b=Vcugj85sDe1E//2+EhRRBk5uGJPnWhd8P+s4FO1kx5kr3x+gqH7Ml/OHlk+X/DrA7055i+bsQDtBi7Aqf+zgnlRGblJ8pfRjRxYHVpbPvc9WkAbAnjw2XCojx2379rBTuKDFoGWEPyu79u8WMWyUpynpKU99StNoI/qpOict0G/MHOXj1UUnK3NNzb8C2Ye1mRUXQhpsZC9fF4i5qtQD9303XcJGq1Ang4OYG8fTy2enxGvWBZxmRnMSaqt6tPB5EXcanKZ5pVxWNRMS4u7B5LMw1sZYdY0jBfzn5HfdYFnup/ZT4m2d5RK3ijmcbkRCDcsmtfZukR3YX0A8lTnIWg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com; dkim=pass header.d=oracle.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.onmicrosoft.com; s=selector2-oracle-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xwJ5vnqwfxnCsJ9afJnmwS52Om+XTj8UDG0cA0oEaQ4=; b=P0HDG0XV0ZWY0MkWOhUW6wWZ9it+klQNRcfE9W38bl661eDYA2r00F3uEZS/LEAnfU3rqnETI7lqb1tE69x+WLRkV70CJYRxqyFBWM7Ptln0TIkisXM9w6ZRFSqiDTESCPfBRzrvlOHriMogQbj5ah2Aesyo+yQrDczp1OYSU94= Received: from BN6PR1001MB2340.namprd10.prod.outlook.com (2603:10b6:405:30::36) by CH0PR10MB4922.namprd10.prod.outlook.com (2603:10b6:610:c6::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.28; Fri, 21 Jul 2023 14:05:50 +0000 Received: from BN6PR1001MB2340.namprd10.prod.outlook.com ([fe80::7514:36d6:fdf2:4313]) by BN6PR1001MB2340.namprd10.prod.outlook.com ([fe80::7514:36d6:fdf2:4313%6]) with mapi id 15.20.6609.026; Fri, 21 Jul 2023 14:05:50 +0000 References: <20230721114835.23667-1-cupertino.miranda@oracle.com> <87y1j98l8n.fsf@oracle.com> User-agent: mu4e 1.4.15; emacs 28.1 From: Cupertino Miranda To: "Jose E. Marchesi" Cc: gcc-patches@gcc.gnu.org, elena.zannoni@oracle.com, david.faust@oracle.com Subject: Re: [PATCH v2] bpf: pseudo-c assembly dialect support In-reply-to: <87y1j98l8n.fsf@oracle.com> Date: Fri, 21 Jul 2023 15:05:40 +0100 Message-ID: <875y6d5phn.fsf@oracle.com> Content-Type: multipart/mixed; boundary="=-=-=" X-ClientProxiedBy: SI2PR02CA0012.apcprd02.prod.outlook.com (2603:1096:4:194::7) To BN6PR1001MB2340.namprd10.prod.outlook.com (2603:10b6:405:30::36) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN6PR1001MB2340:EE_|CH0PR10MB4922:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b4e119e-eef3-4a5b-68a6-08db89f39693 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2GJSr8fT+Yt4/fmh9yDbYKxzYzuybCtGBfMov6hVMtbs3VUufr26wIUP+5MJ1qlAv6RKANmcfVVcd+Ip8sUao3wsSYXdnJiveZkMZ+AM6w0lqruxD/8cNpSxmsz9Q/oR8QGXJmiLsmgbIe9u7rgBPhylHvRNaJHHEO30b4xPfizE/uNKhdVGCSu4i9EgG7Mmha23w/S/kDM/AlS21fu8KW3kUBs8HvIbVCyQXi+TMPUgCbefJEvxH6XQwuzlcyxkcos+Hvan6i9ZGa2xuyYAb87BAU7kd3gbp54yCCNt4Pxg/HR/8yBFO+tIZujRnPiRFEITd6c5Y+0/RX6lNxGDz8S/pAmE5p0BRtxIpCb2Xfa8QO0clsCSE77F5CP5dq4PSZeCRwCy6gPBRVBx7HwQboa8R6isJ8NIjfgKkUU0Z5cK3bo0sPJkgzEWrbV7VBcXXdW37YuZadXf1B8omfvoeBO8R/5ZA1j9AuhclJrr6BhrAUCHdF4nJinh1I1fHRLiZy8xs8DHgh/pny5gRZYN3NGxj5+xzAhq2hyjRT/xtlrSNhfIxaz0D3JDtJlt+DpHWRgNm9DHQe5xi5IpM+MHWXpmnCIZ9T4aOcaU6l9CMbk1qelAfyUFqpnj5yRMOF9B X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN6PR1001MB2340.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(366004)(376002)(136003)(396003)(39860400002)(346002)(451199021)(6636002)(316002)(2616005)(4326008)(41300700001)(6512007)(37006003)(66556008)(6486002)(478600001)(6666004)(186003)(66476007)(66946007)(6506007)(107886003)(53546011)(30864003)(86362001)(2906002)(36756003)(83380400001)(6862004)(8676002)(5660300002)(8936002)(38100700002)(44832011)(334744004);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?glYdpmgTOBxpohRusn4knmr+MyrBM1L5ywFbZiJ5sh5q7Rd87Yrf2w4+QtDS?= =?us-ascii?Q?zb3lb//tqVTawwUPIZvun6ZqEYTvCjoorRg/Ie8lyfHjec3YlyeTAGoo8PlH?= =?us-ascii?Q?M9WaDpA4vyc0oPUO/IxZfrGum6vFzo0vMSAGiB3I1RlmqTozjKHqEza5ScFg?= =?us-ascii?Q?6a8jM2+h+h7CHLRymPMHrY3h7bFKXVSbzEIGZajucuwUHG7VmLKLqrVjzHQW?= =?us-ascii?Q?mNhImhvhPGH3S53b/j30Kaeccr9eSUnDkmZmKydW7bC18Df7kpA2DgVJXW/f?= =?us-ascii?Q?fZecLYhD0g0E7JpUmOOlCIUbCmdfpwJgx0m+Oo1TofDAsZlewqiKKqNYrnfw?= =?us-ascii?Q?HfMiqADTY/ot23cNb78F9t/X/IiwiyyJFVqmPD4ZGBf3d9On6IpIU2W3ouDz?= =?us-ascii?Q?Y6ywfeLWrir/duwISr6/n5mGNdoQgPrXQfbyRdiy5Ld3RWEJg5XF8K5rK7nf?= =?us-ascii?Q?XKWl0j3Yxom0O4OeIPFpu77b2H78wjfkYmfShxqnvjV94y6sAmUcQVIkeeVI?= =?us-ascii?Q?pFis61pOMLup+o4VXGzPeDwkA5UgHlUa026E5SruIfMG2lElEOh8RneuDQX1?= =?us-ascii?Q?3SC/Sv/xCalHj9Iuq8xVq2kjDp3q2eVuXVruh5aqkpEM0yTvUR9rIlEK7tFZ?= =?us-ascii?Q?lwmVbIWrhrEfLbuWClOvaJteMWkk4c7PCKOxQzdklx1ev65C+My5mKx5043D?= =?us-ascii?Q?jnG6h4Ucrle0GwNXmphLudJeXasOua8B+yuJ4KqfkTE01l2XmLVqMu6sfBD6?= =?us-ascii?Q?sV++DPrbTbo/jdMRKWK+feoS3SWHvqGKHtLeoefqZ49wyaGWXSFFB17ucyYj?= =?us-ascii?Q?JN1mSstURqo5n7tId7kPVYrCmXdRqM3JzW1j1GaGX1Tona9xH22Nn4vsUp7n?= =?us-ascii?Q?k/BE3OtQDOlHByTt/rLm2uTGgdS0DaNnm9s0NX6FLRSegR2Vh7SMAQ2kuc1F?= =?us-ascii?Q?86jEUvpnJvxQ3kaJ7XyasjH+Gj1nns4sgETftKUnrCbzj6Wsf3XpaqGEnZ8d?= =?us-ascii?Q?jyUakHaw6r9uRFkR120wHT9ptZMkkcmlCTqnPlaMjXIrrKOOAHLRybqEpImQ?= =?us-ascii?Q?cfTOtz0Lg05SIQrt3bcSpFWjV2jWOBdZDO4Ho0je4dPokTe0iuAkAveKazEx?= =?us-ascii?Q?SjqFoykm564t2WLQq70ViGIMAU7qWcacVi4MvlGrQ1p862L7OnBR63Qv5Z44?= =?us-ascii?Q?jyXjMEgvuG+MdnVPWeMfpthj2Tip/TOK1Ev64s5ZYbEgutBZiIw7lzDw2p+w?= =?us-ascii?Q?qH0DHbhgK59KuKf0qwoi9azVGL78Mu5d3nHr8BosISkCr01jgeeUyJVtRQRe?= =?us-ascii?Q?shaxMYC+LUB51x2IumMLntVeTsJfh51h72RJzGc66aB3xO9DNbukNtsJlMcV?= =?us-ascii?Q?Jq3iuHhPfBTLVffOpCpTRSA0xURTI8svfTsUfLMO8kCuJgqm3jKsn3SZQ67y?= =?us-ascii?Q?PPVMTZHdOJFMqVD39IUFm8oMpHl/+VCj1VXHPdc45LMlJSzz/Fq4aXwqldFE?= =?us-ascii?Q?JEOAhnbtJB+OgQJDZK3IuUVNnLHunyAisublMULyRyfUqfrqFa8YM3iWaELg?= =?us-ascii?Q?vryI8XPaNnxQJOsBqxcBBC3pNIpyXSA+n5KkmMZwPJ2qLGXfua0H6iK1VV5J?= =?us-ascii?Q?NJ77lNSjj9XqmAfsorVohAY=3D?= X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: TKWTS8qAReG0qbY6ygGjTz2TutMac3XvGVEnf8fwFK8IBbHidC7hmBdEpORihMu4CpXobglaD6oPqVU78w7aIlnlDyLJ9eoiSHFIjEMCQu8F7GetUV73YflhRhzJMp09N5KKXURukcAW5rtu+vu7Zku8ASfgUKr060ImpOD5h51be/bb5Y91tDTgYC5anHA43U06FPFoG8b70QUc4XPM0Ta0FazyzCnayzMeRmv6QAGrWtERVzZT7Tz0B2hNDSQ+shvG5r0uPs1AwaazMyeojh98ruoo9OPR5AAnnR0dM/dWiCISbxShxOgicwMYN3QX5/O6QRMmSqc3Ky1CWIt8knR2NiRTsi1srn44BlMTY5Qhyg1ab6Q1C0Z5u3bHdDpFq/UUSCRGEiLQk0RfvY/YjQUA+WBABbiddsW5bDfu5vx3MAEoUdkcseUVBhGntwvS5JwG2UGjUYUJshymdp6CVESXe0mjGeX+RKnQJfpwZ+4kaStZYJxLot0fooce1heLoAUGfxBCG6JPVXqK0TMHv16wmQp6TbCWq2iSy3Nh6x/xxogdx99W4RbBQ2tFMExN58pJXPmZk9xiy3kJquGXsw70aJ5710HdolWB8jbHa83jxSfEyelDmufh+qAX3HKtvlkVCavKQ+yrTE1lcLkYHhBrxvgiImytkIzIMC03XRU43SGCjxFy56CVYJ1oSOGNdewbM+PVT2zx9CSXSPjOTTXCmDf9hMbGxOocRmTNYD3ERiwV8Y2nlG2qeV7xUt8d X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4b4e119e-eef3-4a5b-68a6-08db89f39693 X-MS-Exchange-CrossTenant-AuthSource: BN6PR1001MB2340.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2023 14:05:50.3443 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Bsa1+FJzjnehoN3n8G7X4ZRccrxu9Nyjj6Dqzxf/R0Urn3GfBR9RkkHxqm2sadAuwlY0NhDMbM+SIUOj2Aq4pmqc9Rtg65grTVqrJ+mUK0M= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR10MB4922 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_08,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210127 X-Proofpoint-GUID: IIPxmLW8yJIxossxTs4m28jrf-3nVnnz X-Proofpoint-ORIG-GUID: IIPxmLW8yJIxossxTs4m28jrf-3nVnnz X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --=-=-= Content-Type: text/plain Hi Jose, Thanks for the review. New patch is inline attached. Regards, Cupertino Jose E. Marchesi writes: > Hello Cuper. > > Thanks for the patch. > > We will need an update for the "eBPF Options" section in the GCC manual, > documenting -masm=@var{dialect} and the supported values. Can you > please add it and re-submit? > > >> Hi everyone, >> >> Looking forward to all your reviews. >> >> Best regards, >> Cupertino --=-=-= Content-Type: text/x-diff Content-Disposition: inline; filename=v2-0001-bpf-pseudo-c-assembly-dialect-support.patch >From fa227fefd84e6eaaf8edafed698e9960d7b115e6 Mon Sep 17 00:00:00 2001 From: Cupertino Miranda Date: Mon, 17 Jul 2023 17:42:42 +0100 Subject: [PATCH v2] bpf: pseudo-c assembly dialect support New pseudo-c BPF assembly dialect already supported by clang and widely used in the linux kernel. gcc/ChangeLog: * config/bpf/bpf.opt: Added option -masm=. * config/bpf/bpf-opts.h: Likewize. * config/bpf/bpf.cc: Changed it to conform with new pseudoc dialect support. * config/bpf/bpf.h: Likewise. * config/bpf/bpf.md: Added pseudo-c templates. * doc/invoke.texi: (-masm=DIALECT) New eBPF option item. --- gcc/config/bpf/bpf-opts.h | 6 +++ gcc/config/bpf/bpf.cc | 46 ++++++++++++++++--- gcc/config/bpf/bpf.h | 5 +- gcc/config/bpf/bpf.md | 97 ++++++++++++++++++++------------------- gcc/config/bpf/bpf.opt | 14 ++++++ gcc/doc/invoke.texi | 21 ++++++++- 6 files changed, 133 insertions(+), 56 deletions(-) diff --git a/gcc/config/bpf/bpf-opts.h b/gcc/config/bpf/bpf-opts.h index 8282351cf045..92db01ec4d54 100644 --- a/gcc/config/bpf/bpf-opts.h +++ b/gcc/config/bpf/bpf-opts.h @@ -60,4 +60,10 @@ enum bpf_isa_version ISA_V3, }; +enum bpf_asm_dialect +{ + ASM_NORMAL, + ASM_PSEUDOC +}; + #endif /* ! BPF_OPTS_H */ diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index e0324e1e0e08..1d3936871d60 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -873,16 +873,47 @@ bpf_output_call (rtx target) return ""; } +/* Print register name according to assembly dialect. + In normal syntax registers are printed like %rN where N is the + register number. + In pseudoc syntax, the register names do not feature a '%' prefix. + Additionally, the code 'w' denotes that the register should be printed + as wN instead of rN, where N is the register number, but only when the + value stored in the operand OP is 32-bit wide. */ +static void +bpf_print_register (FILE *file, rtx op, int code) +{ + if(asm_dialect == ASM_NORMAL) + fprintf (file, "%s", reg_names[REGNO (op)]); + else + { + if (code == 'w' && GET_MODE (op) == SImode) + { + if (REGNO (op) == BPF_FP) + fprintf (file, "w10"); + else + fprintf (file, "w%s", reg_names[REGNO (op)]+2); + } + else + { + if (REGNO (op) == BPF_FP) + fprintf (file, "r10"); + else + fprintf (file, "%s", reg_names[REGNO (op)]+1); + } + } +} + /* Print an instruction operand. This function is called in the macro PRINT_OPERAND defined in bpf.h */ void -bpf_print_operand (FILE *file, rtx op, int code ATTRIBUTE_UNUSED) +bpf_print_operand (FILE *file, rtx op, int code) { switch (GET_CODE (op)) { case REG: - fprintf (file, "%s", reg_names[REGNO (op)]); + bpf_print_register (file, op, code); break; case MEM: output_address (GET_MODE (op), XEXP (op, 0)); @@ -936,7 +967,9 @@ bpf_print_operand_address (FILE *file, rtx addr) switch (GET_CODE (addr)) { case REG: - fprintf (file, "[%s+0]", reg_names[REGNO (addr)]); + fprintf (file, asm_dialect == ASM_NORMAL ? "[" : "("); + bpf_print_register (file, addr, 0); + fprintf (file, asm_dialect == ASM_NORMAL ? "+0]" : "+0)"); break; case PLUS: { @@ -945,9 +978,11 @@ bpf_print_operand_address (FILE *file, rtx addr) if (GET_CODE (op0) == REG && GET_CODE (op1) == CONST_INT) { - fprintf (file, "[%s+", reg_names[REGNO (op0)]); + fprintf (file, asm_dialect == ASM_NORMAL ? "[" : "("); + bpf_print_register (file, op0, 0); + fprintf (file, "+"); output_addr_const (file, op1); - fputs ("]", file); + fprintf (file, asm_dialect == ASM_NORMAL ? "]" : ")"); } else fatal_insn ("invalid address in operand", addr); @@ -1816,7 +1851,6 @@ handle_attr_preserve (function *fn) } } - /* This pass finds accesses to structures marked with the BPF target attribute __attribute__((preserve_access_index)). For every such access, a CO-RE relocation record is generated, to be output in the .BTF.ext section. */ diff --git a/gcc/config/bpf/bpf.h b/gcc/config/bpf/bpf.h index 344aca02d1bb..9561bf59b800 100644 --- a/gcc/config/bpf/bpf.h +++ b/gcc/config/bpf/bpf.h @@ -22,7 +22,8 @@ /**** Controlling the Compilation Driver. */ -#define ASM_SPEC "%{mbig-endian:-EB} %{!mbig-endian:-EL} %{mxbpf:-mxbpf}" +#define ASM_SPEC "%{mbig-endian:-EB} %{!mbig-endian:-EL} %{mxbpf:-mxbpf} " \ + "%{masm=pseudoc:-mdialect=pseudoc}" #define LINK_SPEC "%{mbig-endian:-EB} %{!mbig-endian:-EL}" #define LIB_SPEC "" #define STARTFILE_SPEC "" @@ -503,4 +504,6 @@ enum reg_class #define DO_GLOBAL_DTORS_BODY \ do { } while (0) +#define ASSEMBLER_DIALECT ((int) asm_dialect) + #endif /* ! GCC_BPF_H */ diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md index f6be0a212345..0b8f409db687 100644 --- a/gcc/config/bpf/bpf.md +++ b/gcc/config/bpf/bpf.md @@ -77,6 +77,8 @@ (define_mode_attr mop [(QI "b") (HI "h") (SI "w") (DI "dw") (SF "w") (DF "dw")]) +(define_mode_attr smop [(QI "u8") (HI "u16") (SI "u32") (DI "u64") + (SF "u32") (DF "u64")]) (define_mode_attr mtype [(SI "alu32") (DI "alu")]) (define_mode_attr msuffix [(SI "32") (DI "")]) @@ -110,7 +112,7 @@ (plus:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" " r,I")))] "1" - "add\t%0,%2" + "{add\t%0,%2|%w0 += %w1}" [(set_attr "type" "")]) ;;; Subtraction @@ -123,15 +125,15 @@ (minus:AM (match_operand:AM 1 "register_operand" " 0") (match_operand:AM 2 "register_operand" " r")))] "" - "sub\t%0,%2" + "{sub\t%0,%2|%w0 -= %w1}" [(set_attr "type" "")]) ;;; Negation (define_insn "neg2" - [(set (match_operand:AM 0 "register_operand" "=r") - (neg:AM (match_operand:AM 1 "register_operand" " 0")))] + [(set (match_operand:AM 0 "register_operand" "=r,r") + (neg:AM (match_operand:AM 1 "reg_or_imm_operand" " r,I")))] "" - "neg\t%0" + "{neg\t%0,%1|%w0 = -%w1}" [(set_attr "type" "")]) ;;; Multiplication @@ -140,7 +142,7 @@ (mult:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" " r,I")))] "" - "mul\t%0,%2" + "{mul\t%0,%2|%w0 *= %w2}" [(set_attr "type" "")]) (define_insn "*mulsidi3_zeroextend" @@ -149,7 +151,7 @@ (mult:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "reg_or_imm_operand" "r,I"))))] "" - "mul32\t%0,%2" + "{mul32\t%0,%2|%w0 *= %w2}" [(set_attr "type" "alu32")]) ;;; Division @@ -162,7 +164,7 @@ (udiv:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" "r,I")))] "" - "div\t%0,%2" + "{div\t%0,%2|%w0 /= %w2}" [(set_attr "type" "")]) ;; However, xBPF does provide a signed division operator, sdiv. @@ -172,7 +174,7 @@ (div:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" "r,I")))] "TARGET_XBPF" - "sdiv\t%0,%2" + "{sdiv\t%0,%2|%w0 s/= %w2}" [(set_attr "type" "")]) ;;; Modulus @@ -185,7 +187,7 @@ (umod:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" "r,I")))] "" - "mod\t%0,%2" + "{mod\t%0,%2|%w0 %%= %w2}" [(set_attr "type" "")]) ;; Again, xBPF provides a signed version, smod. @@ -195,7 +197,7 @@ (mod:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" "r,I")))] "TARGET_XBPF" - "smod\t%0,%2" + "{smod\t%0,%2|%w0 s%%= %w2}" [(set_attr "type" "")]) ;;; Logical AND @@ -204,7 +206,7 @@ (and:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" "r,I")))] "" - "and\t%0,%2" + "{and\t%0,%2|%w0 &= %w2}" [(set_attr "type" "")]) ;;; Logical inclusive-OR @@ -213,7 +215,7 @@ (ior:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" "r,I")))] "" - "or\t%0,%2" + "{or\t%0,%2|%w0 %|= %w2}" [(set_attr "type" "")]) ;;; Logical exclusive-OR @@ -222,7 +224,7 @@ (xor:AM (match_operand:AM 1 "register_operand" " 0,0") (match_operand:AM 2 "reg_or_imm_operand" "r,I")))] "" - "xor\t%0,%2" + "{xor\t%0,%2|%w0 ^= %w2}" [(set_attr "type" "")]) ;;;; Conversions @@ -245,9 +247,9 @@ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "0,r,q")))] "" "@ - and\t%0,0xffff - mov\t%0,%1\;and\t%0,0xffff - ldxh\t%0,%1" + {and\t%0,0xffff|%0 &= 0xffff} + {mov\t%0,%1\;and\t%0,0xffff|%0 = %1;%0 &= 0xffff} + {ldxh\t%0,%1|%0 = *(u16 *) %1}" [(set_attr "type" "alu,alu,ldx")]) (define_insn "zero_extendqidi2" @@ -255,9 +257,9 @@ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "0,r,q")))] "" "@ - and\t%0,0xff - mov\t%0,%1\;and\t%0,0xff - ldxb\t%0,%1" + {and\t%0,0xff|%0 &= 0xff} + {mov\t%0,%1\;and\t%0,0xff|%0 = %1;%0 &= 0xff} + {ldxh\t%0,%1|%0 = *(u8 *) %1}" [(set_attr "type" "alu,alu,ldx")]) (define_insn "zero_extendsidi2" @@ -266,8 +268,8 @@ (match_operand:SI 1 "nonimmediate_operand" "r,q")))] "" "@ - * return bpf_has_alu32 ? \"mov32\t%0,%1\" : \"mov\t%0,%1\;and\t%0,0xffffffff\"; - ldxw\t%0,%1" + * return bpf_has_alu32 ? \"{mov32\t%0,%1|%0 = %1}\" : \"{mov\t%0,%1\;and\t%0,0xffffffff|%0 = %1;%0 &= 0xffffffff}\"; + {ldxw\t%0,%1|%0 = *(u32 *) %1}" [(set_attr "type" "alu,ldx")]) ;;; Sign-extension @@ -306,11 +308,11 @@ (match_operand:MM 1 "mov_src_operand" " q,rI,B,r,I"))] "" "@ - ldx\t%0,%1 - mov\t%0,%1 - lddw\t%0,%1 - stx\t%0,%1 - st\t%0,%1" + {ldx\t%0,%1|%0 = *( *) %1} + {mov\t%0,%1|%0 = %1} + {lddw\t%0,%1|%0 = %1 ll} + {stx\t%0,%1|*( *) %0 = %1} + {st\t%0,%1|*( *) %0 = %1}" [(set_attr "type" "ldx,alu,alu,stx,st")]) ;;;; Shifts @@ -322,7 +324,7 @@ (ashiftrt:SIM (match_operand:SIM 1 "register_operand" " 0,0") (match_operand:SIM 2 "reg_or_imm_operand" " r,I")))] "" - "arsh\t%0,%2" + "{arsh\t%0,%2|%w0 s>>= %w2}" [(set_attr "type" "")]) (define_insn "ashl3" @@ -330,7 +332,7 @@ (ashift:SIM (match_operand:SIM 1 "register_operand" " 0,0") (match_operand:SIM 2 "reg_or_imm_operand" " r,I")))] "" - "lsh\t%0,%2" + "{lsh\t%0,%2|%w0 <<= %w2}" [(set_attr "type" "")]) (define_insn "lshr3" @@ -338,7 +340,7 @@ (lshiftrt:SIM (match_operand:SIM 1 "register_operand" " 0,0") (match_operand:SIM 2 "reg_or_imm_operand" " r,I")))] "" - "rsh\t%0,%2" + "{rsh\t%0,%2|%w0 >>= %w2}" [(set_attr "type" "")]) ;;;; Endianness conversion @@ -352,9 +354,9 @@ "" { if (TARGET_BIG_ENDIAN) - return "endle\t%0, "; + return "{endle\t%0, |%0 = le %0}"; else - return "endbe\t%0, "; + return "{endbe\t%0, |%0 = be %0}"; } [(set_attr "type" "end")]) @@ -393,16 +395,16 @@ switch (code) { - case EQ: return "jeq\t%0,%1,%2"; break; - case NE: return "jne\t%0,%1,%2"; break; - case LT: return "jslt\t%0,%1,%2"; break; - case LE: return "jsle\t%0,%1,%2"; break; - case GT: return "jsgt\t%0,%1,%2"; break; - case GE: return "jsge\t%0,%1,%2"; break; - case LTU: return "jlt\t%0,%1,%2"; break; - case LEU: return "jle\t%0,%1,%2"; break; - case GTU: return "jgt\t%0,%1,%2"; break; - case GEU: return "jge\t%0,%1,%2"; break; + case EQ: return "{jeq\t%0,%1,%2|if %w0 == %w1 goto %2}"; break; + case NE: return "{jne\t%0,%1,%2|if %w0 != %w1 goto %2}"; break; + case LT: return "{jslt\t%0,%1,%2|if %w0 s< %w1 goto %2}"; break; + case LE: return "{jsle\t%0,%1,%2|if %w0 s<= %w1 goto %2}"; break; + case GT: return "{jsgt\t%0,%1,%2|if %w0 s> %w1 goto %2}"; break; + case GE: return "{jsge\t%0,%1,%2|if %w0 s>= %w1 goto %2}"; break; + case LTU: return "{jlt\t%0,%1,%2|if %w0 < %w1 goto %2}"; break; + case LEU: return "{jle\t%0,%1,%2|if %w0 <= %w1 goto %2}"; break; + case GTU: return "{jgt\t%0,%1,%2|if %w0 > %w1 goto %2}"; break; + case GEU: return "{jge\t%0,%1,%2|if %w0 >= %w1 goto %2}"; break; default: gcc_unreachable (); return ""; @@ -416,7 +418,7 @@ [(set (pc) (label_ref (match_operand 0 "" "")))] "" - "ja\t%0" + "{ja\t%0|goto %0}" [(set_attr "type" "jmp")]) ;;;; Function prologue/epilogue @@ -495,13 +497,14 @@ ;; operands[2] is next_arg_register ;; operands[3] is struct_value_size_rtx. "" - "ja\t%0" + "{ja\t%0|goto %0}" [(set_attr "type" "jmp")]) ;;;; Non-generic load instructions (define_mode_iterator LDM [QI HI SI DI]) (define_mode_attr ldop [(QI "b") (HI "h") (SI "w") (DI "dw")]) +(define_mode_attr pldop [(QI "u8") (HI "u16") (SI "u32") (DI "u64")]) (define_insn "ldind" [(set (reg:LDM R0_REGNUM) @@ -513,7 +516,7 @@ (clobber (reg:DI R3_REGNUM)) (clobber (reg:DI R4_REGNUM))] "" - "ldind\t%0,%1" + "{ldind\t%0,%1|r0 = *( *) skb[%0 + %1]}" [(set_attr "type" "ld")]) (define_insn "ldabs" @@ -526,7 +529,7 @@ (clobber (reg:DI R3_REGNUM)) (clobber (reg:DI R4_REGNUM))] "" - "ldabs\t%0" + "{ldabs\t%0|r0 = *( *) skb[%0]}" [(set_attr "type" "ld")]) ;;;; Atomic increments @@ -541,5 +544,5 @@ (match_operand:SI 2 "const_int_operand")] ;; Memory model. UNSPEC_XADD))] "" - "xadd\t%0,%1" + "{xadd\t%0,%1|*( *) %0 += %1}" [(set_attr "type" "xadd")]) diff --git a/gcc/config/bpf/bpf.opt b/gcc/config/bpf/bpf.opt index fe3ad355e4bd..ff805f9e083c 100644 --- a/gcc/config/bpf/bpf.opt +++ b/gcc/config/bpf/bpf.opt @@ -160,3 +160,17 @@ Enum(bpf_isa) String(v2) Value(ISA_V2) EnumValue Enum(bpf_isa) String(v3) Value(ISA_V3) + +masm= +Target RejectNegative Joined Var(asm_dialect) Enum(asm_dialect) Init(ASM_NORMAL) +Use given assembler dialect. + +Enum +Name(asm_dialect) Type(enum bpf_asm_dialect) +Known assembler dialects (for use with the -masm= option) + +EnumValue +Enum(asm_dialect) String(normal) Value(ASM_NORMAL) + +EnumValue +Enum(asm_dialect) String(pseudoc) Value(ASM_PSEUDOC) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3063e71c8906..b3be65d3efae 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -946,8 +946,8 @@ Objective-C and Objective-C++ Dialects}. @emph{eBPF Options} @gccoptlist{-mbig-endian -mlittle-endian -mkernel=@var{version} --mframe-limit=@var{bytes} -mxbpf -mco-re -mno-co-re --mjmpext -mjmp32 -malu32 -mcpu=@var{version}} +-mframe-limit=@var{bytes} -mxbpf -mco-re -mno-co-re -mjmpext +-mjmp32 -malu32 -mcpu=@var{version} -masm=@var{dialect>}} @emph{FR30 Options} @gccoptlist{-msmall-model -mno-lsim} @@ -24736,6 +24736,23 @@ the restrictions imposed by the BPF architecture: @item Save and restore callee-saved registers at function entry and exit, respectively. @end itemize + +@opindex masm=@var{dialect} +@item -masm=@var{dialect} +Outputs assembly instructions using eBPF selected @var{dialect}. The default +is @samp{normal}. + +Supported values for @var{dialect} are: + +@table @samp +@item normal +Outputs normal assembly dialect. + +@item pseudoc +Outputs pseudo-c assembly dialect. + +@end table + @end table @node FR30 Options -- 2.38.1 --=-=-=--