From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id AB468385482C for ; Fri, 21 Oct 2022 09:36:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AB468385482C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.95,200,1661846400"; d="scan'208";a="85162479" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa4.mentor.iphmx.com with ESMTP; 21 Oct 2022 01:36:11 -0800 IronPort-SDR: OKIRlcmTsWXAvsjxTs5IPhoUMo0q5QsbgHbmZnS88J4khXVwosaeuE4BYGZMdmkD3RzHQW8OO4 tTna51Mlwncoq6ww3azIdZLKATeR5jGg+i8GdTepOpaS+Gd8xIsyPVgVSQ7uhxeVTPs2gn8be7 lAi6Krp9A2TofpuZg0IORLbnuArTn8GCtGoOfxjiOk3ZsDx5mAJfRtZnaeN3LKGALoDJ2hHCFc CmE83jdg4Jbd8VZzNO85sVCr65KHT9x45rAXsWJOBmirktdSnd0iGr49TrTlxYdBmVrQ4dFlzf esI= From: Thomas Schwinge To: Aldy Hernandez , CC: Tom de Vries Subject: Restore 'libgomp.oacc-c-c++-common/nvptx-sese-1.c' SESE regions checking [PR107195, PR107344] (was: [COMMITTED] [PR107195] Set range to zero when nonzero mask is 0.) In-Reply-To: <878rlej3o6.fsf@euler.schwinge.homeip.net> References: <20221011083137.336470-1-aldyh@redhat.com> <878rlej3o6.fsf@euler.schwinge.homeip.net> User-Agent: Notmuch/0.29.3+94~g74c3f1b (https://notmuchmail.org) Emacs/27.1 (x86_64-pc-linux-gnu) Date: Fri, 21 Oct 2022 11:36:00 +0200 Message-ID: <875ygdh62n.fsf@euler.schwinge.homeip.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-12.mgc.mentorg.com (139.181.222.12) To svr-ies-mbx-10.mgc.mentorg.com (139.181.222.10) X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,GIT_PATCH_0,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi! On 2022-10-17T09:43:37+0200, I wrote: > On 2022-10-11T10:31:37+0200, Aldy Hernandez via Gcc-patches wrote: >> When solving 0 =3D _15 & 1, we calculate _15 as: >> >> [irange] int [-INF, -2][0, +INF] NONZERO 0xfffffffe >> >> The known value of _15 is [0, 1] NONZERO 0x1 which is intersected with >> the above, yielding: >> >> [0, 1] NONZERO 0x0 >> >> This eventually gets copied to a _Bool [0, 1] NONZERO 0x0. >> >> This is problematic because here we have a bool which is zero, but >> returns false for irange::zero_p, since the latter does not look at >> nonzero bits. This causes logical_combine to assume the range is >> not-zero, and all hell breaks loose. >> >> I think we should just normalize a nonzero mask of 0 to [0, 0] at >> creation, thus avoiding all this. > > 1. This commit r13-3217-gc4d15dddf6b9eacb36f535807ad2ee364af46e04 > "[PR107195] Set range to zero when nonzero mask is 0" broke a GCC/nvptx > offloading test case: > > UNSUPPORTED: libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-sese-1= .c -DACC_DEVICE_TYPE_nvidia=3D1 -DACC_MEM_SHARED=3D0 -foffload=3Dnvptx-none= -O0 > PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-sese-1.c -DAC= C_DEVICE_TYPE_nvidia=3D1 -DACC_MEM_SHARED=3D0 -foffload=3Dnvptx-none -O2 = (test for excess errors) > PASS: libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-sese-1.c -DAC= C_DEVICE_TYPE_nvidia=3D1 -DACC_MEM_SHARED=3D0 -foffload=3Dnvptx-none -O2 = execution test > [-PASS:-]{+FAIL:+} libgomp.oacc-c/../libgomp.oacc-c-c++-common/nvptx-= sese-1.c -DACC_DEVICE_TYPE_nvidia=3D1 -DACC_MEM_SHARED=3D0 -foffload=3Dnvpt= x-none -O2 scan-nvptx-none-offload-rtl-dump mach "SESE regions:.* [0-9]+= {[0-9]+->[0-9]+(\\.[0-9]+)+}" > > Same for C++. > > I'll later send a patch (for the test case!) to fix that up. Pushed to master branch commit a9de836c2b22f878cff592b96e11c1b95d4d36ee "Restore 'libgomp.oacc-c-c++-common/nvptx-sese-1.c' SESE regions checking [= PR107195, PR107344]", see attached. That discussion I suppose is to be continued in "GCC/nvptx SESE region optimization". Gr=C3=BC=C3=9Fe Thomas >> PR tree-optimization/107195 >> >> gcc/ChangeLog: >> >> * value-range.cc (irange::set_range_from_nonzero_bits): Set range >> to [0,0] when nonzero mask is 0. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.dg/tree-ssa/pr107195-1.c: New test. >> * gcc.dg/tree-ssa/pr107195-2.c: New test. >> --- >> gcc/testsuite/gcc.dg/tree-ssa/pr107195-1.c | 15 +++++++++++++++ >> gcc/testsuite/gcc.dg/tree-ssa/pr107195-2.c | 16 ++++++++++++++++ >> gcc/value-range.cc | 5 +++++ >> 3 files changed, 36 insertions(+) >> create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr107195-1.c >> create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr107195-2.c >> >> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr107195-1.c b/gcc/testsuite/= gcc.dg/tree-ssa/pr107195-1.c >> new file mode 100644 >> index 00000000000..a0c20dbd4b1 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr107195-1.c >> @@ -0,0 +1,15 @@ >> +// { dg-do run } >> +// { dg-options "-O1 -fno-tree-ccp" } >> + >> +int a, b; >> +int main() { >> + int c =3D 0; >> + if (a) >> + c =3D 1; >> + c =3D 1 & (a && c) && b; >> + if (a) { >> + b =3D c; >> + __builtin_abort (); >> + } >> + return 0; >> +} >> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr107195-2.c b/gcc/testsuite/= gcc.dg/tree-ssa/pr107195-2.c >> new file mode 100644 >> index 00000000000..d447c78bdd3 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr107195-2.c >> @@ -0,0 +1,16 @@ >> +// { dg-do run } >> +// { dg-options "-O1" } >> + >> +int a, b; >> +int main() { >> + int c =3D 0; >> + long d; >> + for (; b < 1; b++) { >> + (c && d) & 3 || a; >> + d =3D c; >> + c =3D -1; >> + if (d) >> + __builtin_abort(); >> + } >> + return 0; >> +} >> diff --git a/gcc/value-range.cc b/gcc/value-range.cc >> index a14f9bc4394..e07d2aa9a5b 100644 >> --- a/gcc/value-range.cc >> +++ b/gcc/value-range.cc >> @@ -2903,6 +2903,11 @@ irange::set_range_from_nonzero_bits () >> } >> return true; >> } >> + else if (popcount =3D=3D 0) >> + { >> + set_zero (type ()); >> + return true; >> + } >> return false; >> } >> >> -- >> 2.37.3 > > > From dc4644dcef05a1f21a9ebc194689f31412811387 Mon Sep 17 00:00:00 2001 > From: Thomas Schwinge > Date: Mon, 17 Oct 2022 09:10:03 +0200 > Subject: [PATCH] Add 'c-c++-common/torture/pr107195-1.c' [PR107195] > > ... to display optimization performed as of recent > commit r13-3217-gc4d15dddf6b9eacb36f535807ad2ee364af46e04 > "[PR107195] Set range to zero when nonzero mask is 0". > > PR tree-optimization/107195 > gcc/testsuite/ > * c-c++-common/torture/pr107195-1.c: New. > --- > .../c-c++-common/torture/pr107195-1.c | 41 +++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 gcc/testsuite/c-c++-common/torture/pr107195-1.c > > diff --git a/gcc/testsuite/c-c++-common/torture/pr107195-1.c b/gcc/testsu= ite/c-c++-common/torture/pr107195-1.c > new file mode 100644 > index 000000000000..1e201c1f5e6c > --- /dev/null > +++ b/gcc/testsuite/c-c++-common/torture/pr107195-1.c > @@ -0,0 +1,41 @@ > +/* Inspired by 'libgomp.oacc-c-c++-common/nvptx-sese-1.c'. */ > + > +/* { dg-additional-options -fdump-tree-optimized-raw } > + { dg-skip-if {} { *-*-* } { {-flto -fno-fat-lto-objects} } { } } */ > + > +#if 1 > +extern int > +__attribute__((const)) > +foo (int); > +#else > +int > +__attribute__((noinline)) > +foo (int x) > +{ > + return x & 2; > +} > +#endif > + > +int f (int r) > +{ > + if (foo (r)) /* If this first 'if' holds... */ > + r *=3D 2; /* ..., 'r' now has a zero-value lower-most bit... */ > + > + if (r & 1) /* ..., so this second 'if' can never hold... */ > + { /* ..., so this is unreachable. */ > +#if 1 > + /* In constrast, if the first 'if' does not hold ('foo (r) =3D=3D = 0'), the > + second 'if' may hold, but we know ('foo' being 'const') that > + 'foo (r) =3D=3D 0', so don't have to re-evaluate it here: */ > + r +=3D foo (r); > + /* Thus, if optimizing, we only ever expect one call of 'foo'. > + { dg-final { scan-tree-dump-times {gimple_call + { dg-final { scan-tree-dump-times {gimple_call + */ > +#else > + r +=3D foo (-r); > +#endif > + } > + > + return r; > +} > -- > 2.35.1 ----------------- Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstra=C3=9Fe 201= , 80634 M=C3=BCnchen; Gesellschaft mit beschr=C3=A4nkter Haftung; Gesch=C3= =A4ftsf=C3=BChrer: Thomas Heurung, Frank Th=C3=BCrauf; Sitz der Gesellschaf= t: M=C3=BCnchen; Registergericht M=C3=BCnchen, HRB 106955